CN103050533A - 用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺 - Google Patents

用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺 Download PDF

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CN103050533A
CN103050533A CN2012102934007A CN201210293400A CN103050533A CN 103050533 A CN103050533 A CN 103050533A CN 2012102934007 A CN2012102934007 A CN 2012102934007A CN 201210293400 A CN201210293400 A CN 201210293400A CN 103050533 A CN103050533 A CN 103050533A
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fin
fins
finfet
moulding
etching
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CN103050533B (zh
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万幸仁
叶凌彦
施启元
林以唐
张智胜
刘继文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置，包括：具有成型鳍和规则鳍的鳍式场效晶体管(FinFET)。成型鳍的顶部可以小于、大于、薄于、或短于规则鳍的顶部。成型鳍的底部和规则鳍的底部相同。FinFET可以具有仅一个或多个成型鳍、一个或多个规则鳍、或成型鳍和规则鳍的混合。将一个鳍成型的半导体制造工艺包括：形成一个鳍的光刻开口，可选地掺杂鳍的一部分，以及蚀刻鳍的一部分。本发明还提供了一种用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺。

Description

用于三维晶体管应用的采用等离子体掺杂和蚀刻的选择性鳍成形工艺
技术领域
本发明一般地涉及集成电路器件，更具体地来说，涉及形成鳍式场效晶体管(fin field-effect transistors，FinFET)的结构和方法。
背景技术
在快速发展的半导体制造业，互补金属氧化物半导体(complementarymetal oxide semiconductor，CMOS)FinFET器件可用于很多逻辑和其他应用中，并且集成为各种不同类型的半导体器件。FinFET器件通常包括高纵横比的半导体鳍，在该半导体鳍中形成有晶体管的沟道和源极/漏极区域。沿着半导体鳍的一部分的侧面并在其上形成栅极。在FinFET器件内，沟道和源极/漏极区域的表面积增加使得半导体晶体管器件更快、更可靠并且更好控制。
通过计算机辅助设计(computed-aided design，CAD)层来限定每个FinFET的边界开始应用于FinFET结构，新式的先进设计应运而生。由于制造工艺发展，出现越来越小的技术节点，原本采用较大技术节点设计的器件可以从采用较小技术节点制造中受益，如提高了性能和效率，并且减小了管芯的尺寸。同样，原本采用平面晶体管设计的器件也可以通过采用FinFET器件制造获益。然而，因为应用于平面结构布局的设计规则和应用于FinFET器件布局的设计规则不同，所以手工实现器件由平面布局到FinFET器件布局的转换部分是资源高度密集的过程，可能无异于创建新设计。对于已经使用平面晶体管制造的产品，要寻求形成至少与平面晶体管电气等效的FinFET器件的转换方法。因此，要继续寻求自动将旧的平面结构布局转换为FinFET结构布局的改进方法。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种装置，包括：半导体衬底；以及多个鳍式场效晶体管(FinFET)，位于所述衬底上，所述FinFET具有至少一个鳍；其中，所述多个FinFET中的至少一个包括至少一个成型鳍。
在该装置中，所述至少一个成型鳍小于相同FinFET的其他鳍。
在该装置中，所述至少一个成型鳍是不邻近设置的两个或多个鳍。
在该装置中，所述至少一个成型鳍的一部分比相同FinFET的其他鳍更薄。
在该装置中，所述至少一个成型鳍大于相同FinFET的其他鳍。
在该装置中，所述多个FinFET中的至少一个的一部分是单鳍FinFET。
在该装置中，所述多个FinFET中的至少一个的一部分包括至少一个第一形状的成型鳍，所述多个FinFET的至少一个的另一部分包括至少一个第二形状的成型鳍，并且其中，所述第一形状和所述第二形状不同。
在该装置中，所述至少一个成型鳍具有倾斜侧壁。
根据本发明的另一方面，提供了一种鳍式场效晶体管(FinFET)，包括：半导体衬底；多个鳍，位于所述衬底上，包括一个或多个规则鳍和一个或多个成型鳍，其中，所述规则鳍和所述成型鳍的顶部形状不同；以及氧化层，位于所述半导体衬底上，嵌入所述多个鳍的底部，其中，所述多个鳍的嵌入底部具有基本上相同的形状。
在该晶体管中，所述一个或多个成型鳍包括至少一个第一形状的成型鳍和至少一个第二形状的成型鳍。
在该晶体管中，所述一个或多个成型鳍小于所述一个或多个规则鳍。
在该晶体管中，所述一个或多个成型鳍大于所述一个或多个规则鳍。
在该晶体管中，所述一个或多个成型鳍中的每一个均只邻近于所述一个或多个规则鳍，使晶体管中邻近的鳍之间的间隔相同。
在该晶体管中，所述多个鳍和所述半导体衬底的材料相同。
根据本发明的又一方面，提供了一种形成鳍式场效晶体管(FinFET)的方法，所述方法包括：在半导体衬底上形成多个部分地嵌入在浅沟槽隔离(STI)层中的鳍；图案化所述多个鳍上方的光刻胶层，以形成一个或多个暴露出单个鳍的开口；以及将暴露出的所述单个鳍成型。
在该方法中，将暴露出的所述单个鳍成型包括：利用掺杂剂掺杂暴露出的所述单个鳍的一部分，以及去除暴露出的所述单个鳍的掺杂部分。
在该方法中，将暴露出的所述单个鳍成型包括：蚀刻暴露出的所述单个鳍的一部分。
在该方法中，所述去除步骤包括蚀刻。
根据本发明的又一方面，提供了一种形成鳍式场效晶体管(FinFET)的方法，所述方法包括：在半导体衬底上形成多个部分地嵌入在浅沟槽隔离(STI)层中的鳍；在所述STI层上方沉积介电层，以完全覆盖所述多个鳍；图案化所述介电层上方的光刻胶层，以在单个鳍上方形成一个或多个开口；蚀刻穿透所述介电层，以暴露出单个鳍；去除所述光刻胶层；以及将暴露出的所述单个鳍成型。
在该方法中，将暴露出的所述单个鳍成型包括：外延生长鳍材料。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以最好地理解本发明的特征。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1示出了鳍式场效晶体管(FinFET)。
图2示出了根据本发明的各个实施例的制造FinFET器件的方法的流程图。
图3A和图3B示出了根据本发明的各个实施例的部分制造完成的FinFET器件。
图4A、图5A和图6A示出了根据本发明的鳍短化的实施例。
图4B、图5B和图6B示出了根据本发明的鳍薄化的实施例。
图7、图8和图10示出了根据本发明的各个实施例的鳍形成工艺。
图9A和图9B示出了根据本发明的各个实施例的鳍成形工艺。
具体实施方式
以下详细讨论了说明性的实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。以下描述元件和布置的特定示例以简化本公开。当然这些仅仅是示例并不打算限定。例如，以下描述中第一部件形成在第二部件上可包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成在第一部件和第二部件之间的实施例，使得第一和第二部件不直接接触。当然描述会具体阐述部件是否互相直接接触。另外，本公开可能在各个例子中重复参考数字和/或字母。所讨论的具体实施例仅仅是说明性的且并不限定本发明的范围。
FinFET器件采用大致为矩形的鳍结构，通常用两种方法中的一种形成。在一种方法中，浅沟槽隔离(shallow trench isolation，STI)部件105首先形成在体硅材料上，如图1所示的衬底101。STI部件之间的沟槽底部暴露出体硅。然后，通过采用例如外延工艺，在沟槽里生长硅，以形成鳍103。一旦达到所需的鳍高度，蚀刻STI 105至低于鳍顶部的水平面，以暴露出部分鳍。鳍的暴露部分是顶部107，内嵌部分是底部109。体硅材料101可以是硅衬底或者沉积硅，如绝缘体上硅(silicon-on-insulator，SOI)，在SOI和下面的硅衬底之间有阻挡氧化物(barrier oxide，BOX)层。采用此种方法，STI部件限定了鳍的尺寸和形状。根据沟槽形成时所使用的蚀刻参数，鳍可能具有多种大致为矩形的形状，包括如图1所示的底部有微小的角度的鳍。
在另一种方法中，通过首先对体硅进行图案化并且在该体硅上沉积硬掩模层，从而把衬底上的体硅蚀刻成矩形鳍形状。硬掩模形成了覆盖在鳍顶部的图案。然后，蚀刻体硅，在覆盖着硬掩模层的区域之间形成沟槽。通过沉积绝缘材料(通常是氧化硅)，沟槽形成浅沟槽隔离(STI)部件105。绝缘材料通常过量沉积以完全覆盖鳍103和可选的硬掩模层(如果尚未去除)。将绝缘材料平坦化至鳍/硬掩模层的顶部表面以下，然后将该绝缘材料蚀刻至低于鳍顶部的水平面，以使部分鳍突出到STI之上。突出的鳍的部分是顶部107，内嵌的鳍部分是底部109。
在第二种方法的变形中，通过使用了金属心的工艺形成用于蚀刻体硅的硬掩模。形成和使用光刻胶图案蚀刻金属心图案。然后，围绕金属心沉积共形隔离件材料。共形隔离件通常由硬掩模形成，该硬掩模所形成的隔离件侧壁比金属心的隔离件侧壁更薄。然后，在随后的蚀刻操作中去除隔离件之间的金属心材料，只留下后面的隔离件。然后，一些隔离件用作硬掩模，以蚀刻下面的硅层，从而形成鳍结构。采用金属心/隔离件方法所形成的鳍，可以比采用第一种方法或采用未修正的第二种方法所形成的鳍相互更接近、更薄。暴露出的鳍部分107具有高度尺寸(h)、宽度尺寸(w)和长度尺寸(1)。根据这些尺寸可以限定FinFET器件的一些电气特性。例如，晶体管的有效沟道的宽度可以利用栅极下面的鳍尺寸计算出来。如图1所示，有效沟道宽度是2个鳍，或者2×(2h+w)。注意，有效沟道的宽度不包括鳍之间的距离。因为在本文中的鳍都具有相同的高度尺寸和宽度尺寸，所以这些鳍被称为规则鳍。
此处描述的剩余的形成FinFET器件的工艺步骤为本发明提供语境。栅极介电层113和栅极电极层111沉积在变窄的鳍上和STI层上方。栅极介电层113由高介电常数(高k)绝缘材料形成。示例性的高k材料的k值可以大于约4.0，甚至大于约7.0，可能包括含铝电介质，如Al2O3、HfAlO、HfAlON、或AlZrO；也可以包括含铪的电介质，如HfO2、HfSiOx、HfAlOx、HfZrSiOx、或HfSiON；和/或其他材料，如LaAlO3或ZrO2。栅极电极层111形成在栅极介电层113上，并由导电材料形成，如掺杂多晶硅、金属、或金属氮化物。
然后，将栅极电极层111和栅极介电层113图案化，以在鳍的中部上方形成栅极堆叠件。然后，将不位于栅极堆叠件以下的鳍部分可选地掺杂，以形成轻掺杂漏极(lightly doped drain，LDD)和源极区域。使用的掺杂剂取决于晶体管的导电类型。可以通过离子注入或等离子体掺杂对LDD区域掺杂，其中，将掺杂剂沉积在鳍上并退火。在栅极堆叠件上形成源极和漏极区域。可以通过以下步骤形成源极和漏极区域：离子注入源极/漏极区域，或去除部分鳍并在掺杂条件下将去除的部分外延再生长以形成源极/漏极区域。
电路设计者根据所要实现的各种功能的电气特性在其设计中指定晶体管。要考虑的电气特性包括开启电压(阈值电压)、击穿电压、导通电流(on-state current，Ion)、漏电流、等等。导通电流是栅极电压等于阈值电压时驱动穿过晶体管的电流。导通电流与沟道宽度成正比。当采用平面晶体管设计电路时，仅通过让晶体管更宽些或更窄些，沟道宽度就可以是任意值。然而，对于FinFET器件，沟道宽度不能是任意值——沟道宽度是单个鳍尺寸的整数倍。例如，FinFET器件的沟道宽度可以等于2个鳍或3个鳍，但不能是2.5个鳍。当基于平面晶体管的设计转换成基于FinFET器件的设计的时候，平面晶体管不能转换成具有完全相同的导通电流的FinFET器件。虽然根据电路的功能和应用，通常在一定范围内的导通电流都是可接收的，但是FinFET的沟道宽度的选择限制降低了设计的灵活性和平面晶体管到FinFET器件转换的精度。
本发明的各个实施例关于选择性鳍成形工艺，以允许单个鳍宽度和鳍高度控制。通过将FinFET器件中的一个或多个鳍成型，FinFET器件的沟道宽度可以变化为超过了单个鳍尺寸的整数倍。选择性鳍成形可以扩大一个或多个鳍，缩小一个或多个鳍，薄化一个或多个鳍，同时减小所有鳍尺寸，或在其他规则鳍保持不变的情况下，用其他方式改变一个或多个鳍的形状以创建成型的鳍。例如，通过减小一个鳍的尺寸可设计相当于有2.5个鳍的FinFET器件。优点可包括提高了电路设计的灵活性，增加了从事基于平面晶体管的设计到基于FinFET器件设计的转换的设计者和铸造厂的FinFET工艺裕度。
参考图2，示出了选择性鳍成型的工艺流程211。在操作213中，在半导体衬底上形成部分嵌入浅沟槽隔离(STI)层的鳍。如本文所论述，可采用多种方法形成鳍。鳍可以通过蚀刻体硅得到，或外延生长得到。
在操作215中，在STI层上方沉积可选介电层以完全覆盖鳍。如果要扩大一个或多个鳍，则要用到可选介电层。如果要减小一个或多个鳍，则可选介电层是不必要的。可选介电层可以是氧化硅、氮化硅、或其他较下面的STI层更容易蚀刻的介电层。在一些情况下，可在介电层之前沉积蚀刻停止层。在这种情况下，介电层的材料与STI层的材料可以相同。图3A示出了经过操作215后部分制造完成的FinFET器件。鳍301部分地嵌入STI层303。介电层305沉积在STI层303上方，并且完全覆盖鳍301。
再次参考图2，在操作217中，在鳍上方图案化光刻胶层。光刻尺寸限制了光刻胶层可以保护的最小尺寸以及光刻胶图案可以创建的最小尺寸开口。最小开口小于要保护的最小区域。换句话说，可以用一个鳍间距的尺寸创建开口，但相反，覆盖一个鳍间距的保护区域可能会太小。在图3A和图3B中，沉积并图案化光刻胶层307，以创建开口309。如果沉积了操作215中的介电层，则如图3A中所示，在介电层上方沉积光刻胶层。如果没有沉积操作215中的介电层，那么如图3B所示，直接在STI层和鳍上方沉积光刻胶层。
再次参考图2，在可选(虚线)操作227中，对暴露的单个鳍用掺杂剂掺杂。根据将要掺杂的部分，可以采用若干掺杂工艺。在一个实施例中，可采用离子注入工艺对鳍最顶部的小的垂直部分进行掺杂。掺杂离子对准开口，但由于开口的纵横比，基本上鳍的顶部都将被掺杂，如图4A中的鳍顶端401所示。掺杂剂可能是氧，以形成氧化硅鳍顶端。掺杂剂可能是氮，以形成氮化硅顶端。也可以采用可有效地改变鳍顶端401的化学特性以使其可以在后续的蚀刻程序中被简单地去除的其他掺杂剂。
在其他实施例中，如图4B所示，可采用共形等离子体掺杂工艺将鳍外层403转换为不同的材料。等离子体可以在现场或远程产生。例如，可用氧等离子体来氧化鳍的外层部分。也可以采用包括其他掺杂剂的等离子体，有效地改变鳍外层403的化学特性，以使外层403可以在后续的蚀刻程序中被简单地去除。
再次参考图2，在操作229中，蚀刻和去除暴露出的单个鳍的部分。去除部分可以是操作207中被掺杂的部分。根据掺杂工艺的类型和各种材料的蚀刻选择性，可以采用若干式蚀刻工艺。
在一些实施例中，将要去除的部分基本上位于鳍的顶端。采用这些实施例可以缩短FinFET器件中的一个或多个鳍，但丝毫不能改变鳍的宽度。可采用各个类型的等离子体蚀刻去除鳍顶端的掺杂部分。在图4A的一个示例中，将要去除的部分位于鳍的顶端，可以采用偏等离子体去除鳍顶端的材料。根据要去除的材料，等离子体可以包括活性离子，如氢和氟，例如氟碳等离子体。等离子体也可以可选地或额外地包括相对惰性类物质(relative inert species)，如氮、氩、氪或氙。例如，如果鳍顶端是氧化硅，则各向异性等离子体蚀刻可以包括氟基蚀刻剂。注意，相对于下面STI层里的氧化硅和鳍里的硅，等离子体蚀刻剂应该对于鳍顶端的氧化硅具有蚀刻偏好(etching preference)，以免以不期望的方式去除了许多STI层并且对鳍定型。可以通过以下方式将STI层的意外蚀刻最小化：以朝向衬底的较低功率进行偏置，将等离子体以一个角度朝向衬底使得大部分入射角都被阻挡，并且还通过选择蚀刻剂和STI材料来具有不同的蚀刻选择性。
在另一个示例中，如果掺杂剂是氮，则鳍顶端可以是氮化硅。比氧化硅具有氮化硅相对高蚀刻选择性的氮化硅等离子体蚀刻可以随着甲烷、氮和氧助剂气流而包括一些氟基等离子体。本领域技术人员可以调整气体混合物，以使相对于鳍顶端的氮化硅，很少或没有STI层被去除。蚀刻掉掺杂的鳍顶端后，由此产生的结构可能是图5A中的那样，其中，暴露的单个鳍短于邻近的受保护的鳍。
还可以采用湿式蚀刻方法去除掺杂的鳍顶端。在湿式蚀刻方法中，一个或多个衬底浸(bathed)在蚀刻剂容器里，还可以进行搅动，以促进蚀刻剂接触要被蚀刻的表面。湿式蚀刻剂通常会腐蚀(attack)所有暴露的表面，因此，相对于结构的其他部分，湿式蚀刻剂应具有用于蚀刻鳍顶端材料的高蚀刻选择性。例如，对于氧化硅鳍顶端，湿式蚀刻剂可以包括氢氟酸或氟碳蚀刻剂。对于氮化硅鳍顶端，湿式蚀刻剂可以包括磷酸。
在一些实施例中，如图4B所示，鳍外层是将要去除的部分。适当的各向同性蚀刻方法包括使用等离子体的干式蚀刻方法和湿式蚀刻方法。例如，可通过采用湿式蚀刻中的缓冲氧化蚀刻或氟化铵和氢氟酸的混合物去除氧化硅外层。等离子体蚀刻可涉及无偏等离子体，包括远程产生等离子体，去除外层。例如，可以采用带有氧的远程产生的SF6等离子体。蚀刻掉掺杂的外层部分后，由此产生的结构可能是图5B中的那样，其中，暴露的单个鳍薄于、并且有些短于邻近的受光刻胶保护的鳍。
仍有其他的实施例中，不采用首先掺杂鳍部分的方法蚀刻暴露的单个鳍的部分。各种蚀刻方法直接应用于硅鳍以改变其形状。可以将各种蚀刻方法分类为：干式蚀刻和湿式蚀刻、各向同性和各向异性、和产生不同形状的不同组合。
在一个示例中，可能采用使用各种氟基等离子体(如XeF2和BrF3)的等离子体蚀刻来各向同性地对暴露的鳍重新成型。效果类似于首先采用含等离子体的氧气氧化鳍、然后蚀刻氧化硅层。
在另一个示例中，采用聚合技术的等离子体蚀刻可以使得仅针对鳍的顶端部分进行适度的各向异性蚀刻。侧壁上的来自蚀刻沉积的聚合物副产品形成保护层。使用此技术，在后续的处理中必须去除聚合物残留物。可采用富含碳的氟碳或氢氟碳等离子体。
在另一个示例中，采用各向异性蚀刻剂的湿式蚀刻可以根据晶体定向将鳍成型。以定向面从属速率去除硅的各向异性湿式蚀刻包括采用四甲基氢氧化铵(tetramethylammonium hydroxide，TMAH)、氢氧化钾(potassiumhydroxide，KOH)或其他强碱性蚀刻剂(pH＞12)去蚀刻硅。因为每个晶面硅原子的结合能(bonding energy)不同，所以在蚀刻率限制(而非扩散限制)的反应中，这些蚀刻剂在特定的定向面间具有高灵敏度。TMAH湿式蚀刻形成凹口(notch)开口。KOH湿式蚀刻的定向依赖性类似于TMAH，但有不同的速率和比例。在一个示例中，蚀刻剂包括TMAH和KOH，其中TMAH约占重量的20％。
在又一个示例中，各向同性湿式蚀刻可以均匀地从所有方向去除未受保护的硅。各向同性硅蚀刻可以采用氢氟酸(hydrofluoric，HF)的组合，添加若干添加物，如硝酸((HNO3)、柠檬酸(CH3COOH)、亚氯酸钠(NaClO2)、高氯酸(HClO4)、新鲜的高锰酸钾(KMnO4)、或这些添加物的组合。这些化学混合物均匀地去除材料，并且受化学物类(chemicalspecies)在晶体表面的质量传输(扩散限制)的限制。
再次参考图2，在操作231中，去除了光刻胶层。采用本领域公知的灰化工艺完成光刻胶的去除。图6A和图6B示出了由此产生的鳍结构的示例。在图6A中，FinFET器件包括3个鳍，其中2个规则鳍和1个成型鳍。成型鳍具有较短的顶部。在图6B中，FinFET器件也包括3个鳍，其中2个规则鳍和1个成型鳍。成型鳍具有较窄的顶部，该较窄的顶部可以相同于、略短于、或略长于相邻的规则鳍。因为底部没有成型，所以三个鳍的底部都大致相同。注意，虽然成型鳍可能短于规则鳍，但是因为STI层也被蚀刻，并且成型鳍的顶部可以更多地暴露出来，所以成型鳍的顶部可以与规则鳍的顶部长度相同或者长于规则鳍。
本文讨论的各种蚀刻方法可以多种方式将暴露的鳍成型，以形成减小鳍高度和/或宽度的轮廓。轮廓变化使得FinFET器件能够具有非规则鳍整数倍的有效沟道宽度。根据期望的有效沟道宽度选择蚀刻方法来最小化处理和最大化工艺控制。
在减小鳍宽度的实施例中，额外的优点是增加了邻近鳍间的距离。增加鳍间的距离增大了用于形成栅极的工艺窗口。FinFET器件可以包括沉积在鳍中部上方的不同材料的许多层。每层都增加了鳍间的剩余空间的纵横比，使得最后的层可能由于没有空隙而难以充分沉积。增加鳍间距离减少了最初的纵横比，使得最后沉积工艺窗口较大。
仍然再次参考图2，操作219至操作223示出了通过增大鳍成型暴露出的单个鳍的可选实施例。在操作219中，蚀刻穿透由操作215得到的介电层以暴露单个鳍。当增大暴露的鳍时，介电层用来保护规则鳍。图7示出了将介电层705蚀刻到STI层703以下，形成包含一个单个鳍701的开口709之后的结构。然后，如图8所示，用图2中的操作221去除光刻胶层707。因为外延温度非常高，高于适合光刻胶材料的温度，所以在操作221中去除了光刻胶。注意，为了鳍801的外延生长，介电层805可以是氧化硅，且某些情况下可以是氮化硅。
在操作223中，在外延生长工艺期间，硅在暴露出的鳍上生长。没有硅在被介电层805覆盖的表面上生长。因为外延温度非常高，高于适合光刻胶材料的温度，所以在操作221中去除了光刻胶。图9A和图9B示出了由操作223得到的不同的结果。在图9A中，根据晶体定向，沿着暴露的鳍的表面单晶生长，形成了成型鳍901A。鳍901A的各种顶端角度取决于鳍的晶体定向。在一些实施例中，可控制鳍的顶端形状以形成不同的形状，如图9B中示出的那样。在外延生长期间，可包括能蚀刻特定表面的额外气体以将生长成型。可以通过调整具有各种盐酸气流的外延配方(epitaxialrecipe)形成如鳍901B的形状的球状顶端形状。
再次参考图2，在操作231中，去除光刻胶层。采用本领域公知的灰化工艺完成光刻胶的去除。图10中示出了由此产生的鳍的示例，展示了成型鳍901A。在图10中，FinFET器件包括3个鳍，其中2个规则鳍和1个成型鳍。成型鳍有对应硅晶定向的有角的表面(angular face)。与有3个规则鳍的FinFET器件相比，图10中的FinFET器件的有效沟道宽度增加。
本文中关于一个有三个鳍的FinFET器件论述了本公开的各个实施例。实际上，FinFET器件可能有任意数量的鳍，从一个至多个、甚至上百个。本公开并不限制FinFET器件具体的鳍个数。对于单鳍FinFET器件，唯一的鳍是成型鳍。对于两鳍FinFET器件，可以将一个或两个鳍成型。对于三鳍FinFET器件，可以将中间的鳍成型。如所述，尽管可在光刻胶中形成单个鳍开口，但是有光刻胶保护，仅一个鳍对于当前光刻工艺来说可能太小。因此，对于有超过3个鳍的FinFET器件，成型鳍可以通过2个规则鳍与规则鳍间隔开。四鳍FinFET器件可以包括位于两端的成型鳍和位于中间的两个规则鳍。可选地，可在同一开口中成型多个鳍。因此，四鳍FinFET器件也可包括位于中间的成型鳍和在两端的规则鳍。当然，可能三个鳍是成型的或三个鳍是规则的，或者可能所有鳍都是成型的或所有鳍都是规则的。
一种集成电路装置包括很多晶体管。该装置可能包括很多具有不同数量鳍的不同尺寸的FinFET。一些FinFET可能具有成型鳍，而一些FinFET可能不具有成型鳍。FinFET可以具有多种类型的成型鳍，例如，五鳍FinFET可以具有2个规则鳍、2个通过特定方式成型的鳍和1个通过不同方式成型的鳍。虽然成型鳍的工艺可能重复任意次，但是每次鳍成形工艺使用的生产资源都包括一个光掩模和一次至多次沉积和蚀刻工艺。
根据各个实施例，本发明涉及一种装置，该装置具有位于半导体衬底上的若干个FinFET，其中，一些FinFET具有至少一个成型鳍。该成型鳍可以小于或大于相同FinFET中的或其他FinFET中的规则鳍。在一些实施例中，至少一个成型鳍可以是两个或多个鳍，并且不相互邻接放置。在一些实施例中，多种成型鳍可以用在相同的FinFET中。
根据各种实施例，本发明还涉及一种FinFET器件，包括：半导体衬底、在衬底上的包括一个至多个规则鳍和具有不同顶部形状的一个至多个成型鳍的若干个鳍、在衬底上的嵌入了鳍底部的氧化层，其中，所嵌入的鳍底部具有大致相同的形状。然而定位效果可能在一定程度上影响晶体管边缘上的鳍的底部形状，但是这种变形并不明显，并且如果在制造的时候其唯一的不同是定位小欧冠，那么鳍将有大致相同的形状。
根据各种实施例，本公开也关于形成FinFET器件的方法，包括：在半导体衬底上形成若干个通过浅沟槽隔离(STI)层部分地内嵌的鳍、在多个鳍上图案化光刻胶层以形成一个或多个暴露单个鳍的开口、和成型暴露的单个鳍。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明的公开，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种装置，包括：
半导体衬底；以及
多个鳍式场效晶体管(FinFET)，位于所述衬底上，所述FinFET具有至少一个鳍；
其中，所述多个FinFET中的至少一个包括至少一个成型鳍。
2.根据权利要求1所述的装置，其中，所述至少一个成型鳍小于相同FinFET的其他鳍。
3.根据权利要求2所述的装置，其中，所述至少一个成型鳍是不邻近设置的两个或多个鳍。
4.根据权利要求1所述的装置，其中，所述至少一个成型鳍的一部分比相同FinFET的其他鳍更薄。
5.根据权利要求1所述的装置，其中，所述至少一个成型鳍大于相同FinFET的其他鳍。
6.根据权利要求1所述的装置，其中，所述多个FinFET中的至少一个的一部分是单鳍FinFET。
7.根据权利要求1所述的装置，其中，所述多个FinFET中的至少一个的一部分包括至少一个第一形状的成型鳍，所述多个FinFET的至少一个的另一部分包括至少一个第二形状的成型鳍，并且其中，所述第一形状和所述第二形状不同。
8.根据权利要求1所述的装置，其中，所述至少一个成型鳍具有倾斜侧壁。
9.一种鳍式场效晶体管(FinFET)，包括：
半导体衬底；
多个鳍，位于所述衬底上，包括一个或多个规则鳍和一个或多个成型鳍，其中，所述规则鳍和所述成型鳍的顶部形状不同；以及
氧化层，位于所述半导体衬底上，嵌入所述多个鳍的底部，
其中，所述多个鳍的嵌入底部具有基本上相同的形状。
10.一种形成鳍式场效晶体管(FinFET)的方法，所述方法包括：
在半导体衬底上形成多个部分地嵌入在浅沟槽隔离(STI)层中的鳍；
在所述STI层上方沉积介电层，以完全覆盖所述多个鳍；
图案化所述介电层上方的光刻胶层，以在单个鳍上方形成一个或多个开口；
蚀刻穿透所述介电层，以暴露出单个鳍；
去除所述光刻胶层；以及
将暴露出的所述单个鳍成型。
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