CN107706111B - 半导体器件的形成方法 - Google Patents

半导体器件的形成方法 Download PDF

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CN107706111B
CN107706111B CN201610646944.5A CN201610646944A CN107706111B CN 107706111 B CN107706111 B CN 107706111B CN 201610646944 A CN201610646944 A CN 201610646944A CN 107706111 B CN107706111 B CN 107706111B
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isolation film
fin
fin portion
forming
side wall
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CN107706111A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Priority to US15/665,651 priority patent/US10096518B2/en
Priority to EP17185248.6A priority patent/EP3282477A1/en
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Abstract

一种半导体器件的形成方法,包括:提供半导体衬底,所述半导体衬底上具有第一鳍部和第二鳍部,第一鳍部具有第一宽度,第二鳍部具有第二宽度,第二宽度大于第一宽度;在半导体衬底上形成覆盖第一鳍部侧壁和第二鳍部侧壁的第一隔离膜;在所述第一隔离膜中形成凹槽,所述凹槽暴露出第二鳍部的侧壁,所述凹槽侧壁与相邻所述第一鳍部侧壁之间的距离大于所述凹槽侧壁与相邻所述第二鳍部侧壁之间的距离;采用流体化学气相沉积工艺在所述凹槽中形成第二隔离膜,所述流体化学气相沉积工艺包括含氧退火,所述含氧退火适于氧化第二鳍部的侧壁,被氧化的所述第二鳍部的侧壁对应区域形成副产层。所述方法能够提高第二鳍部和第一鳍部的宽度一致性。

Description

半导体器件的形成方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体器件的形成方法。
背景技术
MOS(金属-氧化物-半导体)晶体管,是现代集成电路中最重要的元件之一,MOS晶体管的基本结构包括:半导体衬底;位于半导体衬底表面的栅极结构,所述栅极结构包括:位于半导体衬底表面的栅介质层以及位于栅介质层表面的栅电极层;位于栅极结构两侧半导体衬底中的源漏掺杂区。
随着半导体技术的发展,传统的平面式的MOS晶体管对沟道电流的控制能力变弱,造成严重的漏电流。鳍式场效应晶体管(FinFET)是一种新兴的多栅器件,它一般包括凸出于半导体衬底表面的鳍部,覆盖部分所述鳍部的顶部表面和侧壁的栅极结构,位于栅极结构两侧的鳍部中的源漏掺杂区。
然而,现有技术中鳍式场效应晶体管构成的半导体器件的鳍部宽度一致性较差。
发明内容
本发明解决的问题是提供一种半导体器件的形成方法,以提高第二鳍部和第一鳍部的宽度一致性。
为解决上述问题,本发明提供一种半导体器件的形成方法,包括:提供半导体衬底,所述半导体衬底上具有第一鳍部和第二鳍部,第一鳍部具有第一宽度,第二鳍部具有第二宽度,第二宽度大于第一宽度;在半导体衬底上形成覆盖第一鳍部侧壁和第二鳍部侧壁的第一隔离膜;在所述第一隔离膜中形成凹槽,所述凹槽暴露出第二鳍部的侧壁;所述凹槽侧壁与相邻所述第一鳍部侧壁之间的距离大于所述凹槽侧壁与相邻所述第二鳍部侧壁之间的距离;采用流体化学气相沉积工艺在所述凹槽中形成第二隔离膜,所述流体化学气相沉积工艺包括含氧退火,所述含氧退火适于氧化第二鳍部的侧壁,被氧化的所述第二鳍部的侧壁对应区域形成副产层。
可选的,所述含氧退火为水汽退火。
可选的,所述流体化学气相沉积工艺包括:在所述凹槽中形成隔离流体层;进行水汽退火,使所述隔离流体层形成第二隔离膜。
可选的,所述水汽退火的参数包括:采用的气体包括氧气、臭氧和气态水,退火温度为350摄氏度~750摄氏度。
可选的,所述流体化学气相沉积工艺还包括:进行水汽退火后,对所述第二隔离膜进行致密化退火处理。
可选的,所述致密化退火处理的参数包括:采用的气体包括氮气,退火温度为850摄氏度~1050摄氏度。
可选的,还包括:采用流体化学气相沉积工艺形成第二隔离膜之前,在所述凹槽暴露出的第二鳍部的侧壁表面形成控制层。
可选的,所述控制层沿垂直于第二鳍部侧壁方向上的尺寸为5埃~50埃。
可选的,所述控制层的材料为氧化硅、氮化硅或氮氧化硅。
可选的,所述第二隔离膜的材料为氧化硅。
可选的,所述凹槽暴露出第二鳍部一侧的侧壁;或者,所述凹槽暴露出第二鳍部两侧的侧壁。
可选的,所述第一鳍部和第二鳍部的顶部表面具有掩膜层;所述第一隔离膜还覆盖所述掩膜层的侧壁。
可选的,所述第一隔离膜覆盖第一鳍部和第二鳍部的侧壁且暴露出第一鳍部和第二鳍部的顶部表面。
可选的,所述第二隔离膜还位于第一鳍部和第二鳍部上、以及第一隔离膜表面;所述半导体器件的形成方法还包括:去除高于第一鳍部和第二鳍部顶部表面的第二隔离膜。
可选的,所述第一隔离膜覆盖第一鳍部和第二鳍部的侧壁和顶部表面。
可选的,所述第二隔离膜还位于第一隔离膜表面;所述半导体器件的形成方法还包括:去除高于第一鳍部和第二鳍部顶部表面的第一隔离膜和第二隔离膜。
可选的,还包括:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜、第二隔离膜和副产层的表面低于第一鳍部和第二鳍部的顶部表面;或者:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜和副产层的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜,从而形成隔离结构;或者:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜和副产层,从而形成隔离结构。
可选的,所述第一鳍部和第二鳍部的材料为硅、锗或锗化硅。
与现有技术相比,本发明的技术方案具有以下优点:
本发明提供的半导体器件的形成方法,利用形成第二隔离膜采用的流体化学气相沉积工艺中的含氧退火,使所述含氧退火作用于第二鳍部。一方面,在含氧退火的过程中,含氧退火能够氧化第二鳍部的侧壁,使得所述凹槽暴露出的第二鳍部的区域经过水汽处理后对应的宽度减小。因此使得所述凹槽暴露出的第二鳍部的区域经过水汽处理后对应的宽度和第一宽度之间的差值能够小于第二宽度与第一宽度之间的差值。因而提高了第二鳍部和第一鳍部的宽度一致性。另一方面,无需额外的含氧退火,简化了工艺。
附图说明
图1是一种半导体器件的结构图;
图2为沿着图1中切割线A-A1获得的剖面图;
图3至图10为本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述,现有技术中形成的半导体器件的鳍部宽度一致性较差。
图1是一种半导体器件的结构图,图2为沿着图1中切割线A-A1获得的剖面图,所述半导体器件为SRAM器件,所述半导体器件包括:半导体衬底100;两个第一鳍部110,位于半导体衬底100上;鳍部组,鳍部组位于半导体衬底100上,所述鳍部组包括两个相邻的第二鳍部111;两个第一鳍部110分别位于鳍部组的两侧,第一鳍部110和第二鳍部111相邻。
第一鳍部110和第二鳍部111通过直接刻蚀所述半导体衬底100而形成。
相邻第二鳍部111之间的距离为30nm~100nm。
为了方便说明,将相邻第一鳍部110和第二鳍部111之间的凹槽称为第一凹槽,将相邻第二鳍部111之间的凹槽称为第二凹槽。
然而,基于工艺设计的需要,相邻的第一鳍部110和第二鳍部111之间的距离小于相邻的第二鳍部111之间的距离。因此导致在图形化所述半导体衬底100的过程中,需要刻蚀去除较少的半导体衬底100的材料以形成第一凹槽,对应产生的副产物较少。因此导致在图形化所述半导体衬底100的过程中,需要刻蚀去除较多的半导体衬底100的材料以形成第二凹槽,对应产生的副产物较多。由于第一凹槽侧壁形成的副产物相对于第二凹槽侧壁形成的副产物较少,且副产物的聚集会降低刻蚀速率。因此导致对第一凹槽侧壁的刻蚀速率大于对第二凹槽侧壁的刻蚀速率。从而导致第一鳍部110的宽度小于第二鳍部111的宽度。降低了第一鳍部110和第二鳍部111的宽度一致性。
在此基础上,本发明提供一种半导体器件的形成方法,包括:提供半导体衬底,所述半导体衬底上具有第一鳍部和第二鳍部,第一鳍部具有第一宽度,第二鳍部具有第二宽度,第二宽度大于第一宽度;在半导体衬底上形成覆盖第一鳍部侧壁和第二鳍部侧壁的第一隔离膜;在所述第一隔离膜中形成凹槽,所述凹槽暴露出第二鳍部的侧壁;采用流体化学气相沉积工艺在所述凹槽中形成第二隔离膜,所述流体化学气相沉积工艺包括含氧退火,所述含氧退火适于氧化第二鳍部的侧壁,从而形成副产层。
利用形成第二隔离膜采用的流体化学气相沉积工艺中的含氧退火,使所述含氧退火作用于第二鳍部。一方面,在含氧退火的过程中,含氧退火能够氧化第二鳍部的侧壁,使得所述凹槽暴露出的第二鳍部的区域经过水汽处理后对应的宽度减小。因此使得所述凹槽暴露出的第二鳍部的区域经过水汽处理后对应的宽度和第一宽度之间的差值能够小于第二宽度与第一宽度之间的差值。因而提高了第二鳍部和第一鳍部的宽度一致性。另一方面,无需额外的含氧退火,简化了工艺。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图3至图10为本发明一实施例中半导体器件形成过程的结构示意图。
参考图3,提供半导体衬底200,所述半导体衬底200上具有第一鳍部221和第二鳍部222,第一鳍部221具有第一宽度W1,第二鳍部222具有第二宽度W21,第二宽度W21大于第一宽度W1。
所述半导体衬底200为后续形成半导体器件提供工艺平台。
所述半导体衬底200的材料可以是单晶硅、多晶硅或非晶硅;半导体衬底200的材料也可以是硅、锗、锗化硅、砷化镓等半导体材料;所述半导体衬底200还可以是其它半导体材料,这里不再一一举例。本实施例中,所述半导体衬底200的材料为单晶硅。
所述第一宽度W1指的是垂直于第一鳍部221延伸方向且平行于半导体衬底200表面的方向上的尺寸;所述第二宽度W21指的是垂直于第二鳍部222延伸方向且平行于半导体衬底200表面的方向上的尺寸。
本实施例中,第一鳍部221和第二鳍部222通过刻蚀半导体衬底200而形成。
具体的,在所述半导体衬底200上形成掩膜层230,所述掩膜层230定义出第一鳍部221和第二鳍部222的位置;以所述掩膜层230为掩膜,刻蚀部分半导体衬底200,从而形成第一鳍部221和第二鳍部222。
本实施例中,所述掩膜层230的材料为氮化硅或者氮氧化硅。在其它实施例中,所述掩膜层的材料为光刻胶。
本实施例中,形成第一鳍部221和第二鳍部222后,保留掩膜层230。在其它实施例中,在形成第一鳍部和第二鳍部后,去除掩膜层230。
需要说明的是,在其它实施例中,也可以是:在所述半导体衬底上形成鳍部材料层(未图示);图形化所述鳍部材料层,从而形成第一鳍部和第二鳍部。
所述第一鳍部221和第二鳍部222的材料为硅、锗或锗化硅。具体的,所述第一鳍部221和第二鳍部222的材料为单晶硅、单晶锗或者单晶锗化硅。
所述第一鳍部221的数量为一个或者多个。所述第二鳍部222的数量为一个或者多个。本实施例中,以第一鳍部221的数量为两个,第二鳍部222的数量为两个作为示例。
在一个实施例中,由两个第一鳍部221和两个第二鳍部222构成鳍部单元。在一个鳍部单元中,两个相邻的第二鳍部222构成鳍部组,两个第一鳍部221分别位于鳍部组的两侧。在相邻的鳍部单元中,一个鳍部单元中的第一鳍部221和另一个鳍部单元中的第一鳍部221相邻。
在其它实施例中,第一鳍部和第二鳍部的排布可以为其它情况。
基于工艺设计的需要,相邻的第一鳍部221和第二鳍部222之间的距离小于相邻的第二鳍部222之间的距离。为了方便说明,将相邻第一鳍部221和第二鳍部222之间的凹槽称为第一凹槽,将相邻第二鳍部222之间的凹槽称为第二凹槽。
相应的,在图形化所述半导体衬底200以形成第一鳍部221和第二鳍部222的过程中,需要刻蚀去除较少的半导体衬底200的材料以形成第一凹槽,对应产生的副产物较少。在图形化所述半导体衬底200的过程中,需要刻蚀去除较多的半导体衬底200的材料以形成第二凹槽,对应产生的副产物较多。由于第一凹槽侧壁形成的副产物相对于第二凹槽侧壁形成的副产物较少,且副产物的聚集会降低刻蚀速率,因此导致对第一凹槽侧壁的刻蚀速率大于对第二凹槽侧壁的刻蚀速率。从而使得第一鳍部221的第一宽度W1小于第二鳍部222的第二宽度W21。
相邻第二鳍部222之间的距离为30nm~100nm。
参考图4,在所述半导体衬底200上形成覆盖第一鳍部221侧壁和第二鳍部222侧壁的第一隔离膜240。
所述第一隔离膜240的材料为氧化硅、氮氧化硅或者碳氧化硅。
本实施例中,形成第一隔离膜240的方法包括:采用沉积工艺形成覆盖所述第一鳍部221、第二鳍部222、掩膜层230半导体衬底200的第一隔离初始膜(未图示),所述第一隔离初始膜的表面高于掩膜层230的顶部表面;去除高于掩膜层230顶部表面的第一隔离初始膜,从而形成第一隔离膜240。相应的,第一隔离膜240还覆盖掩膜层230的侧壁。
形成第一隔离初始膜的工艺为沉积工艺,如流体化学气相沉积工艺、亚大气压化学气相沉积工艺、高密度等离子体化学气相沉积工艺、低压化学气相沉积工艺。当采用流体化学气相沉积工艺形成第一隔离初始膜时,使得第一隔离初始膜的填充效果较好。
在其它实施例中,可以去除高于掩膜层顶部表面的部分第一隔离初始膜,使得第一隔离膜覆盖掩膜层、第一鳍部和第二鳍部。
在其它实施例中,当没有形成掩膜层时,所述第一隔离初始膜的表面高于第一鳍部和第二鳍部的顶部表面;需要去除高于第一鳍部和第二鳍部的顶部表面的第一隔离初始膜,从而形成第一隔离膜。
当没有形成掩膜层时,在一个实施例中,第一隔离膜覆盖第一鳍部和第二鳍部的侧壁且暴露出第一鳍部和第二鳍部的顶部表面;在另一个实施例中,第一隔离膜覆盖第一鳍部和第二鳍部的侧壁和顶部表面。
参考图5,在所述第一隔离膜240中形成凹槽250,所述凹槽250暴露出第二鳍部222的侧壁,所述凹槽侧壁与相邻所述第一鳍部侧壁之间的距离大于所述凹槽侧壁与相邻所述第二鳍部侧壁之间的距离。
形成凹槽250的工艺为干刻工艺或者湿刻工艺。
本实施例中,所述凹槽250暴露出第二鳍部222两侧的侧壁,具体的,所述凹槽250分别暴露出第二鳍部222两侧的部分侧壁。
在其它实施例中,所述凹槽分别暴露出第二鳍部两侧的全部侧壁。
在其它实施例中,所述凹槽暴露出第二鳍部一侧的侧壁。具体的,所述凹槽暴露出第二鳍部一侧的部分侧壁;或者,所述凹槽暴露出第二鳍部一侧的全部侧壁。
当所述凹槽分别暴露出第二鳍部两侧的部分侧壁,或者所述凹槽暴露出第二鳍部一侧的部分侧壁时,所述凹槽不会暴露出半导体衬底表面。相应的,在刻蚀第一隔离膜以形成凹槽的过程中,沿着半导体衬底表面法线方向上需要刻蚀的第一隔离膜较少,提高了工艺效率,且降低了成本。
所述凹槽250暴露出的第二鳍部222侧壁表面为宽度控制面。
参考图6,在所述凹槽250(参考图5)暴露出的第二鳍部222的侧壁表面形成控制层260。
所述控制层260的材料为氧化硅、氮化硅或氮氧化硅。
本实施例中,在所述凹槽250的底部和侧壁、掩膜层230和第一隔离膜240上形成控制层260。在其它实施例中,当第一隔离膜覆盖掩膜层时,在所述凹槽的底部和侧壁、以及第一隔离膜上形成控制层。
当没有形成掩膜层时,且第一隔离膜未覆盖第一鳍部和第二鳍部的顶部表面时,可以是:在所述凹槽的底部和侧壁、第一鳍部和第二鳍部上、以及第一隔离膜上形成控制层。当没有形成掩膜层,且第一隔离膜还覆盖第一鳍部和第二鳍部的顶部表面时,可以是:在所述凹槽的底部和侧壁、以及第一隔离膜上形成控制层。
在上述各种情况下,形成控制层的工艺为沉积工艺,如等离子体化学气相沉积工艺、低压化学气相沉积工艺、原子层沉积工艺或者亚大气压化学气相沉积工艺。
需要说明的是,在其它实施例中,可以仅在凹槽暴露出的第二鳍部的侧壁表面形成控制层。相应的,控制层的材料为氧化硅,形成所述控制层的工艺为热氧化工艺。
后续在所述凹槽250中形成隔离流体层。后续在对隔离流体层进行含氧退火的过程中,由于隔离流体层和第二鳍部222之间具有控制层260,避免隔离流体层直接接触第二鳍部222,因此使得控制层260能够减缓含氧退火对第二鳍部222氧化的速度。后续含氧退火后,所述宽度控制面对应的第二鳍部222的宽度为第三宽度。由于控制层260能够减缓含氧退火对第二鳍部222氧化的速度,因此利于对第三宽度的精准控制。
所述控制层260沿垂直于第二鳍部222侧壁方向上的尺寸需要选择合适的范围。若所述控制层260沿垂直于第二鳍部222侧壁方向上的尺寸过小,导致对第二鳍部222氧化的速度的控制作用下降;若所述控制层260沿垂直于第二鳍部222侧壁方向上的尺寸过大,将严重阻碍后续含氧退火对第二鳍部222的氧化,需要较长的时间使得宽度控制面对应的第二鳍部222到达第三宽度,使得含氧退火的工艺效率下降。故本实施例中,选择所述控制层260沿垂直于第二鳍部222侧壁方向上的尺寸为5埃~50埃。
在其它实施例中,可以不形成控制层。
接着,采用流体化学气相沉积工艺在所述凹槽250中形成第二隔离膜,所述流体化学气相沉积工艺包括含氧退火,所述含氧退火适于氧化第二鳍部222的侧壁。
下面具体介绍采用流体化学气相沉积工艺形成第二隔离膜的过程。
参考图7,图7为在图6基础上形成的示意图,在所述凹槽250中形成隔离流体层270。
本实施例中,在所述凹槽250中、第一鳍部221和第二鳍部222上、以及第一隔离膜240上形成隔离流体层270。
由于形成了掩膜层230,因此隔离流体层270还覆盖所述掩膜层230。
本实施例中,由于形成了控制层260,所述隔离流体层270还覆盖控制层260。
隔离流体层270中含有大量的氢元素,且所述隔离流体层270为流体状。
形成所述隔离流体层270的参数包括:采用的气体包括NH3和(SiH3)3N,NH3的流量为1sccm~1000sccm,(SiH3)3N的流量为3sccm~800sccm,温度为50摄氏度~100摄氏度。
形成隔离流体层270后,进行含氧退火。一方面,所述含氧退火能够减少隔离流体层270中的氢元素含量;另一方面,所述含氧退火能够氧化第二鳍部222的侧壁。
具体的,所述含氧退火为水汽退火。
参考图8,进行水汽退火,使所述隔离流体层270(参考图7)形成第二隔离膜271。
本实施例中,所述第二隔离膜271的材料为氧化硅。
所述水汽退火的参数包括:采用的气体包括氧气、臭氧和气态水,退火温度为350摄氏度~750摄氏度。
在所述水汽退火中,分别采用氧气、臭氧和气态水对所述隔离流体层270在350摄氏度~750摄氏度下进行处理。一方面,氧气、臭氧和气态水中的氧元素取代隔离流体层270中的部分氢元素或者全部氢元素,减少隔离流体层270中的氢元素含量;另一方面,在350摄氏度~750摄氏度下,使得隔离流体层270从流体状转变为固态状,从而形成第二隔离膜271。
另外,所述水汽退火能够氧化第二鳍部222的侧壁,被氧化的第二鳍部222对应的区域构成副产层(未标示)。
在所述水汽退火中,氧气、臭氧和气态水中的氧元素通过控制层扩散至第二鳍部222表面,扩散至第二鳍部222表面的氧元素氧化第二鳍部222的侧壁,使得宽度控制面对应的第二鳍部222的宽度减小。
所述流体化学气相沉积工艺还包括:进行水汽退火后,对所述第二隔离膜271进行致密化退火处理。
所述致密化退火处理的参数包括:采用的气体包括氮气,退火温度为850摄氏度~1050摄氏度。
所述致密化退火处理能够将第二隔离膜271的内部组织结构致密化。另外,若所述第二隔离膜271中还残留氢元素,所述致密化退火处理能够进一步去除第二隔离膜271中的氢元素。
水汽退火后,宽度控制面对应的第二鳍部222具有第三宽度W22,第三宽度W22小于第二宽度W21。
由于第三宽度W22小于第二宽度W21,因此能够使得第三宽度W22和第一鳍部221的第一宽度W1之间的差值小于第二宽度W21和第一鳍部221的第一宽度W1之间的差值。提高了第二鳍部222和第一鳍部221的宽度一致性。
参考图9,去除高于第一掩膜层230顶部表面的第二隔离膜271。
当没有形成第一掩膜层时,需要去除高于第一鳍部和第二鳍部顶部表面的第二隔离膜;当没有形成第一掩膜层,且第一隔离膜覆盖第一鳍部和第二鳍部的顶部表面时,需要去除高于第一鳍部和第二鳍部顶部表面的第二隔离膜和第一隔离膜;当第一隔离膜覆盖第一掩膜层时,需要去除高于第一掩膜层顶部表面的第二隔离膜和第一隔离膜。
参考图10,回刻蚀第一隔离膜240、第二隔离膜271和副产层,使第一隔离膜240、第二隔离膜271和副产层的表面低于第一鳍部221和第二鳍部222的顶部表面。
在其它实施例中,回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜和副产层的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜,从而形成隔离结构。或者是:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜和副产层,从而形成隔离结构。
当形成控制层时,在回刻蚀第一隔离膜、第二隔离膜和副产层的过程中,还回刻蚀控制层,使得控制层的表面也低于第一鳍部和第二鳍部的顶部表面。
本实施例中,在回刻蚀第一隔离膜240和第二隔离膜261的过程中,还去除了第一掩膜层230。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (18)

1.一种半导体器件的形成方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底上具有第一鳍部和第二鳍部,第一鳍部具有第一宽度,第二鳍部具有第二宽度,第二宽度大于第一宽度;
在半导体衬底上形成覆盖第一鳍部侧壁和第二鳍部侧壁的第一隔离膜;
在所述第一隔离膜中形成凹槽,所述凹槽暴露出第二鳍部的侧壁;
所述凹槽侧壁与相邻所述第一鳍部侧壁之间的距离大于所述凹槽侧壁与相邻所述第二鳍部侧壁之间的距离;
采用流体化学气相沉积工艺在所述凹槽中形成第二隔离膜,所述流体化学气相沉积工艺包括含氧退火,所述含氧退火适于氧化第二鳍部的侧壁,被氧化的所述第二鳍部的侧壁对应区域形成副产层。
2.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述含氧退火为水汽退火。
3.根据权利要求2所述的半导体器件的形成方法,其特征在于,所述流体化学气相沉积工艺包括:在所述凹槽中形成隔离流体层;进行水汽退火,使所述隔离流体层形成第二隔离膜。
4.根据权利要求3所述的半导体器件的形成方法,其特征在于,所述水汽退火的参数包括:采用的气体包括氧气、臭氧和气态水,退火温度为350摄氏度~750摄氏度。
5.根据权利要求3所述的半导体器件的形成方法,其特征在于,所述流体化学气相沉积工艺还包括:进行水汽退火后,对所述第二隔离膜进行致密化退火处理。
6.根据权利要求5所述的半导体器件的形成方法,其特征在于,所述致密化退火处理的参数包括:采用的气体包括氮气,退火温度为850摄氏度~1050摄氏度。
7.根据权利要求1所述的半导体器件的形成方法,其特征在于,还包括:采用流体化学气相沉积工艺形成第二隔离膜之前,在所述凹槽暴露出的第二鳍部的侧壁表面形成控制层。
8.根据权利要求7所述的半导体器件的形成方法,其特征在于,所述控制层沿垂直于第二鳍部侧壁方向上的尺寸为5埃~50埃。
9.根据权利要求7所述的半导体器件的形成方法,其特征在于,所述控制层的材料为氧化硅、氮化硅或氮氧化硅。
10.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第二隔离膜的材料为氧化硅。
11.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述凹槽暴露出第二鳍部一侧的侧壁;或者,所述凹槽暴露出第二鳍部两侧的侧壁。
12.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第一鳍部和第二鳍部的顶部表面具有掩膜层;所述第一隔离膜还覆盖所述掩膜层的侧壁。
13.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第一隔离膜覆盖第一鳍部和第二鳍部的侧壁且暴露出第一鳍部和第二鳍部的顶部表面。
14.根据权利要求13所述的半导体器件的形成方法,其特征在于,所述第二隔离膜还位于第一鳍部和第二鳍部上、以及第一隔离膜表面;所述半导体器件的形成方法还包括:去除高于第一鳍部和第二鳍部顶部表面的第二隔离膜。
15.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第一隔离膜覆盖第一鳍部和第二鳍部的侧壁和顶部表面。
16.根据权利要求15所述的半导体器件的形成方法,其特征在于,所述第二隔离膜还位于第一隔离膜表面;所述半导体器件的形成方法还包括:去除高于第一鳍部和第二鳍部顶部表面的第一隔离膜和第二隔离膜。
17.根据权利要求14或16所述的半导体器件的形成方法,其特征在于,还包括:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜、第二隔离膜和副产层的表面低于第一鳍部和第二鳍部的顶部表面;
或者:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜和副产层的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜,从而形成隔离结构;
或者:回刻蚀第一隔离膜、第二隔离膜和副产层,使第一隔离膜的表面低于第一鳍部和第二鳍部的顶部表面,且去除第二隔离膜和副产层,从而形成隔离结构。
18.根据权利要求1所述的半导体器件的形成方法,其特征在于,所述第一鳍部和第二鳍部的材料为硅、锗或锗化硅。
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