CN104137265B - 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 - Google Patents

具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 Download PDF

Info

Publication number
CN104137265B
CN104137265B CN201180076423.6A CN201180076423A CN104137265B CN 104137265 B CN104137265 B CN 104137265B CN 201180076423 A CN201180076423 A CN 201180076423A CN 104137265 B CN104137265 B CN 104137265B
Authority
CN
China
Prior art keywords
source
channel region
gate electrode
sidewall spacers
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180076423.6A
Other languages
English (en)
Other versions
CN104137265A (zh
Inventor
B·塞尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN201710116832.3A priority Critical patent/CN107039281B/zh
Priority to CN201710964294.3A priority patent/CN107742640A/zh
Priority to CN202110583500.2A priority patent/CN113540080A/zh
Priority to CN202110410997.8A priority patent/CN113345952A/zh
Publication of CN104137265A publication Critical patent/CN104137265A/zh
Application granted granted Critical
Publication of CN104137265B publication Critical patent/CN104137265B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13067—FinFET, source/drain region shapes fins on the silicon surface

Abstract

本发明描述了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。例如，半导体器件包括设置于衬底之上的半导体主体。栅极电极堆叠体设置于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。

Description

具有颈状半导体主体的半导体器件以及形成不同宽度的半导 体主体的方法
技术领域
本发明的实施例是在半导体器件和加工的领域中，具体而言，是在具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法的领域中。
背景技术
在过去几十年中，集成电路中的特征的缩放已经成为不断成长的半导体产业背后的驱动力。缩放到越来越小的特征使得能够增大在半导体芯片的有限的基板面上的功能单元的密度。例如，缩小晶体管尺寸允许芯片上包含的存储器设备或逻辑设备的数量增加，从而制造出具有更大的容量的产品。然而，对于越来越大容量的追求并不是没有问题。对每个器件的性能进行最优化的必要性变得越发显著。
在集成电路器件的制造中，诸如fin-FET和三栅极晶体管之类的多栅极晶体管已经随着器件尺寸不断缩小而变得更普遍。在常规工艺中，通常在体硅衬底或绝缘体上硅衬底上制造fin-FET和三栅极晶体管。在一些实例中，由于体硅衬底的成本较低并且因为它们能够实现较不复杂的fin-FET和三栅极制造工艺，所以体硅衬底是优选的。在其它实例中，由于fin-FET和三栅极晶体管的改进的短沟道特性，因而绝缘体上硅衬底是优选的。
然而，对多栅极晶体管进行缩放并不是还没有成果。随着微电子电路的这些基本构建块的尺寸减小，并且随着在给定区域中制造的基本构建块的绝对数目增加，在这些器件的运行期间，对外部电阻(Rext)的限制已经变得至关重要。已经尝试了许多不同的技术来改进晶体管的Rext，所述技术包括改进的接触金属、增大的掺杂剂活性以及降低的半导体与接触金属之间的势垒。然而，在减小Rext的领域中仍然需要显著改进。
发明内容
本发明的实施例包括具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。
在实施例中，半导体器件包括设置于衬底上方的半导体主体。栅极电极堆叠体设置于半导体主体的一部分上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成半导体主体。栅极电极堆叠体形成于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区、以及半导体主体中的位于栅极电极堆叠体的两侧上的源极区和漏极区。侧壁间隔体形成于临界栅极电极堆叠体处，并且形成于源极区和漏极区的仅一部分之上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖第二区并暴露第一区。随后，蚀刻第一区的鳍状物形成特征，以形成减薄的鳍状物形成特征，其中每个特征具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第三宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，从第一和第二区的鳍状物形成半导体器件。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第一宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖具有鳍状物的第二区并暴露具有鳍状物的第一区。随后，蚀刻第一区中的鳍状物，以形成减薄的鳍状物，其中每个减薄的鳍状物具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，从第一和第二区的鳍状物形成半导体器件。
附图说明
图1A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。
图1B示出根据本发明的实施例的图1A的半导体器件的沿着a-a’轴截取的截面视图。
图1C示出根据本发明的实施例的图1A的半导体器件的沿着b-b’轴截取的截面视图。
图2A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。
图2B示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。
图2C示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。
图3示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程。
图4示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程。
图5A包括根据本发明的实施例的驱动电流增益(如％Idsat增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线。
图5B包括根据本发明的实施例的驱动电流增益(如％Idlin增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线。
图6示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程。
图7示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程。
图8示出根据本发明的一种实施方式的计算设备。
具体实施方式
描述了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。在下文的描述中，为提供对本发明的实施例的深入理解而阐述了大量的具体细节，例如具体的集成和材料方案(regime)。对于本领域技术人员来说显而易见的是，可以在没有这些具体细节的情况下实践本发明的实施例。在其它实例中，为了不非必要地使本发明的实施例难以理解，没有具体描述诸如集成电路设计布局之类的公知的特征。此外，应该理解的是，附图中所示的各种实施例是说明性的表示，并且未必是按比例绘制的。
本发明的一个或多个实施例针对具有(1)与间隔体下方的鳍状物宽度相比的有源沟道区中的不同的鳍状物宽度，(2)在同一管芯上的不同有源沟道区中至少具有两个不同的鳍状物宽度的集成电路，(3)用于在实际鳍状物蚀刻之前限定两个不同的鳍状物宽度的构图工艺，(4)用于在牺牲虚设栅极去除工艺之后限定两个不同的鳍状物宽度的构图工艺，或它们的组合的半导体器件。一个或多个实施例针对改进诸如晶体管之类的器件的驱动电流，并且要建立具有低空载功率和高激活性能的电路。
FinFET中的鳍状物的宽度影响阈值电压(Vt)和器件的外部电阻。对于高性能器件而言，可能有益的是包含具有较高Vt和较低电阻的相对较宽的鳍状物。对于低功率器件而言，情况却正好相反。目前，必须针对这些器件的其中之一来优化所述工艺。可能有益的是使这两种器件都具有最佳性能，以优化产品功率性能。例如，利用引起较高的Vt和较高的结泄漏的附加的适当掺杂产生低功率器件，其尤其在低电源电压下降低了驱动电流。替代地，针对导致高性能器件的驱动电流降低的低功率器件来优化所述工艺。本发明的实施例可以通过在同一管芯上提供两个不同的器件或通过具有低Vt和低外部电阻二者的器件，使得能够同时实现高性能和低功率器件的优化。
在第一方面，提供了具有颈状半导体主体的半导体器件和形成具有颈状半导体主体的半导体器件的方法。这种晶体管结构在沟道中和间隔体下方的鳍状物区中具有不同的鳍状物宽度。随着鳍状物CD的缩放，颈状鳍状物可以改善短沟道效应改进与外部电阻之间的权衡，从而改善了最佳器件的驱动电流。
在示例中，图1A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。图1B示出根据本发明的实施例的图1A的半导体器件的沿着a-a’轴截取的截面视图。图1C示出根据本发明的实施例的图1A的半导体器件的沿着b-b’轴截取的截面视图。
参考图1A-1C，半导体器件100包括设置于衬底102上方的半导体主体104。栅极电极堆叠体106设置于半导体主体104的一部分上，以限定半导体主体104中的位于栅极电极堆叠体106下方的沟道区108。在栅极电极堆叠体106的两侧上的半导体主体104中限定了源极区和漏极区110。侧壁间隔体112设置于邻近栅极电极堆叠体106处，并且设置于源极区和漏极区110的仅一部分上。
参考图1B和1C，相较于半导体主体104的沟道区108的高度(H1)和宽度(W1)，源极区和漏极区110的位于侧壁间隔体112下方的部分具有更大的高度(H2)和宽度(W2)。高度H1和H2被限定为隔离层114上方的半导体主体104的相应的部分的高度，如图1B和1C中所描绘的那样。
参考图1A，在实施例中，相较于源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)和宽度(W2)，源极区和漏极区110的不在侧壁间隔体112下方的部分具有更大的高度和宽度(W3)，例如，W3>W2。替代地，在另一个实施例中，源极区和漏极区110的不在侧壁间隔体112下方的部分的高度和宽度(W3)与源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)和宽度(W2)大致相同，例如，W3＝W2。
在实施例中，源极区和漏极区110的至少一部分是源极区和漏极区110的嵌入的部分。也就是，在形成源极区和漏极区110时，去除最初的半导体主体104的一部分，并且例如通过外延生长来将其替换为半导体主体104的新的部分。例如，在一个这种实施例中，源极区和漏极区110的嵌入的部分由与沟道区108的半导体材料不同的半导体材料构成。在一个实施例中，嵌入的部分并不包括源极区和漏极区110的位于侧壁间隔体112下方的部分。在另一个实施例中，嵌入的部分包括源极区和漏极区110的位于侧壁间隔体112下方的部分中的至少一部分并且可能是全部。
在实施例中，参考图1B和1C，衬底102是晶体衬底，并且半导体主体104(例如，图1B中的沟道区108和图1C中的源极区和漏极区110)与晶体衬底102连续。也就是，从体衬底形成半导体主体104。在替代的实施例(未示出)中，电介质层设置于半导体主体与衬底之间，并且半导体主体与衬底不连续，例如，如绝缘体上硅(SOI)衬底会出现的情况一样。
在实施例中，沟道区108的高度(H1)近似在30-50纳米的范围中，并且宽度(W1)近似在10-30纳米的范围中。在该实施例中，沟道区108的高度(H1)比源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)小大约1-2纳米。同样，沟道区108的宽度(W1)比源极区和漏极区110的位于侧壁间隔体112下方的部分的宽度(W2)小大约2-4纳米。在实施例中，源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)比沟道区108的高度(H1)大大约1-7％。在该实施例中，源极区和漏极区110的位于侧壁间隔体112下方的部分的宽度(W2)比沟道区108的宽度(W1)大大约6-40％。
以下描述了图1A-1C中的半导体器件100的可能的实施例。在第一个示例中，图2A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。参考图2A，沟道区108通过台阶特征120耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
在第二个示例中，图2B示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。参考图2B，沟道区108通过刻面(facet)特征130耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
在第三个示例中，图2C示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。参考图2C，沟道区108通过圆化拐角特征140耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
因此，再次参考图2B和2C，在实施例中，沟道区108通过缓变(graded)特征(例如，120或140)耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。在实施例中，缓变特征在半导体器件110的运行期间减小了重叠电容和扩散电阻。
在实施例中，如以下结合工艺流程600和700所更详细地描述的，半导体器件100设置于与具有沟道区的第二半导体器件相同的衬底102上方。在该实施例中，第二半导体器件的沟道区的最窄宽度大于半导体器件100的沟道区108的最窄宽度(例如，W1)。
半导体器件100可以是包含栅极、沟道区和源极/漏极区对的任何半导体器件。在实施例中，半导体器件100是例如但不限于MOS-FET或微机电系统(MEMS)的半导体器件。在一个实施例中，半导体器件100是三维的MOS-FET，并且是隔离的器件或者是多个嵌套的器件中的一个器件。会理解，对于典型的集成电路来说，可以在单个衬底上制造N沟道和P沟道晶体管二者，以形成CMOS集成电路。
衬底102可以由能够承受制造工艺并且电荷能够在其中迁移的半导体材料构成，并且因此半导体主体104也可以由这种半导体材料构成。在实施例中，衬底102是体衬底，并且半导体主体104与体衬底102连续。在实施例中，衬底102由晶体硅、硅/锗或掺杂有电荷载流子的锗层构成，所述电荷载流子例如但不限于磷、砷、硼或它们的组合。在一个实施例中，衬底102中的硅原子的浓度大于97％，或者，替代地，掺杂剂原子的浓度小于1％。在另一个实施例中，衬底102由生长在不同的晶体衬底顶上的外延层构成，例如，生长在硼掺杂的体硅单晶衬底顶上的硅外延层。衬底102还可以包括设置于体晶体衬底与外延层之间的绝缘层，以形成例如绝缘体上硅衬底。在所述示例中，半导体主体104可以是隔离的半导体主体。在实施例中，绝缘层由例如但不限于二氧化硅、氮化硅、氮氧化硅或高k电介质层的材料构成。替代地，衬底102可以由Ⅲ-Ⅴ族材料构成。在实施例中，衬底102由例如但不限于氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓、磷化铟镓、或它们的组合的Ⅲ-Ⅴ族材料构成。半导体主体104可以由多种半导体材料构成，所述多种半导体材料中的每种半导体材料可以包括附加的掺杂原子。在一个实施例中，衬底102由晶体硅构成，并且电荷载流子掺杂剂杂质原子是例如但不限于硼、砷、铟或磷的原子。在另一个实施例中，衬底102由Ⅲ-Ⅴ族材料构成，并且电荷载流子掺杂剂杂质原子是例如但不限于碳、硅、锗、氧、硫、硒或碲的原子。在另一个实施例中，半导体主体104是未掺杂的或仅轻度掺杂的。另外，在一个实施例中，可以在半导体器件100的制造中消除常规器件制造中通常使用的晕轮(halo)掺杂。应该理解的是，在实施例中，半导体主体104的材料与衬底102的材料不同。
在另一个实施例中，半导体器件100是例如但不限于fin-FET或三栅极器件的非平面器件。在这种实施例中，半导体主体104由三维主体构成，或者从三维主体形成。在一个这种实施例中，栅极电极堆叠体106至少包围三维主体的顶表面和一对侧壁。在另一个实施例中，例如在纳米线器件中，将半导体主体104制造为分立的三维主体。在一个这种实施例中，栅极电极堆叠体100完全包围半导体主体104的一部分。
栅极电极堆叠体106可以包括栅极电极和下层的栅极电介质层。在实施例中，栅极电极堆叠体106的栅极电极由金属栅极构成，并且栅极电介质层由高K材料构成。例如，在一个实施例中，栅极电介质层由例如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、铅钽钪氧化物、铌酸铅锌、或它们的组合之类的材料构成。此外，栅极电介质层的一部分可以包括由半导体主体104的顶部几层形成的自然氧化物层。在实施例中，栅极电介质层由顶部高K部分和由半导体材料的氧化物构成的下层部分构成。在一个实施例中，栅极电介质层由氧化铪的顶部部分和二氧化硅或氮氧化硅的底部部分构成。
在一个实施例中，栅极电极由例如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍、或导电金属氧化物之类的金属层构成。在具体实施例中，栅极电极由形成于金属功函数设定层上方的非功函数设定填充材料构成。在实施例中，栅极电极由P型材料构成。在另一个实施例中，栅极电极由N型材料构成。在另一个实施例中，栅极电极由中间带隙材料构成。在特定的这种实施例中，相应的沟道区是未掺杂的或仅轻度掺杂的。
在实施例中，侧壁间隔体112由例如但不限于二氧化硅、碳化硅、氮氧化硅或氮化硅的绝缘电介质材料构成。类似地，电介质层114可以由例如但不限于二氧化硅、碳化硅、氮氧化硅或氮化硅的绝缘电介质材料构成。
在本发明的实施例的精神和范围内还考虑了形成诸如以上所描述的那些器件之类的器件的方法。在第一个示例中，图3示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程300。
参考工艺流程300的部分A，形成厚鳍状物302，对牺牲栅极304进行构图，通过均厚沉积和随后的蚀刻来形成栅极间隔体306，并且形成源极-漏极区308。另外，可以沉积层间电介质膜310并对其进行抛光，以暴露牺牲栅极304。参考工艺流程300的部分B，去除牺牲栅极304，并且蚀刻厚鳍状物302，以形成具有减小的厚度(例如，减小大约1-5纳米范围内的量)的减薄的鳍状物312。参考工艺流程300的部分C，在减薄的鳍状物312之上形成永久的栅极堆叠体320。例如，可以形成高k栅极电介质层和金属栅极电极。在实施例中，减薄的鳍状物312提供改进的短沟道效应，而源极区和漏极区308的位于间隔体306下方的较宽的部分有助于减小外部电阻。
在实施例中，牺牲栅极304由适合于在替换栅极操作时去除的材料构成。在一个实施例中，牺牲栅极304由多晶硅、非晶硅、二氧化硅、氮化硅、或它们的组合构成。在另一个实施例中，在牺牲栅极304上方形成诸如二氧化硅或氮化硅层之类的保护性覆盖层(未示出)。在实施例中，包括了下层的虚设栅极电介质层(也未示出)。在实施例中，牺牲栅极304包括侧壁间隔体306，侧壁间隔体306可由适合于最终将永久栅极结构与邻近的导电接触部电隔离的材料构成。例如，在一个实施例中，间隔体306由例如但不限于二氧化硅、氮氧化硅、氮化硅、或碳掺杂的氮化硅的电介质材料构成。
在实施例中，通过干法蚀刻或湿法蚀刻工艺来去除牺牲栅极304。在一个实施例中，牺牲栅极304由多晶硅或非晶硅构成，并且利用使用SF6的干法蚀刻工艺来去除牺牲栅极304。在另一个实施例中，牺牲栅极304由多晶硅或非晶硅构成，并且利用使用NH4OH或四甲胺羟化物的水溶液的湿法蚀刻工艺来去除牺牲栅极304。在一个实施例中，牺牲栅极304由氮化硅构成，并且利用使用磷酸水溶液的湿法蚀刻来去除牺牲栅极304。
在对存在的其它半导体特征没有不利影响的情况下，可以通过将鳍状物302的一部分去除的任何适合的技术(例如通过利用干法蚀刻或湿法蚀刻工艺)来将鳍状物302减薄，以形成312。在一个实施例中，可以通过利用使用NF3、HBr、SF6/Cl或Cl2的干法等离子体蚀刻来将鳍状物302减薄，以形成312。
在第二个示例中，图4示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程400。参考工艺流程400的部分A，形成薄鳍状物412，对牺牲栅极404进行构图，并且形成薄源极-漏极区408。参考工艺流程400的部分B，通过均厚沉积和随后的蚀刻来形成栅极间隔体406，并且例如通过外延生长来形成厚源极区和漏极区418。此外，可以沉积层间电介质膜410并对其进行抛光，以暴露牺牲栅极404。然后去除牺牲栅极404，如部分B中所描绘的那样。参考工艺流程400的部分C，在薄鳍状物412上形成永久的栅极堆叠体420。例如，可以形成高k栅极电介质层和金属栅极电极。在实施例中，薄鳍状物412提供改进的短沟道效应，而源极区和漏极区408/418的位于间隔体406下方的较宽的部分有助于减小外部电阻。可以如以上结合工艺流程300所描述的那样来执行牺牲栅极的形成和替换。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成半导体主体。栅极电极堆叠体形成于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区、以及半导体主体中的位于栅极电极堆叠体的两侧上的源极区和漏极区。侧壁间隔体形成于邻近栅极电极堆叠体处并且形成于源极区和漏极区的仅一部分之上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在一个这种实施例中，形成栅极电极堆叠体包括：形成牺牲栅极电极堆叠体、去除牺牲栅极电极堆叠体、以及形成永久的栅极电极堆叠体。在该实施例中，形成沟道区包括：在去除牺牲栅极电极堆叠体之后并且在形成永久的栅极电极堆叠体之前，将暴露的半导体主体的一部分减薄，例如，如结合工艺流程300所描述的那样。在另一个这种实施例中，形成栅极电极堆叠体包括：形成牺牲栅极电极堆叠体、去除牺牲栅极电极堆叠体、以及形成永久的栅极电极堆叠体。在该实施例中，形成源极区和漏极区包括：在去除牺牲栅极电极堆叠体之前扩展暴露的半导体主体的一部分，例如，如结合工艺流程400所描述的那样。
图5A包括根据本发明的实施例的驱动电流增益(如％Idsat增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线500A。图5B包括根据本发明的实施例的驱动电流增益(如％Idlin增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线500B。参考曲线500A和500B，将根据预先的硅宽度(Wsi)限定形成的鳍状物与具有在替换栅极操作期间限定的减薄的硅宽度(Wsi)的鳍状物(例如，如结合工艺流程300所描述的那样)进行比较。曲线揭示了减薄的鳍状物器件的预期驱动电流增益。
在第二方面，提供了形成不同宽度的半导体主体的方法。这种工艺可以使得能够在同一管芯内形成不同的鳍状物宽度。因此，可以在同一管芯上实现使用用于高性能应用的较宽的鳍状物宽度器件和用于低功率(低待机泄漏)应用的较低的鳍状物宽度器件。
在第一个示例中，图6示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程600。
参考工艺流程600的部分A，衬底602上方(例如，晶体硅衬底上方)的用于最终鳍状物形成的硬掩模603A/603B的形成包括硬掩模层的沉积和构图。已构图的硬掩模层603A/603B包括用于最终薄鳍状物形成的区域604和用于最终厚鳍状物形成的区域606。参考工艺流程600的部分B，利用抗蚀剂层608来遮住将维持较宽的宽度的鳍状物(例如，在区域606中)，并且蚀刻暴露的硬掩模603A来减小线的宽度。参考工艺流程600的部分C，然后去除抗蚀剂层608(例如包括灰化工艺)，并且将新的硬掩模图案603A/603B转移到衬底602中，以形成鳍状物610A和610B。替代地，在实施例中，可以在鳍状物被蚀刻到衬底中之后、并且在牺牲栅极的构图之前执行附加的光刻鳍状物减薄。在实施例中，由间隔体构图流程首先形成硬掩模区603A/603B，所述间隔体构图流程可以用于有效地使被用于形成特征的光刻工艺的间距加倍。工艺流程600维持了间隔体构图流程的间距。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖第二区并暴露第一区。随后，蚀刻第一区的鳍状物形成特征，以形成减薄的鳍状物形成特征，其中每个特征具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第三宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，利用第一和第二区的鳍状物形成半导体器件。在一个这种实施例中，衬底是单晶硅衬底，并且将硬掩模图案转移到衬底包括形成单晶硅鳍状物。
在第二个示例中，图7示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程700。
参考工艺流程700的部分A，衬底702上方(例如，晶体硅衬底上方)的用于鳍状物形成的硬掩模703A/703B的形成包括硬掩模层的沉积和构图。已构图的硬掩模层703A/703B包括用于薄鳍状物形成的区域704和用于厚鳍状物形成的区域706。然后将硬掩模图案703A/703B转移到衬底702中，以形成对应的鳍状物。然后可以执行牺牲栅极构图以及延伸源极和漏极的形成。同样，可以沉积层间电介质材料并对其进行抛光，以露出牺牲栅极。然后去除牺牲栅极。参考工艺流程700的部分B，利用抗蚀剂层708来遮住将保持较宽的宽度的鳍状物710B(例如，在区域706中)。鳍状物减薄蚀刻用于减小鳍状物710A的鳍状物宽度。参考工艺流程700的部分C，去除抗蚀剂层708(例如包括灰化工艺)，并且可以利用较薄的鳍状物710A和较宽的鳍状物710B来执行标准器件制造技术。在实施例中，由间隔体构图流程首先形成硬掩模区703A/703B，所述间隔体构图流程可以用于有效地使被用于形成特征的光刻工艺的间距加倍。工艺流程700维持了间隔体构图流程的间距。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第一宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，形成抗蚀剂层并对其进行蚀刻，以覆盖具有鳍状物的第二区并暴露具有鳍状物的第一区。随后，蚀刻第一区的鳍状物，以形成减薄的鳍状物，其中每个减薄的鳍状物具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，利用第一和第二区的鳍状物形成半导体器件。在一个这种实施例中，衬底是单晶硅衬底，并且将硬掩模图案转移到衬底包括形成单晶硅鳍状物。
本文中所描述的工艺可以用于制造一个或多个半导体器件。半导体器件可以是晶体管或类似器件。例如，在实施例中，半导体器件是用于逻辑或存储器的金属氧化物半导体(MOS)晶体管，或是双极晶体管。同样，在实施例中，半导体器件具有三维的架构，例如三栅极器件、独立访问的双栅极器件、或FIN-FET。
图8示出根据本发明的一种实施方式的计算设备800。计算设备800容纳板802。板802可以包括多个部件，包括但不限于处理器804和至少一个通信芯片806。处理器804与板802物理地和电气地耦合。在一些实施方式中，至少一个通信芯片806也与板802物理地和电气地耦合。在其它实施方式中，通信芯片806是处理器804的一部分。
取决于其应用，计算设备800可以包括其它部件，所述其它部件可以或可以不与板802物理地和电气地耦合。这些其它部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘，等等)。
通信芯片806使得能够进行用于到和来自计算设备800的数据的传送的无线通信。术语“无线”和其衍生词可以用于描述可以通过使用调制的电磁辐射、经由非固态介质传送数据的电路、设备、系统、方法、技术、通信信道，等等。所述术语并不暗示相关联的设备不包含任何线路，尽管在一些实施例中它们可能不包含。通信芯片806可以实施多种无线标准或协议中的任何一种，所述多种无线标准或协议包括但不限于Wi-Fi(IEEE802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及它们的衍生物，以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备800可以包括多个通信芯片806。例如，第一通信芯片806可以专用于诸如Wi-Fi和蓝牙的较短距离的无线通信，并且第二通信芯片806可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它的较远距离的无线通信。
计算设备800的处理器804包括封装在处理器804内的集成电路管芯。在本发明的一些实施方式中，处理器的集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。术语“处理器”可以指代处理来自寄存器和/存储器的电子数据以将该电子数据转换成可以在寄存器和/或存储器中存储的其它电子数据的任何器件或器件的部分。
通信芯片806还包括封装在通信芯片806内的集成电路管芯。根据本发明的另一种实施方式，通信芯片的集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。
在进一步的实施方式中，计算设备800内容纳的另一个部件可以包含集成电路管芯，该集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。
在各种实施方式中，计算设备800可以是膝上型电脑、上网本、笔记本电脑、超极本、智能手机、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或数字录像机。在进一步的实施方式中，计算设备800可以是处理数据的任何其它电子设备。
因此，已经公开了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。在实施例中，半导体器件包括设置于衬底上方的半导体主体。栅极电极堆叠体设置于半导体主体的一部分上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。在一个实施例中，半导体器件设置于与具有沟道区的第二半导体器件相同的衬底上方，并且第二半导体器件的沟道区的最窄的宽度大于半导体器件的沟道区的最窄的宽度。

Claims (36)

1.一种半导体器件，包括：
半导体主体，其设置于衬底上方；
栅极电极堆叠体，其设置于所述半导体主体的一部分之上，以限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区、以及所述半导体主体中的位于所述栅极电极堆叠体的两侧上的源极区和漏极区，其中所述沟道区包括位于所述栅极电极堆叠体下方的缓变特征；以及
侧壁间隔体，其设置于邻近所述栅极电极堆叠体处，并且设置于所述源极区和漏极区的仅一部分之上，其中相较于所述半导体主体的所述沟道区的高度和宽度，所述源极区和漏极区的位于所述侧壁间隔体下方的部分具有更大的高度和宽度。
2.根据权利要求1所述的半导体器件，其中相较于所述源极区和漏极区的位于所述侧壁间隔体下方的部分的高度和宽度，所述源极区和漏极区的不在所述侧壁间隔体下方的部分具有更大的高度和宽度。
3.根据权利要求1所述的半导体器件，其中所述源极区和漏极区的不在所述侧壁间隔体下方的部分的高度和宽度与所述源极区和漏极区的位于所述侧壁间隔体下方的部分的高度和宽度几乎相同。
4.根据权利要求1所述的半导体器件，其中所述源极区和漏极区的至少一部分是所述源极区和漏极区的嵌入部分。
5.根据权利要求4所述的半导体器件，其中所述源极区和漏极区的所述嵌入部分包括与所述沟道区不同的半导体材料。
6.根据权利要求1所述的半导体器件，其中所述衬底是晶体衬底，并且所述半导体主体与所述晶体衬底连续。
7.根据权利要求1所述的半导体器件，其中电介质层设置于所述半导体主体与所述衬底之间，并且所述半导体主体与所述衬底不连续。
8.根据权利要求1所述的半导体器件，其中所述沟道区的高度在30-50纳米的范围内，并且所述沟道区的宽度在10-30纳米的范围内，相较于所述源极区和漏极区的位于所述侧壁间隔体下方的部分的高度，所述沟道区的高度小了1-2纳米，并且相较于所述源极区和漏极区的位于所述侧壁间隔体下方的部分的宽度，所述沟道区的宽度小了2-4纳米。
9.根据权利要求1所述的半导体器件，其中相较于所述沟道区的高度，所述源极区和漏极区的位于所述侧壁间隔体下方的部分的所述高度大了1-7％，并且相较于所述沟道区的宽度，所述源极区和漏极区的位于所述侧壁间隔体下方的部分的宽度大了6-40％。
10.根据权利要求1所述的半导体器件，其中所述缓变特征包括刻面。
11.根据权利要求1所述的半导体器件，其中所述缓变特征包括圆化拐角。
12.根据权利要求1所述的半导体器件，其中所述缓变特征减小了在所述半导体器件的运行期间的重叠电容和扩散电阻。
13.根据权利要求1所述的半导体器件，其中所述半导体器件与具有沟道区的第二半导体器件设置于相同的衬底上方，并且其中所述第二半导体器件的所述沟道区的最窄宽度大于所述半导体器件的所述沟道区的最窄宽度。
14.一种制造半导体器件的方法，所述方法包括：
在衬底上方形成半导体主体；
在所述半导体主体的一部分之上形成栅极电极堆叠体，以限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区、以及所述半导体主体中的位于所述栅极电极堆叠体的两侧上的源极区和漏极区，其中所述沟道区包括位于所述栅极电极堆叠体下方的缓变特征；以及
在邻近所述栅极电极堆叠体处、并且在所述源极区和漏极区的仅一部分之上形成侧壁间隔体，其中相较于所述半导体主体的所述沟道区的高度和宽度，所述源极区和漏极区的位于所述侧壁间隔体下方的部分具有更大的高度和宽度。
15.根据权利要求14所述的方法，其中形成所述栅极电极堆叠体包括：形成牺牲栅极电极堆叠体，去除所述牺牲栅极电极堆叠体，以及形成永久的栅极电极堆叠体，并且其中形成所述沟道区包括：在去除所述牺牲栅极电极堆叠体之后、并且在形成所述永久的栅极电极堆叠体之前将暴露的所述半导体主体的一部分减薄。
16.根据权利要求14所述的方法，其中形成所述栅极电极堆叠体包括：形成牺牲栅极电极堆叠体，去除所述牺牲栅极电极堆叠体，以及形成永久的栅极电极堆叠体，并且其中形成所述源极区和漏极区包括：在去除所述牺牲栅极电极堆叠体之前扩展暴露的所述半导体主体的部分。
17.一种半导体结构，包括：
硅主体，其从下方的体硅衬底突出出来并且与所述下方的体硅衬底是连续的；
栅极电极，其位于所述硅主体的一部分之上，限定了所述硅主体中的位于所述栅极电极下方的沟道区，所述栅极电极具有第一侧和与所述第一侧相对的第二侧，其中从平面视图视角来看所述沟道区包括第一锥形部分和第二锥形部分，所述第一锥形部分从所述沟道区的中央到所述沟道区的第一端变宽，并且所述第二锥形部分从所述沟道区的中央到所述沟道区的第二端变宽；
第一源极/漏极区，其耦合到所述沟道区的所述第一端并且邻近所述栅极电极的所述第一侧；
第二源极/漏极区，其耦合到所述沟道区的所述第二端并且邻近所述栅极电极的所述第二侧；
第一电介质侧壁间隔体，其邻近所述栅极电极的所述第一侧并且仅位于所述第一源极/漏极区的一部分之上；以及
第二电介质侧壁间隔体，其邻近所述栅极电极的所述第二侧并且仅位于所述第二源极/漏极区的一部分之上。
18.根据权利要求17所述的半导体结构，其中从平面视图视角来看所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分的最宽宽度大于所述硅主体的沟道区的最宽宽度，并且其中从平面视图视角来看所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的最宽宽度大于所述硅主体的沟道区的最宽宽度。
19.根据权利要求18所述的半导体结构，其中从平面视图视角来看所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之外的部分的最宽宽度大于所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分的最宽宽度，并且从平面视图视角来看所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之外的部分的最宽宽度大于所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的最宽宽度。
20.根据权利要求18所述的半导体结构，其中从平面视图视角来看所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之外的部分的最宽宽度与所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分的最宽宽度大致相同，并且从平面视图视角来看所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之外的部分的最宽宽度与所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的最宽宽度大致相同。
21.根据权利要求17所述的半导体结构，其中所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分的至少一部分包括与所述硅主体的沟道区不同的半导体材料，并且其中所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的至少一部分包括所述半导体材料。
22.根据权利要求21所述的半导体结构，其中所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的整个部分均包括所述半导体材料，并且其中所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的整个部分均包括所述半导体材料。
23.根据权利要求17所述的半导体结构，其中所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之外的部分包括与所述硅主体的沟道区不同的半导体材料，但是所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分不包括所述半导体材料，并且其中所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之外的部分包括所述半导体材料，但是所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分不包括所述半导体材料。
24.根据权利要求17所述的半导体结构，其中相较于所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分以及所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的高度，所述沟道区的高度小了1-2纳米。
25.根据权利要求17所述的半导体结构，其中相较于所述沟道区的高度，所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分以及所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的高度大了1-7％，并且相较于所述沟道区的宽度，所述第一源极/漏极区的位于所述第一电介质侧壁间隔体之下的部分以及所述第二源极/漏极区的位于所述第二电介质侧壁间隔体之下的部分的宽度大了6-40％。
26.根据权利要求17所述的半导体结构，还包括：
所述栅极电极与所述沟道区之间的栅极电介质，其中所述栅极电介质包括顶部高k部分和底部二氧化硅或氮氧化硅部分。
27.根据权利要求26所述的半导体结构，其中所述栅极电极包括金属功函数设定层。
28.根据权利要求27所述的半导体结构，其中所述栅极电极还包括所述金属功函数设定层之上的非功函数设定填充材料。
29.一种制造半导体结构的方法，所述方法包括：
形成硅主体，其从下方的体硅衬底突出出来并且与所述下方的体硅衬底是连续的；
在所述硅主体的一部分之上形成牺牲栅极电极，其限定了所述硅主体中的位于所述牺牲栅极电极下方的第一沟道区，所述牺牲栅极电极具有第一侧和与所述第一侧相对的第二侧；
形成邻近所述牺牲栅极电极的所述第一侧的第一电介质侧壁间隔体，并且形成邻近所述牺牲栅极电极的所述第二侧的第二电介质侧壁间隔体；
形成第一源极/漏极区，其耦合到所述第一沟道区的第一端并且邻近所述栅极电极的所述第一侧，其中所述第一源极/漏极区的仅一部分位于所述第一电介质侧壁间隔体之下；以及形成第二源极/漏极区，其耦合到所述第一沟道区的第二端并且邻近所述栅极电极的所述第二侧，其中所述第二源极/漏极区的仅一部分位于所述第二电介质侧壁间隔体之下；
在形成所述第一源极/漏极区和所述第二源极/漏极区之后，去除所述牺牲栅极电极；
在去除所述牺牲栅极电极之后，蚀刻所述第一沟道区以形成第二沟道区，从平面视图视角来看所述第二沟道区包括第一锥形部分和第二锥形部分，所述第一锥形部分从所述第二沟道区的中央到所述第二沟道区的第一端变宽，并且所述第二锥形部分从所述第二沟道区的中央到所述第二沟道区的第二端变宽；以及
在蚀刻所述第一沟道区以形成所述第二沟道区之后，在所述第二沟道区之上并且在所述第一电介质间隔体和所述第二电介质间隔体之间形成永久栅极电极。
30.根据权利要求29所述的方法，其中形成所述第一源极/漏极区和所述第二源极/漏极区包括：
去除所述硅主体的位于所述第一电介质侧壁间隔体之下的部分的至少一部分，以及去除所述硅主体的位于所述第二电介质侧壁间隔体之下的部分的至少一部分；以及
外延生长与所述硅主体的沟道区不同的半导体材料，以形成嵌入的第一源极/漏极区和嵌入的第二源极/漏极区。
31.根据权利要求29所述的方法，其中形成所述第一源极/漏极区和所述第二源极/漏极区包括：
去除所述硅主体的位于所述第一电介质侧壁间隔体之下的直到牺牲栅极电极的所述第一侧的部分，以及去除所述硅主体的位于所述第二电介质侧壁间隔体之下的直到牺牲栅极电极的所述第二侧的部分；以及
外延生长与所述硅主体的沟道区不同的半导体材料，以形成嵌入的第一源极/漏极区和嵌入的第二源极/漏极区。
32.根据权利要求29所述的方法，其中形成所述第一源极/漏极区和所述第二源极/漏极区包括：
去除所述硅主体的位于所述第一电介质侧壁间隔体之外的部分但是不去除所述硅主体的位于所述第一电介质侧壁间隔体之下的任意部分，以及去除所述硅主体的位于所述第二电介质侧壁间隔体之外的部分但是不去除所述硅主体的位于所述第二电介质侧壁间隔体之下的任意部分；以及
外延生长与所述硅主体的沟道区不同的半导体材料，以形成嵌入的第一源极/漏极区和嵌入的第二源极/漏极区。
33.根据权利要求29所述的方法，其中蚀刻所述第一沟道区以形成所述第二沟道区包括将所述第一沟道区的高度减小1-2纳米。
34.根据权利要求29所述的方法，还包括：
在蚀刻所述第一沟道区以形成所述第二沟道区之后并且在形成所述永久栅极电极之前，在所述第二沟道区之上形成栅极电介质，其中所述栅极电介质包括底部二氧化硅或氮氧化硅部分和顶部高k部分。
35.根据权利要求34所述的方法，其中形成所述栅极电极包括形成金属功函数设定层。
36.根据权利要求35所述的方法，其中形成所述栅极电极还包括在所述金属功函数设定层之上形成非功函数设定填充材料。
CN201180076423.6A 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 Active CN104137265B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201710116832.3A CN107039281B (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN201710964294.3A CN107742640A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110583500.2A CN113540080A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110410997.8A CN113345952A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/066991 WO2013095550A1 (en) 2011-12-22 2011-12-22 Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Related Child Applications (4)

Application Number Title Priority Date Filing Date
CN201710116832.3A Division CN107039281B (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN201710964294.3A Division CN107742640A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110410997.8A Division CN113345952A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110583500.2A Division CN113540080A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Publications (2)

Publication Number Publication Date
CN104137265A CN104137265A (zh) 2014-11-05
CN104137265B true CN104137265B (zh) 2017-11-17

Family

ID=48669191

Family Applications (5)

Application Number Title Priority Date Filing Date
CN201710116832.3A Active CN107039281B (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110410997.8A Pending CN113345952A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110583500.2A Pending CN113540080A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN201180076423.6A Active CN104137265B (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN201710964294.3A Pending CN107742640A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Family Applications Before (3)

Application Number Title Priority Date Filing Date
CN201710116832.3A Active CN107039281B (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110410997.8A Pending CN113345952A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
CN202110583500.2A Pending CN113540080A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201710964294.3A Pending CN107742640A (zh) 2011-12-22 2011-12-22 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法

Country Status (5)

Country Link
US (7) US8941214B2 (zh)
CN (5) CN107039281B (zh)
DE (1) DE112011105996B4 (zh)
TW (6) TWI610445B (zh)
WO (1) WO2013095550A1 (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941214B2 (en) * 2011-12-22 2015-01-27 Intel Corporation Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
EP4044249A1 (en) * 2013-09-27 2022-08-17 Intel Corporation Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)
CN104576382B (zh) 2013-10-14 2017-09-12 中国科学院微电子研究所 一种非对称FinFET结构及其制造方法
CN104576385A (zh) * 2013-10-14 2015-04-29 中国科学院微电子研究所 一种FinFET结构及其制造方法
EP3087590A4 (en) * 2013-12-23 2017-11-22 Intel Corporation Pre-sculpting of si fin elements prior to cladding for transistor channel applications
CN110610866B (zh) * 2013-12-27 2023-05-30 英特尔公司 扩散的尖端延伸晶体管
US9431523B2 (en) * 2014-01-16 2016-08-30 Globalfoundries Inc. Local thinning of semiconductor fins
KR102252224B1 (ko) * 2014-03-24 2021-05-14 인텔 코포레이션 트랜지스터 채널 응용예들에 대한 대체 게이트 프로세스 동안의 핀 스컬프팅 및 클래딩
EP3123517A4 (en) * 2014-03-24 2017-11-29 Intel Corporation Techniques for achieving multiple transistor fin dimensions on a single die
US9570514B2 (en) * 2014-06-06 2017-02-14 Kabushiki Kaisha Toshiba Semiconductor device
US20160027775A1 (en) * 2014-07-25 2016-01-28 Globalfoundries Inc. Dual-width fin structure for finfets devices
US9496259B2 (en) 2015-04-14 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET semiconductor device having fins with stronger structural strength
US9418897B1 (en) 2015-06-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap around silicide for FinFETs
US9627378B2 (en) * 2015-06-30 2017-04-18 International Business Machines Corporation Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
US9728624B2 (en) * 2015-10-28 2017-08-08 International Business Machines Corporation Semiconductor testing devices
US9941377B2 (en) * 2015-12-29 2018-04-10 Qualcomm Incorporated Semiconductor devices with wider field gates for reduced gate resistance
KR102413610B1 (ko) 2016-03-02 2022-06-24 삼성전자주식회사 레이아웃 디자인 시스템, 이를 이용한 반도체 장치 및 그 제조 방법
US11018254B2 (en) * 2016-03-31 2021-05-25 International Business Machines Corporation Fabrication of vertical fin transistor with multiple threshold voltages
CN107706111B (zh) 2016-08-09 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9837406B1 (en) 2016-09-02 2017-12-05 International Business Machines Corporation III-V FINFET devices having multiple threshold voltages
CN111370466A (zh) * 2016-11-21 2020-07-03 华为技术有限公司 一种场效应晶体管及其制作方法
US10388763B2 (en) * 2016-12-15 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Manufacturing of semiconductor fin structure and manufacturing method of semiconductor device
DE102017127354A1 (de) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-bauelement und herstellungsverfahren dafür
US10707331B2 (en) * 2017-04-28 2020-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device with a reduced width
CN109560045B (zh) * 2017-09-25 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
DE112017007838T5 (de) * 2017-09-28 2020-05-07 Intel Corporation Transistoren mit kanal- und unterkanalregionen mit unterschiedlichen zusammensetzungen und abmessungen
CN115831969A (zh) * 2017-11-30 2023-03-21 英特尔公司 用于高级集成电路结构制造的鳍状物图案化
WO2019135766A1 (en) * 2018-01-08 2019-07-11 Intel Corporation Stacked transistor architecture having diverse fin geometry
US10461078B2 (en) * 2018-02-26 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Creating devices with multiple threshold voltage by cut-metal-gate process
CN108470766A (zh) * 2018-03-14 2018-08-31 上海华力集成电路制造有限公司 全包覆栅极晶体管及其制造方法
CN108470769A (zh) * 2018-03-14 2018-08-31 上海华力集成电路制造有限公司 鳍式晶体管及其制造方法
US11404423B2 (en) 2018-04-19 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Fin-based strap cell structure for improving memory performance
US10930768B2 (en) * 2018-10-18 2021-02-23 Samsung Electronics Co., Ltd. Low current leakage finFET and methods of making the same
US10957786B2 (en) * 2018-10-18 2021-03-23 Samsung Electronics Co., Ltd. FinFET with reduced extension resistance and methods of manufacturing the same
US11362199B2 (en) 2018-11-30 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
DE102019111297B4 (de) 2018-11-30 2023-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Bauelement und Verfahren
US11728335B2 (en) * 2019-01-25 2023-08-15 Intel Corporation Buried channel structure integrated with non-planar structures
CN110571265A (zh) * 2019-07-30 2019-12-13 西安电子科技大学 一种基于GaN的鳍式场效应晶体管器件及其制造方法
CN113540213B (zh) * 2020-04-17 2023-07-14 长鑫存储技术有限公司 有源区、有源区阵列及其形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
CN1311525C (zh) * 2003-07-28 2007-04-18 英特尔公司 制造超窄沟道半导体器件的方法

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19961528C1 (de) * 1999-12-20 2001-06-13 Siemens Ag Verfahren zur Überwachung des radialen Spalts zwischen dem Rotor und dem Stator eines elektrischen Generators und Vorrichtung zur Durchführung des Verfahrens
JP3476410B2 (ja) * 2000-03-01 2003-12-10 Ｎｅｃエレクトロニクス株式会社 露光用マスクの製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
CN1218400C (zh) 2002-06-14 2005-09-07 台湾积体电路制造股份有限公司 具有颈状信道的场效晶体管及其制造方法
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US8222680B2 (en) * 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US6857478B1 (en) 2003-01-29 2005-02-22 Junata E. Weber Packaged residential fire sprinkler system
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7095065B2 (en) * 2003-08-05 2006-08-22 Advanced Micro Devices, Inc. Varying carrier mobility in semiconductor devices to achieve overall design goals
US6927104B2 (en) * 2003-09-15 2005-08-09 Chartered Semiconductor Manufacturing Ltd. Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding
US7015534B2 (en) * 2003-10-14 2006-03-21 Texas Instruments Incorporated Encapsulated MOS transistor gate structures and methods for making the same
US7029958B2 (en) 2003-11-04 2006-04-18 Advanced Micro Devices, Inc. Self aligned damascene gate
KR100521384B1 (ko) * 2003-11-17 2005-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR100539008B1 (ko) * 2003-12-30 2005-12-27 동부아남반도체 주식회사 핀 트랜지스터 제조 방법
US7005700B2 (en) * 2004-01-06 2006-02-28 Jong Ho Lee Double-gate flash memory device
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7180134B2 (en) * 2004-01-30 2007-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for planar and multiple-gate transistors formed on SOI
KR100598099B1 (ko) 2004-02-24 2006-07-07 삼성전자주식회사 다마신 게이트를 갖는 수직 채널 핀 전계효과 트랜지스터 및 그 제조방법
US7122412B2 (en) 2004-04-30 2006-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a necked FINFET device
US7300837B2 (en) * 2004-04-30 2007-11-27 Taiwan Semiconductor Manufacturing Co., Ltd FinFET transistor device on SOI and method of fabrication
US7157350B2 (en) 2004-05-17 2007-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration
KR100532564B1 (ko) * 2004-05-25 2005-12-01 한국전자통신연구원 다중 게이트 모스 트랜지스터 및 그 제조 방법
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US6949768B1 (en) * 2004-10-18 2005-09-27 International Business Machines Corporation Planar substrate devices integrated with finfets and method of manufacture
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
TWI281257B (en) * 2005-03-30 2007-05-11 Taiwan Semiconductor Mfg Quasi-planar and FinFET-like transistors on bulk silicon
US7696537B2 (en) * 2005-04-18 2010-04-13 Toshiba America Electronic Components, Inc. Step-embedded SiGe structure for PFET mobility enhancement
KR100680291B1 (ko) * 2005-04-22 2007-02-07 한국과학기술원 Ｈ자형 이중 게이트 구조를 갖는 다중비트 비휘발성 메모리소자와 이의 제조 방법 및 다중비트 동작을 위한 동작방법
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7384838B2 (en) * 2005-09-13 2008-06-10 International Business Machines Corporation Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070152266A1 (en) 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
US8354311B2 (en) * 2006-04-04 2013-01-15 Micron Technology, Inc. Method for forming nanofin transistors
US7753074B2 (en) * 2006-07-28 2010-07-13 Masco Corporation Of Indiana Mixing valve
US7456471B2 (en) * 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
US7646046B2 (en) 2006-11-14 2010-01-12 Infineon Technologies Ag Field effect transistor with a fin structure
US8518767B2 (en) * 2007-02-28 2013-08-27 International Business Machines Corporation FinFET with reduced gate to fin overlay sensitivity
US7612405B2 (en) * 2007-03-06 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of FinFETs with multiple fin heights
US7560785B2 (en) * 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
US7667271B2 (en) * 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US7923337B2 (en) * 2007-06-20 2011-04-12 International Business Machines Corporation Fin field effect transistor devices with self-aligned source and drain regions
US9484435B2 (en) 2007-12-19 2016-11-01 Texas Instruments Incorporated MOS transistor with varying channel width
US8022487B2 (en) 2008-04-29 2011-09-20 Intel Corporation Increasing body dopant uniformity in multi-gate transistor devices
US8716786B2 (en) * 2008-06-17 2014-05-06 Infineon Technologies Ag Semiconductor device having different fin widths
CN102272905B (zh) * 2009-02-12 2014-01-29 松下电器产业株式会社 半导体装置及其制造方法
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8202780B2 (en) 2009-07-31 2012-06-19 International Business Machines Corporation Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions
US8313999B2 (en) * 2009-12-23 2012-11-20 Intel Corporation Multi-gate semiconductor device with self-aligned epitaxial source and drain
US8354719B2 (en) * 2010-02-18 2013-01-15 GlobalFoundries, Inc. Finned semiconductor device with oxygen diffusion barrier regions, and related fabrication methods
DE102010029527B4 (de) 2010-05-31 2012-04-05 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung eines selbstjustierenden Transistors mit Mehrfachgate auf einem Vollsubstrat
TWI433241B (zh) * 2010-06-24 2014-04-01 Inotera Memories Inc 具有浮置體之鰭式場效電晶體的製造方法
US8941214B2 (en) * 2011-12-22 2015-01-27 Intel Corporation Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
EP2831727B1 (en) * 2012-03-30 2018-09-26 Intel Corporation Accessing a device on a remote machine
KR101909204B1 (ko) * 2012-06-25 2018-10-17 삼성전자 주식회사 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법
US8765533B2 (en) * 2012-12-04 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) channel profile engineering method and associated device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
CN1311525C (zh) * 2003-07-28 2007-04-18 英特尔公司 制造超窄沟道半导体器件的方法

Also Published As

Publication number Publication date
CN107742640A (zh) 2018-02-27
TWI724633B (zh) 2021-04-11
US20190319121A1 (en) 2019-10-17
TW202139471A (zh) 2021-10-16
TWI802868B (zh) 2023-05-21
TW201717401A (zh) 2017-05-16
DE112011105996B4 (de) 2023-11-16
CN104137265A (zh) 2014-11-05
WO2013095550A1 (en) 2013-06-27
TW201543691A (zh) 2015-11-16
US20200235241A1 (en) 2020-07-23
US10651310B2 (en) 2020-05-12
DE112011105996T5 (de) 2014-09-04
TWI610445B (zh) 2018-01-01
US20170012132A1 (en) 2017-01-12
CN113540080A (zh) 2021-10-22
US11784257B2 (en) 2023-10-10
CN113345952A (zh) 2021-09-03
US11164975B2 (en) 2021-11-02
US8941214B2 (en) 2015-01-27
US20230013575A1 (en) 2023-01-19
US20220005953A1 (en) 2022-01-06
TW201342603A (zh) 2013-10-16
US9711410B2 (en) 2017-07-18
TW202013745A (zh) 2020-04-01
TWI506786B (zh) 2015-11-01
TWI565077B (zh) 2017-01-01
TW201826543A (zh) 2018-07-16
US10319843B2 (en) 2019-06-11
US20130313610A1 (en) 2013-11-28
TW202308171A (zh) 2023-02-16
CN107039281A (zh) 2017-08-11
CN107039281B (zh) 2021-06-18
US20150147863A1 (en) 2015-05-28
TWI680584B (zh) 2019-12-21

Similar Documents

Publication Publication Date Title
CN104137265B (zh) 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US20220130962A1 (en) Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same
US8889508B2 (en) Precision resistor for non-planar semiconductor device architecture
EP3050106B1 (en) Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)
US9978636B2 (en) Isolated and bulk semiconductor devices formed on a same bulk substrate
US20130320455A1 (en) Semiconductor device with isolated body portion
US9881927B2 (en) CMOS-compatible polycide fuse structure and method of fabricating same
US20130320448A1 (en) Semiconductor devices having three-dimensional bodies with modulated heights
TWI834335B (zh) 具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant