TWI506786B - 具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法 - Google Patents

具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法 Download PDF

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TWI506786B
TWI506786B TW101146193A TW101146193A TWI506786B TW I506786 B TWI506786 B TW I506786B TW 101146193 A TW101146193 A TW 101146193A TW 101146193 A TW101146193 A TW 101146193A TW I506786 B TWI506786 B TW I506786B
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semiconductor device
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substrate
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TW201342603A (zh
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Bernhard Sell
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Intel Corp
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Description

具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法
本發明的實施例為半導體裝置及製程的領域，且尤其為具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法。
在過去幾十年，積體電路中的特性圖案之縮放已經成為不斷增長的半導體產業背後的驅動力。縮放至愈來愈小的特性圖案使半導體晶片的有限基板面上的功能單元之密度能夠增加。例如，縮小電晶體尺寸容許較多數量的記憶體或邏輯裝置被併入晶片上，給予製造出具較多容量的產品。然而對愈多容量的需要並非沒有問題。最佳化各個裝置的性能之必要性變得愈來愈重要。
在製造積體電路裝置中，多閘極電晶體(諸如FIN-FET及三閘極電晶體)已隨著裝置尺寸持續縮小而變得較為普遍。在習知製程中，FIN-FET及三閘極電晶體一般被製造於大塊矽基板或者絕緣體上矽基板上。在一些例子中，大塊矽基板較佳，因為它們的成本較低且因為它們可以致能較不複雜的FIN-FET及三閘極製造程序。在其他例子中，絕緣體上矽基板較佳是因為FIN-FET及三閘極電晶體的短通道性能被改善。
然而縮放多閘極電晶體並非沒有後果。隨著這些微電子電路的基本建構區塊之尺寸被減小且隨著給定區中所製 造之大量基本建構區塊被增加，此種裝置運作期間對外部電阻(Rext )的限制已經變得無法克服。已經嘗試許多不同技術來改善電晶體的Rext ，包括改善接觸金屬、增加摻雜劑的活性及降低半導體與接觸金屬間的障壁。然而，Rext 降低的領域中仍需要顯著改善。
本發明的實施例包括了具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法。
在實施例中，一種半導體裝置包括被設置於基板之上的半導體本體。閘極電極堆疊被設置於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區。源極與汲極區被界定於該閘極電極堆疊的兩側上的半導體本體中。側壁間隔物被設置成相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上。該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本體的通道區之高度與寬度更大的高度與寬度。
在另一實施例中，一種製造半導體裝置的方法包括形成半導體本體於基板之上。閘極電極堆疊被形成於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區以及該閘極電極堆疊的兩側上的半導體本體中的源極與汲極區。側壁間隔物被形成為相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上。該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本 體的通道區之高度與寬度更大的高度與寬度。
在另一實施例中，一種製造半導體裝置的方法包括形成硬遮罩圖案於基板之上。該硬遮罩圖案包括第一區的多數鰭片形成特性圖案，各者具第一寬度。該硬遮罩圖案也包括第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度。隨後，抗蝕層被形成及圖案化以覆蓋該第二區及暴露該第一區。隨後，該第一區的多數鰭片形成特性圖案被蝕刻以形成多數薄化鰭片形成特性圖案，各者具小於該第二寬度的第三寬度。隨後，該抗蝕層被移除。隨後，該硬遮罩圖案被轉移至該基板以形成第一區的多數鰭片，各者具該第三寬度，且形成第二區的多數鰭片，各者具該第二寬度。隨後，半導體裝置從該等第一及第二區的多數鰭片加以形成。
在另一實施例中，一種製造半導體裝置的方法包括形成硬遮罩圖案於基板之上。該硬遮罩圖案包括第一區的多數鰭片形成特性圖案，各者具第一寬度。該硬遮罩圖案也包括第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度。隨後，該硬遮罩圖案被轉移至該基板以形成第一區的多數鰭片，各者具該第一寬度，且形成第二區的多數鰭片，各者具該第二寬度。隨後，抗蝕層被形成及圖案化以覆蓋該第二區的多數鰭片及暴露該第一區的多數鰭片。隨後，該第一區的多數鰭片被蝕刻以形成多數薄化鰭片，各者具小於該第二寬度的第三寬度。隨後，該抗蝕層被移除。隨後，半導體裝置從該等第一及第二區 的多數鰭片加以形成。
具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法被描述。在下列實施方式中，數個特定細節被陳述，諸如特定整合與材料體系，以便提供本發明實施例的徹底理解。對熟習本技藝之人士而言將顯而易見的是，本發明的實施例可在沒有這些特定細節的情況下加以實行。在其他例子中，熟知的特徵(諸如積體電路設計佈局)未被詳細描述以便不會不必要地模糊本發明的實施例。進一步而言，將理解的是，圖中所示的各種實施例為例示性表示且不必然按比例繪製。
本發明的一或更多個實施例目標為具有下列的半導體裝置：(1)對間隔物下方的鰭片寬度而言不同的主動通道區中的鰭片寬度，(2)在相同晶粒上的不同主動通道中具至少二個不同鰭片寬度的積體電路，(3)圖案化製程，在蝕刻真實鰭片前界定二個不同鰭片寬度，(4)圖案化製程，以在犧牲虛擬閘極移除製程以後、或其組合以後界定二個不同鰭片寬度。一或更多個實施例目標為改善諸如電晶體的裝置的驅動電流且建構具有閒置耗電低與主動性能高的電路。
FinFET中的鰭片之寬度影響臨限電壓(Vt)及該裝置的外部電阻。針對高性能裝置，可能有益處的是具有具較高Vt及較低電阻的相對較寬鰭片。針對低功率裝置， 相反才是正確。目前，該製程必須針對這些裝置的一個加以最佳化。可能有益處的是兩個裝置具有最佳性能來最佳化產品功率性能。例如，低功率裝置藉由額外的井摻雜加以產生，導致了會降低(尤其在低電源供應電壓時)驅動電流的較高Vt及較高接面洩漏。替代地，該製程針對低功率裝置加以最佳化，導致高性能裝置的驅動電流被降低。本發明的實施例可藉由提供相同晶粒上的二個不同裝置或者藉由具有低Vt及低外部電阻兩者的裝置，致能高性能與低功率裝置的同時最佳化。
在第一態樣中，具有頸部半導體本體的半導體裝置及形成具有頸部半導體本體的半導體裝置的方法被提供。此種電晶體結構在通道中及在間隔物下方的鰭片區中具有不同鰭片寬度。頸部鰭片可改善在鰭片CD被縮放時的短通道效應改善與外部電阻間的權衡，改善最佳裝置的驅動電流。
在實例中，第1A圖示出了依據本發明實施例之具有頸部半導體本體的半導體裝置之平面圖。第1B圖示出了依據本發明實施例之第1A圖的半導體裝置沿著a-a’軸所取得的剖面圖。第1C圖示出了依據本發明實施例之第1A圖的半導體裝置沿著b-b’軸所取得的剖面圖。
參照第1A至1C圖，半導體裝置100包括被設置於基板102之上的半導體本體104。閘極電極堆疊106被設置於半導體本體104的一部分之上以界定閘極電極堆疊106下方的半導體本體104中的通道區108。源極與汲極 區110被界定於閘極電極堆疊106的兩側上的半導體本體104中。側壁間隔物112被設置成相鄰於閘極電極堆疊106且在僅源極與汲極區110的一部分之上。
參照第1B及1C圖，源極與汲極區110在側壁間隔物112下方的該部分具有比半導體本體104的通道區108之高度(H1)與寬度(W1)更大的高度(H2)與寬度(W2)。高度H1及H2被定義為半導體本體104在隔離層114之上的各別部分之高度，如第1B及1C圖中所示。
參照第1A圖，在實施例中，源極與汲極區110未在側壁間隔物112下方的部分具有比源極與汲極區110在側壁間隔物112下方的該部分之高度(H2)與寬度(W2)更大的高度與寬度(W3)，例如，W3>W2。替代地，在另一實施例中，源極與汲極區110未在側壁間隔物112下方的部分具有與源極與汲極區110在側壁間隔物112下方的該部分之高度(H2)與寬度(W2)大約相同的高度與寬度(W3)，例如，W3=W2。
在實施例中，源極與汲極區110的至少一部分為源極與汲極區110的嵌埋部分。即，在形成源極與汲極區110時，原始半導體本體104的一部分被移除且被半導體本體104的新部分替換(例如，藉由磊晶生長)。例如，在一個此種實施例中，源極與汲極區110的該嵌埋部分由不同於通道區108的半導體材料所構成。在一個實施例中，該嵌埋部分不包括源極與汲極區110在側壁間隔物112下方 的該部分。在另一實施例中，該嵌埋部分包括至少部份及可能所有的源極與汲極區110在側壁間隔物112下方的該部分。
在實施例中，參照第1B及1C圖，基板102為結晶基板，且半導體本體104(例如，第1B圖中的通道區108及第1C圖中的源極與汲極區110)與結晶基板102連續。即，半導體本體104從大塊基板加以形成。在替代實施例中(未顯示)，介電層被設置於該於該半導體本體與該基板間，且該半導體本體與該基板不連續，例如，如同絕緣體上矽(SOI)基板的情況。
在實施例中，通道區108具有大約範圍在30-50奈米的高度(H1)及大約範圍在10-30奈米的寬度(W1)。在該實施例中，通道區108的高度(H1)比源極與汲極區110在側壁間隔物112下方的該部分之高度(H2)少大約1-2奈米。並且，通道區108的寬度(W1)比源極與汲極區110在側壁間隔物112下方的該部分之寬度(W2)少大約2-4奈米。在實施例中，源極與汲極區110在側壁間隔物112下方的該部分之高度(H2)比通道區108的高度(H1)大大約1-7%。在該實施例中，源極與汲極區110在側壁間隔物112下方的該部分之寬度(W2)比通道區108的寬度(W1)大大約6-40%。
第1A至1C圖中的半導體裝置100之可能實施例被描述於下。在第一實例中，第2A圖示出了依據本發明實施例之具有頸部半導體本體的半導體裝置之平面圖。參照 第2A圖，通道區108係由步階特性圖案120耦接至源極與汲極區110在側壁間隔物112下方的該部分。閘極電極堆疊106被描繪為虛線以透視下層通道區108。並且，源極與汲極區110未在間隔物112下方的該部分之尺寸較大的選項以源極與汲極區110周圍的長虛線加以描繪。
在第二實例中，第2B圖示出了依據本發明另一實施例之具有頸部半導體本體的另一半導體裝置之平面圖。參照第2B圖，通道區108係由刻面特性圖案130耦接至源極與汲極區110在側壁間隔物112下方的該部分。閘極電極堆疊106被描繪為虛線以透視下層通道區108。並且，源極與汲極區110未在間隔物112下方的該部分之尺寸較大的選項以源極與汲極區110周圍的長虛線加以描繪。
在第三實例中，第2C圖示出了依據本發明另一實施例之具有頸部半導體本體的另一半導體裝置之平面圖。參照第2C圖，通道區108係由圓角特性圖案140耦接至源極與汲極區110在側壁間隔物112下方的該部分。閘極電極堆疊106被描繪為虛線以透視下層通道區108。並且，源極與汲極區110未在間隔物112下方的該部分之尺寸較大的選項以源極與汲極區110周圍的長虛線加以描繪。
因此，再次參照第2B及2C圖，在實施例中，通道區104係由漸變(graded)特性圖案(例如，120或140)耦接至源極與汲極區110在側壁間隔物112下方的該部分。在實施例中，該漸變特性圖案在半導體裝置110的操作期間降低重疊電容及展佈電阻。
在實施例中，如關於製程流程600及700加以較詳細描述於下，半導體裝置100被設置於相同基板102之上作為具有通道區的第二半導體裝置。在該實施例中，該第二半導體裝置的通道區的最窄寬度大於半導體裝置100的通道區108的最窄寬度(例如，W1)。
半導體裝置100可為任何併入閘極、通道區及一對源極/汲極區的半導體裝置。在實施例中，半導體裝置100為一種諸如但不限於MOS-FET或微機電系統(MEMS)的半導體裝置。在一個實施例中，半導體裝置100為三維MOS-FET且為或隔離裝置或者為複數個巢套裝置中的一個裝置。如被理解的一個典型積體電路，N通道及P通道電晶體兩者可被製造於單一基板上以形成CMOS積體電路。
基板102及因此半導體本體104可能由可承受製造程序且電荷可在其中遷移的半導體材料所構成。在實施例中，基板102為大塊基板，且半導體本體104與大塊基板102連續。在實施例中，基板102由結晶矽、矽/鍺或以電荷載子(諸如但不限於磷、砷、硼或其組合)摻雜的鍺層所構成。在一個實施例中，基板102中的矽原子之濃度大於97%，或替代地，摻雜原子的濃度小於1%。在另一實施例中，基板102由生長於不同結晶基板頂上的磊晶層所構成，例如生長於硼摻雜大塊矽單晶基板頂上的矽磊晶層。基板102也可包括被設置於大塊結晶基板與磊晶層間的絕緣層，以形成例如絕緣體上矽基板。在此種實例中， 半導體本體104可能為隔離半導體本體。在實施例中，該絕緣層由諸如但不限於二氧化矽、氮化矽、氮氧化矽或高k介電層的材料所構成。基板102可替代地由III-V族材料所構成。在實施例中，基板102由III-V材料所構成，諸如但不限於氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、銦鎵砷化物、鋁鎵砷化物、銦鎵磷化物、或其組合。半導體本體104可由多個半導體材料所構成，其各者可包括額外的摻雜原子。在一個實施例中，基板102由結晶矽所構成且電荷載子摻雜劑雜質原子為諸如但不限於硼、砷、銦或磷的原子。在另一實施例中，基板102由III-V材料所構成且電荷載子摻雜劑雜質原子為諸如但不限於碳、矽、鍺、氧、硫、硒或碲的原子。在另一實施例中，半導體本體104為未經摻雜或僅輕度摻雜。額外地，通常在習知裝置製造中所使用的暈摻雜可能在一個實施例中從半導體裝置100的製造中消除。將理解的是，在實施例中半導體本體104的材料不同於基板102的材料。
在另一實施例中，半導體裝置100為非平面裝置，諸如但不限於fin-FET或三閘極裝置。在此種裝置中，半導體本體104由三維體所構成或從三維體所形成。在一個此種實施例中，閘極電極堆疊106圍繞該三維體的至少頂表面及一對側壁。在另一實施例中，半導體本體104被製成分離的三維體，諸如在奈米線裝置中。在一個此種實施例中，閘極電極堆疊106完全圍繞半導體本體104的一部分。
閘極電極堆疊106可包括閘極電極及下層閘極介電層。在實施例中，閘極電極堆疊106的閘極電極由金屬閘極所構成且該閘極介電層由高K材料所構成。例如，在一個實施例中，該閘極介電層由諸如但不限於氧化鉿、氮氧化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉛鈧鉭氧化物(lead scandium tantalum oxide)、鈮酸鉛鋅、或其組合的材料所構成。此外，閘極介電層的一部分可包括從半導體本體104的頂部幾層所形成的一層原生氧化物。在實施例中，該閘極介電層由頂部高k部分及下方部分(由半導體材料的氧化物所構成)所構成。在一個實施例中，該閘極介電層由氧化鉿的頂部部分及二氧化矽或氮氧化矽的底部部分所構成。
在一個實施例中，該閘極電極由諸如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳或導電性金屬氧化物的金屬層所構成。在特定實施例中，該閘極電極由被形成於金屬功函數設定層之上的非功函數設定填充材料所構成。在實施例中，該閘極電極由P型材料所構成。在另一實施例中，該閘極電極由N型材料所構成。在另一實施例中，該閘極電極由中間能隙材料所構成。在特定的此種實施例中，對應的通道區為未經摻雜或為僅輕度摻雜。
在實施例中，側壁間隔物112由絕緣性介電材料所構成，諸如但不限於二氧化矽、碳化矽、氮氧化矽或氮化 矽。同樣地，介電層114可由絕緣性介電材料所構成，諸如但不限於二氧化矽、碳化矽、氮氧化矽或氮化矽。
形成諸如以上所述的裝置之方法也被預期在本發明實施例的精神與範圍內。在第一實例中，第3圖示出了依據本發明實施例之製造具有頸部半導體本體的半導體裝置之方法中的製程流程300。
參照製程流程300的A部份，厚鰭片302被形成，犧牲閘極304被圖案化，閘極間隔物306藉由全面性沈積(blanket deposition)與隨後的蝕刻來加以形成，且源極-汲極區308被形成。額外地，層間介電膜310可被沈積及拋光以暴露犧牲閘極304。參照製程流程300的B部份，犧牲閘極304被移除且厚鰭片302被蝕刻以形成具減少厚度的薄化鰭片312，例如，減少大約範圍在1-5奈米的量。參照製程流程300的C部份，永久閘極堆疊320被形成於薄化鰭片312之上。例如，高k閘極介電層及金屬閘極電極可被形成。在實施例中，薄化鰭片312提供改善的短通道效應，而源極與汲極區308在間隔物306下方的較寬部分有助於降低外部電阻。
犧牲閘極304在實施例中由適於在替換閘極操作時移除的材料所構成。在一個實施例中，犧牲閘極304由多晶矽、非晶矽、二氧化矽、氮化矽、或其組合所構成。在另一實施例中，諸如二氧化矽或氮化矽層的保護性蓋層(未顯示)被形成於犧牲閘極304之上。在實施例中，下層的虛擬閘極介電層(也未顯示)被含括。在實施例中，犧牲 閘極304包括側壁間隔物306，其可由適於最終電隔離永久閘極結構與相鄰導電接點的材料所構成。例如，在一個實施例中，間隔物306由介電材料所構成，諸如但不限於二氧化矽、氮氧化矽、氮化矽、或碳摻雜的氮化矽。
在實施例中，犧牲閘極304藉由乾蝕刻或濕蝕刻製程加以移除。在一個實施例中，犧牲閘極304由多晶矽或非晶矽所構成且藉由使用SF6 的濕蝕刻製程加以移除。在另一實施例中，犧牲閘極304由多晶矽或非晶矽所構成且藉由使用NH4 OH水溶液或氫氧化四甲基銨的濕蝕刻製程加以移除。在一個實施例中，犧牲閘極304由氮化矽所構成且藉由使用磷酸水溶液的濕蝕刻加以移除。
鰭片302可藉由任何移除鰭片302的一部分而沒有不利影響其他存在的半導體特性圖案之合適技術加以薄化以形成312，諸如藉由使用乾蝕刻或濕蝕刻製程。在一個實施例中，鰭片302藉由使用乾電漿蝕刻(使用NF3 、HBr、SF6 /Cl或Cl2 )加以薄化以形成312。在另一實施例中，濕蝕刻製程被使用。
在第二實例中，第4圖示出了依據本發明實施例之製造具有頸部半導體本體的半導體裝置之方法中的製程流程400。參照製程流程400的A部份，薄鰭片412被形成，犧牲閘極404被圖案化，且薄源極-汲極區408被形成。參照製程流程400的B部份，閘極間隔物406藉由全面性沈積與隨後的蝕刻來加以形成，且厚源極與汲極區418藉由例如磊晶生長來加以形成。額外地，層間介電膜410可 被沈積及拋光以暴露犧牲閘極404。犧牲閘極404被接著移除，如B部份中所示。參照製程流程400的C部份，永久閘極堆疊420被形成於薄鰭片412之上。例如，高k閘極介電層及金屬閘極電極可被形成。在實施例中，薄鰭片412提供改善的短通道效應，而源極與汲極區408/418在間隔物406下方的較寬部分有助於降低外部電阻。犧牲閘極形成及替換可如同以上關於製程流程300所述來加以實施。
因此，在實施例中，一種製造半導體裝置的方法包括形成半導體本體於基板之上。閘極電極堆疊被形成於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區以及該閘極電極堆疊的兩側上的半導體本體中的源極與汲極區。側壁間隔物被形成為相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上。該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本體的通道區之高度與寬度更大的高度與寬度。
在一個此種實施例中，形成該閘極電極堆疊包括形成犧牲閘極電極堆疊、移除該犧牲閘極電極堆疊、及形成永久閘極電極堆疊。在該實施例中，形成該通道區包括薄化該半導體本體在移除該犧牲閘極電極堆疊之後且在形成該永久閘極電極堆疊之前所暴露的部分，例如如同關於製程流程300所述。在另一此種實施例中，形成該閘極電極堆疊包括形成犧牲閘極電極堆疊、移除該犧牲閘極電極堆疊、及形成永久閘極電極堆疊。在該實施例中，形成該源 極與汲極區包括擴展該半導體本體在移除該犧牲閘極電極堆疊以前所暴露的部分，例如如同關於製程流程400所述。
第5A圖包括了依據本發明實施例之具有頸部半導體本體的半導體裝置對沒有頸部半導體本體的半導體裝置的驅動電流增益(% Idsat增益)作為矽通道厚度(微米)之函數的曲線圖500A。第5B圖包括了依據本發明實施例之具有頸部半導體本體的半導體裝置對沒有頸部半導體本體的半導體裝置的驅動電流增益(% Idlin增益)作為矽通道厚度(微米)之函數的曲線圖500B。參照曲線圖500A及500B，由前方矽寬度(Wsi)定義所形成的鰭片相較於替換閘極操作期間所定義之具薄化矽寬度(Wsi)的鰭片，例如，如同關於製程300所述。該等曲線圖顯示薄化鰭片裝置的預期驅動電流增益。
在第二態樣中，形成具有變化寬度的半導體本體的方法被提供。此種製程可使不同鰭片寬度形成於相同晶粒內。使用較寬鰭片寬度裝置於高性能應用以及較低鰭片寬度裝置於較低功率(低待機洩漏)應用可因此在相同晶粒上達成。
在第一實例中，第6圖示出了依據本發明實施例之製造具有變化寬度的半導體本體的半導體裝置之方法中的製程流程600。
參照製程流程600的A部份，硬遮罩603A/603B形成於基板602之上(例如，於結晶矽基板之上)以供最終 鰭片形成係包括沈積及圖案化硬遮罩層。圖案化的硬遮罩層603A/603B包括最終薄鰭片形成區604及最終厚鰭片形成區606。參照製程流程600的B部份，將保持較寬的鰭片(例如，在區606中)以抗蝕層608加以阻擋且暴露的硬遮罩603A被蝕刻以減少該等線的寬度。參照製程流程600的C部份，抗蝕層608被接著移除(例如包括灰化製程)，且新硬遮罩圖案603A/603B被轉移至基板602中以形成鰭片610A及610B。替代地，在實施例中，額外的微影鰭片薄化可在該等鰭片被蝕刻至該基板中以後且在圖案化犧牲閘極以前加以實施。在實施例中，硬遮罩區603A/603B首先藉由間隔物圖案化流程加以形成，其可被用來有效使被用來形成該等特性圖案的微影製程之間距(pitch)加倍。製程流程600保留該間隔物圖案化流程的間距。
因此，在實施例中，一種製造半導體裝置的方法包括形成硬遮罩圖案於基板之上。該硬遮罩圖案包括第一區的多數鰭片形成特性圖案，各者具第一寬度。該硬遮罩圖案也包括第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度。隨後，抗蝕層被形成及圖案化以覆蓋該第二區及暴露該第一區。隨後，該第一區的多數鰭片形成特性圖案被蝕刻以形成多數薄化鰭片形成特性圖案，各者具小於該第二寬度的第三寬度。隨後，該抗蝕層被移除。隨後，該硬遮罩圖案被轉移至該基板以形成第一區的多數鰭片，各者具該第三寬度，且形成第二區的多數 鰭片，各者具該第二寬度。隨後，半導體裝置從該等第一及第二區的多數鰭片加以形成。在一個此種實施例中，該基板為單晶矽基板，且轉移該硬遮罩圖案至該基板包括形成單晶矽鰭片。
在第二實例中，第7圖示出了依據本發明實施例之製造具有變化寬度的半導體本體的半導體裝置之方法中的製程流程700。
參照製程流程700的A部份，硬遮罩703A/703B形成於基板702之上(例如，於結晶矽基板之上)以供鰭片形成係包括沈積及圖案化硬遮罩層。圖案化的硬遮罩層703A/703B包括薄鰭片形成區704及厚鰭片形成區706。硬遮罩圖案703A/703B被接著轉移至基板702中以形成對應的鰭片。犧牲閘極圖案化及延伸源極與汲極形成可接著被實施。並且，層間介電材料可被沈積及接著拋光以顯露該等犧牲閘極。該等犧牲閘極被接著移除。參照製程流程700的B部份，將保持較寬的鰭片710B(例如，在區706中)以抗蝕層708加以阻擋。鰭片薄化蝕刻被用來減少鰭片710A的鰭片寬度。參照製程流程700的C部份，抗蝕層708被移除(例如包括灰化製程)，且標準裝置製造技術可藉由使用較薄鰭片710A及較寬鰭片710B加以實施。在實施例中，硬遮罩區703A/703B首先藉由間隔物圖案化流程加以形成，其可被用來有效使被用來形成該等特性圖案的微影製程之間距加倍。製程流程700保留該間隔物圖案化流程的間距。
因此，在實施例中，一種製造半導體裝置的方法包括形成硬遮罩圖案於基板之上。該硬遮罩圖案包括第一區的多數鰭片形成特性圖案，各者具第一寬度。該硬遮罩圖案也包括第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度。隨後，該硬遮罩圖案被轉移至該基板以形成第一區的多數鰭片，各者具該第一寬度，且形成第二區的多數鰭片，各者具該第二寬度。隨後，抗蝕層被形成及圖案化以覆蓋該第二區的多數鰭片及暴露該第一區的多數鰭片。隨後，該第一區的多數鰭片被蝕刻以形成多數薄化鰭片，各者具小於該第二寬度的第三寬度。隨後，該抗蝕層被移除。隨後，半導體裝置從該等第一及第二區的多數鰭片加以形成。在一個此種實施例中，該基板為單晶矽基板，且轉移該硬遮罩圖案至該基板包括形成單晶矽鰭片。
此處所述的製程可被用來製造一或複數個半導體裝置。該等半導體裝置可能為電晶體或相似裝置。例如，在實施例中，該等半導體裝置為用於邏輯或記憶體的金屬氧化物半導體(MOS)電晶體，或為雙極電晶體。並且，在實施例中，該等半導體裝置具有三維架構，諸如三閘極裝置、獨立存取的雙閘極裝置、或FIN-FET。
第8圖示出了依據本發明一個實施方式的運算裝置800。運算裝置800容納主機板802。主機板802可包括數個組件，包括但不限於處理器804及至少一個通訊晶片806。處理器804被實體及電耦接至主機板802。在一些 實施方式中，至少一個通訊晶片806也被實體及電耦接至主機板802。在另外的實施方式中，通訊晶片806為處理器804的一部份。
取決於其應用，運算裝置800可包括可能或可能未實體及電耦接至主機板802的其他組件。這些其他組件包括但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚聲器、攝影機、及大量儲存裝置(諸如硬碟機、光碟(CD)、數位多媒體光碟(DVD)等)。
通訊晶片806致能無線通訊以供資料傳輸進出運算裝置800。術語「無線」及其衍生詞可被用來描述可經由使用調變的電磁輻射通過非固體媒體來傳送資料的電路、裝置、系統、方法、技術、通訊頻道等。該術語未暗指相關裝置不含有任何導線，儘管在一些實施例中它們可能不含有。通訊晶片806可實施數個無線標準或協定的任一者，包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生、以及被標記為3G、4G、5G、與往後的任何其他無線協定。 運算裝置800可包括複數個通訊晶片806。例如，第一通訊晶806可專用於短程無線通訊(諸如Wi-Fi及藍芽)且第二通訊晶片806可專用於長程無線通訊(諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他)。
運算裝置800的處理器804包括被封裝於處理器804內的積體電路晶粒。在本發明的一些實施方式中，該處理器的積體電路晶粒包括一或更多個裝置，諸如依據本發明實施方式所建造的MOS-FET。術語「處理器」可意指任何裝置或裝置的部分，其處理來自暫存器及/或記憶體的電子資料以轉換該電子資料成為可被儲存於暫存器及/或記憶體中的其他電子資料。
通訊晶片806也包括被封裝於通訊晶片806內的積體電路晶粒。依據本發明的另一實施方式，該通訊晶片的積體電路晶粒包括一或更多個裝置，諸如依據本發明實施方式所建造的MOS-FET。
在另外的實施方式中，運算裝置800內所容納的另一組件可含有包括一或更多個裝置的積體電路晶粒，該一或更多個裝置諸如依據本發明實施方式所建造的MOS-FET。
在各種實施方式中，運算裝置800可為膝上型電腦、小筆電、筆記型電腦、超極致筆電、智慧型手機、平板、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂 控制單元、數位攝影機、可攜式音樂播放器、或數位錄影機。在另外的實施方式中，運算裝置800可為處理資料的任何其他電子裝置。
因此，具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法被描述。在實施例中，一種半導體裝置包括被設置於基板之上的半導體本體。閘極電極堆疊被設置於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區。源極與汲極區被界定於該閘極電極堆疊的兩側上的半導體本體中。側壁間隔物被設置成相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上。該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本體的通道區之高度與寬度更大的高度與寬度。在一個實施例中，該半導體裝置被設置於相同基板之上作為具有通道區的第二半導體裝置，且該第二半導體裝置的通道區的最窄寬度大於該半導體裝置的通道區的最窄寬度。
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧半導體本體
106‧‧‧閘極電極堆疊
108‧‧‧通道區
110‧‧‧源極與汲極區
112‧‧‧側壁間隔物
114‧‧‧隔離層
120‧‧‧步階特性圖案
130‧‧‧刻面特性圖案
140‧‧‧圓角特性圖案
300‧‧‧製程流程
302‧‧‧厚鰭片
304‧‧‧犧牲閘極
306‧‧‧間隔物
308‧‧‧源極-汲極區
310‧‧‧層間介電膜
312‧‧‧薄化鰭片
320‧‧‧永久閘極堆疊
400‧‧‧製程流程
404‧‧‧犧牲閘極
406‧‧‧間隔物
408‧‧‧薄源極-汲極區
410‧‧‧層間介電膜
412‧‧‧薄鰭片
418‧‧‧厚源極與汲極區
420‧‧‧永久閘極堆疊
500A‧‧‧曲線圖
500B‧‧‧曲線圖
600‧‧‧製程流程
602‧‧‧基板
603A‧‧‧硬遮罩
603B‧‧‧硬遮罩
604‧‧‧區
606‧‧‧區
608‧‧‧抗蝕層
610A‧‧‧鰭片
610B‧‧‧鰭片
700‧‧‧製程流程
702‧‧‧基板
703A‧‧‧硬遮罩
703B‧‧‧硬遮罩
704‧‧‧區
706‧‧‧區
708‧‧‧抗蝕層
710A‧‧‧鰭片
710B‧‧‧鰭片
800‧‧‧運算裝置
802‧‧‧主機板
804‧‧‧處理器
806‧‧‧通訊晶片
第1A圖示出了依據本發明實施例之具有頸部半導體本體的半導體裝置之平面圖。
第1B圖示出了依據本發明實施例之第1A圖的半導體裝置沿著a-a’軸所取得的剖面圖。
第1C圖示出了依據本發明實施例之第1A圖的半導體裝置沿著b-b’軸所取得的剖面圖
第2A圖示出了依據本發明實施例之具有頸部半導體本體的半導體裝置之平面圖。
第2B圖示出了依據本發明另一實施例之具有頸部半導體本體的另一半導體裝置之平面圖。
第2C圖示出了依據本發明另一實施例之具有頸部半導體本體的另一半導體裝置之平面圖。
第3圖示出了依據本發明實施例之製造具有頸部半導體本體的半導體裝置之方法中的製程流程。
第4圖示出了依據本發明實施例之製造具有頸部半導體本體的半導體裝置之方法中的製程流程。
第5A圖包括了依據本發明實施例之具有頸部半導體本體的半導體裝置對沒有頸部半導體本體的半導體裝置的驅動電流增益(% Idsat增益)作為矽通道厚度(微米)之函數的曲線圖。
第5B圖包括了依據本發明實施例之具有頸部半導體本體的半導體裝置對沒有頸部半導體本體的半導體裝置的驅動電流增益(% Idlin增益)作為矽通道厚度(微米)之函數的曲線圖。
第6圖示出了依據本發明實施例之製造具有變化寬度的半導體本體的半導體裝置之方法中的製程流程。
第7圖示出了依據本發明實施例之製造具有變化寬度的半導體本體的半導體裝置之方法中的製程流程。
第8圖示出了依據本發明一個實施方式的運算裝置。
300‧‧‧製程流程
302‧‧‧厚鰭片
304‧‧‧犧牲閘極
306‧‧‧間隔物
308‧‧‧源極-汲極區
310‧‧‧層間介電膜
312‧‧‧薄化鰭片
320‧‧‧永久閘極堆疊

Claims (22)

  1. 一種半導體裝置，包含：半導體本體，設置於基板之上；閘極電極堆疊，設置於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區以及該閘極電極堆疊的兩側上的半導體本體中的源極與汲極區；及側壁間隔物，設置成相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上，其中該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本體的通道區之高度與寬度更大的高度與寬度。
  2. 如申請專利範圍第1項之半導體裝置，其中該源極與汲極區未在該等側壁間隔物下方的該部分具有比該源極與汲極區在該等側壁間隔物下方的該部分之高度與寬度更大的高度與寬度。
  3. 如申請專利範圍第1項之半導體裝置，其中該源極與汲極區未在該等側壁間隔物下方的部分具有與該源極與汲極區在該等側壁間隔物下方的該部分之高度與寬度大約相同的高度與寬度。
  4. 如申請專利範圍第1項之半導體裝置，其中該源極與汲極區的至少一部分為該源極與汲極區的磊晶部分。
  5. 如申請專利範圍第4項之半導體裝置，其中該源極與汲極區的該磊晶部分包含不同於該通道區的半導體材料。
  6. 如申請專利範圍第1項之半導體裝置，其中該基板為結晶基板，且該半導體本體與該結晶基板連續。
  7. 如申請專利範圍第1項之半導體裝置，其中介電層被設置於該半導體本體與該基板間，且該半導體本體與該基板不連續。
  8. 如申請專利範圍第1項之半導體裝置，其中該通道區具有大約範圍在30-50奈米的高度及大約範圍在10-30奈米的寬度，該通道區的高度比該源極與汲極區在該等側壁間隔物下方的該部分之高度少大約1-2奈米，且該通道區的寬度比該源極與汲極區在該等側壁間隔物下方的該部分之寬度少大約2-4奈米。
  9. 如申請專利範圍第1項之半導體裝置，其中該源極與汲極區在該等側壁間隔物下方的該部分之高度比該通道區的高度大大約1-7%，且該源極與汲極區在該等側壁間隔物下方的該部分之寬度比該通道區的寬度大大約6-40%。
  10. 如申請專利範圍第1項之半導體裝置，其中該通道區係由步階特性圖案耦接至該源極與汲極區在該等側壁間隔物下方的該部分。
  11. 如申請專利範圍第1項之半導體裝置，其中該通道區係由漸變特性圖案(graded feature)耦接至該源極與汲極區在該等側壁間隔物下方的該部分。
  12. 如申請專利範圍第11項之半導體裝置，其中該漸變特性圖案包含刻面(facet)。
  13. 如申請專利範圍第11項之半導體裝置，其中該漸變特性圖案包含圓角。
  14. 如申請專利範圍第11項之半導體裝置，其中該漸變特性圖案在該半導體裝置的操作期間降低重疊電容及展佈電阻。
  15. 如申請專利範圍第1項之半導體裝置，其中該半導體裝置被設置於相同基板之上作為具有通道區的第二半導體裝置，且其中該第二半導體裝置的通道區的最窄寬度大於該半導體裝置的通道區的最窄寬度。
  16. 一種製造半導體裝置的方法，該方法包含：形成半導體本體於基板之上；形成閘極電極堆疊於該半導體本體的一部分之上以界定該閘極電極堆疊下方的半導體本體中的通道區以及該閘極電極堆疊的兩側上的半導體本體中的源極與汲極區；及形成側壁間隔物相鄰於該閘極電極堆疊且在僅該源極與汲極區的一部分之上，其中該源極與汲極區在該等側壁間隔物下方的該部分具有比該半導體本體的通道區之高度與寬度更大的高度與寬度。
  17. 如申請專利範圍第16項之方法，其中形成該閘極電極堆疊包含形成犧牲閘極電極堆疊、移除該犧牲閘極電極堆疊、及形成永久閘極電極堆疊，且其中形成該通道區包含薄化該半導體本體在移除該犧牲閘極電極堆疊之後且在形成該永久閘極電極堆疊之前所暴露的部分。
  18. 如申請專利範圍第16項之方法，其中形成該閘 極電極堆疊包含形成犧牲閘極電極堆疊、移除該犧牲閘極電極堆疊、及形成永久閘極電極堆疊，且其中形成該源極與汲極區包含擴展該半導體本體在移除該犧牲閘極電極堆疊以前所暴露的部分。
  19. 一種製造半導體裝置的方法，該方法包含：形成硬遮罩圖案於基板之上，該硬遮罩圖案包含第一區的多數鰭片形成特性圖案，各者具第一寬度，且該硬遮罩圖案也包含第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度；及，隨後，形成及圖案化抗蝕層以覆蓋該第二區及暴露該第一區；及，隨後，蝕刻該第一區的多數鰭片形成特性圖案以形成多數薄化鰭片形成特性圖案，各者具小於該第二寬度的第三寬度；及，隨後，移除該抗蝕層；及，隨後，轉移該硬遮罩圖案至該基板以形成第一區的多數鰭片，各者具該第三寬度，且形成第二區的多數鰭片，各者具該第二寬度；及，隨後，從該等第一及第二區的多數鰭片形成半導體裝置。
  20. 如申請專利範圍第19項之方法，其中該基板為單晶矽基板，且其中轉移該硬遮罩圖案至該基板包含形成單晶矽鰭片。
  21. 一種製造半導體裝置的方法，該方法包含：形成硬遮罩圖案於基板之上，該硬遮罩圖案包含第一 區的多數鰭片形成特性圖案，各者具第一寬度，且該硬遮罩圖案也包含第二區的多數鰭片形成特性圖案，各者具大約等於該第一寬度的第二寬度；及，隨後，轉移該硬遮罩圖案至該基板以形成第一區的多數鰭片，各者具該第一寬度，且形成第二區的多數鰭片，各者具該第二寬度；及，隨後，形成及圖案化抗蝕層以覆蓋該第二區的多數鰭片及暴露該第一區的多數鰭片；及，隨後，蝕刻該第一區的多數鰭片以形成多數薄化鰭片，各者具小於該第二寬度的第三寬度；及，隨後，移除該抗蝕層；及，隨後，從該等第一及第二區的多數鰭片形成半導體裝置。
  22. 如申請專利範圍第21項之方法，其中該基板為單晶矽基板，且其中轉移該硬遮罩圖案至該基板包含形成單晶矽鰭片。
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