CN113345952A - 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 - Google Patents

具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法 Download PDF

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CN113345952A
CN113345952A CN202110410997.8A CN202110410997A CN113345952A CN 113345952 A CN113345952 A CN 113345952A CN 202110410997 A CN202110410997 A CN 202110410997A CN 113345952 A CN113345952 A CN 113345952A
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source
drain regions
width
semiconductor body
channel region
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B·塞尔
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Intel Corp
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Intel Corp
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Abstract

本发明描述了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。例如，半导体器件包括设置于衬底之上的半导体主体。栅极电极堆叠体设置于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。

Description

具有颈状半导体主体的半导体器件以及形成不同宽度的半导 体主体的方法
本申请为分案申请，其原申请是于2014年8月21日(国际申请日为2011年12月22日)向中国专利局提交的专利申请，申请号为201180076423.6，发明名称为“具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法”。
技术领域
本发明的实施例是在半导体器件和加工的领域中，具体而言，是在具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法的领域中。
背景技术
在过去几十年中，集成电路中的特征的缩放已经成为不断成长的半导体产业背后的驱动力。缩放到越来越小的特征使得能够增大在半导体芯片的有限的基板面上的功能单元的密度。例如，缩小晶体管尺寸允许芯片上包含的存储器设备或逻辑设备的数量增加，从而制造出具有更大的容量的产品。然而，对于越来越大容量的追求并不是没有问题。对每个器件的性能进行最优化的必要性变得越发显著。
在集成电路器件的制造中，诸如fin-FET和三栅极晶体管之类的多栅极晶体管已经随着器件尺寸不断缩小而变得更普遍。在常规工艺中，通常在体硅衬底或绝缘体上硅衬底上制造fin-FET和三栅极晶体管。在一些实例中，由于体硅衬底的成本较低并且因为它们能够实现较不复杂的fin-FET和三栅极制造工艺，所以体硅衬底是优选的。在其它实例中，由于fin-FET和三栅极晶体管的改进的短沟道特性，因而绝缘体上硅衬底是优选的。
然而，对多栅极晶体管进行缩放并不是还没有成果。随着微电子电路的这些基本构建块的尺寸减小，并且随着在给定区域中制造的基本构建块的绝对数目增加，在这些器件的运行期间，对外部电阻(Rext)的限制已经变得至关重要。已经尝试了许多不同的技术来改进晶体管的Rext，所述技术包括改进的接触金属、增大的掺杂剂活性以及降低的半导体与接触金属之间的势垒。然而，在减小Rext的领域中仍然需要显著改进。
发明内容
本发明的实施例包括具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。
在实施例中，半导体器件包括设置于衬底上方的半导体主体。栅极电极堆叠体设置于半导体主体的一部分上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成半导体主体。栅极电极堆叠体形成于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区、以及半导体主体中的位于栅极电极堆叠体的两侧上的源极区和漏极区。侧壁间隔体形成于临界栅极电极堆叠体处，并且形成于源极区和漏极区的仅一部分之上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖第二区并暴露第一区。随后，蚀刻第一区的鳍状物形成特征，以形成减薄的鳍状物形成特征，其中每个特征具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第三宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，从第一和第二区的鳍状物形成半导体器件。
在另一个实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第一宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖具有鳍状物的第二区并暴露具有鳍状物的第一区。随后，蚀刻第一区中的鳍状物，以形成减薄的鳍状物，其中每个减薄的鳍状物具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，从第一和第二区的鳍状物形成半导体器件。
附图说明
图1A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。
图1B示出根据本发明的实施例的图1A的半导体器件的沿着a-a’轴截取的截面视图。
图1C示出根据本发明的实施例的图1A的半导体器件的沿着b-b’轴截取的截面视图。
图2A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。
图2B示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。
图2C示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。
图3示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程。
图4示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程。
图5A包括根据本发明的实施例的驱动电流增益(如％Idsat增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线。
图5B包括根据本发明的实施例的驱动电流增益(如％Idlin增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线。
图6示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程。
图7示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程。
图8示出根据本发明的一种实施方式的计算设备。
具体实施方式
描述了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。在下文的描述中，为提供对本发明的实施例的深入理解而阐述了大量的具体细节，例如具体的集成和材料方案(regime)。对于本领域技术人员来说显而易见的是，可以在没有这些具体细节的情况下实践本发明的实施例。在其它实例中，为了不非必要地使本发明的实施例难以理解，没有具体描述诸如集成电路设计布局之类的公知的特征。此外，应该理解的是，附图中所示的各种实施例是说明性的表示，并且未必是按比例绘制的。
本发明的一个或多个实施例针对具有(1)与间隔体下方的鳍状物宽度相比的有源沟道区中的不同的鳍状物宽度，(2)在同一管芯上的不同有源沟道区中至少具有两个不同的鳍状物宽度的集成电路，(3)用于在实际鳍状物蚀刻之前限定两个不同的鳍状物宽度的构图工艺，(4)用于在牺牲虚设栅极去除工艺之后限定两个不同的鳍状物宽度的构图工艺，或它们的组合的半导体器件。一个或多个实施例针对改进诸如晶体管之类的器件的驱动电流，并且要建立具有低空载功率和高激活性能的电路。
FinFET中的鳍状物的宽度影响阈值电压(Vt)和器件的外部电阻。对于高性能器件而言，可能有益的是包含具有较高Vt和较低电阻的相对较宽的鳍状物。对于低功率器件而言，情况却正好相反。目前，必须针对这些器件的其中之一来优化所述工艺。可能有益的是使这两种器件都具有最佳性能，以优化产品功率性能。例如，利用引起较高的Vt和较高的结泄漏的附加的适当掺杂产生低功率器件，其尤其在低电源电压下降低了驱动电流。替代地，针对导致高性能器件的驱动电流降低的低功率器件来优化所述工艺。本发明的实施例可以通过在同一管芯上提供两个不同的器件或通过具有低Vt和低外部电阻二者的器件，使得能够同时实现高性能和低功率器件的优化。
在第一方面，提供了具有颈状半导体主体的半导体器件和形成具有颈状半导体主体的半导体器件的方法。这种晶体管结构在沟道中和间隔体下方的鳍状物区中具有不同的鳍状物宽度。随着鳍状物CD的缩放，颈状鳍状物可以改善短沟道效应改进与外部电阻之间的权衡，从而改善了最佳器件的驱动电流。
在示例中，图1A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。图1B示出根据本发明的实施例的图1A的半导体器件的沿着a-a’轴截取的截面视图。图1C示出根据本发明的实施例的图1A的半导体器件的沿着b-b’轴截取的截面视图。
参考图1A-1C，半导体器件100包括设置于衬底102上方的半导体主体104。栅极电极堆叠体106设置于半导体主体104的一部分上，以限定半导体主体104中的位于栅极电极堆叠体106下方的沟道区108。在栅极电极堆叠体106的两侧上的半导体主体104中限定了源极区和漏极区110。侧壁间隔体112设置于邻近栅极电极堆叠体106处，并且设置于源极区和漏极区110的仅一部分上。
参考图1B和1C，相较于半导体主体104的沟道区108的高度(H1)和宽度(W1)，源极区和漏极区110的位于侧壁间隔体112下方的部分具有更大的高度(H2)和宽度(W2)。高度H1和H2被限定为隔离层114上方的半导体主体104的相应的部分的高度，如图1B和1C中所描绘的那样。
参考图1A，在实施例中，相较于源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)和宽度(W2)，源极区和漏极区110的不在侧壁间隔体112下方的部分具有更大的高度和宽度(W3)，例如，W3>W2。替代地，在另一个实施例中，源极区和漏极区110的不在侧壁间隔体112下方的部分的高度和宽度(W3)与源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)和宽度(W2)大致相同，例如，W3＝W2。
在实施例中，源极区和漏极区110的至少一部分是源极区和漏极区110的嵌入的部分。也就是，在形成源极区和漏极区110时，去除最初的半导体主体104的一部分，并且例如通过外延生长来将其替换为半导体主体104的新的部分。例如，在一个这种实施例中，源极区和漏极区110的嵌入的部分由与沟道区108的半导体材料不同的半导体材料构成。在一个实施例中，嵌入的部分并不包括源极区和漏极区110的位于侧壁间隔体112下方的部分。在另一个实施例中，嵌入的部分包括源极区和漏极区110的位于侧壁间隔体112下方的部分中的至少一部分并且可能是全部。
在实施例中，参考图1B和1C，衬底102是晶体衬底，并且半导体主体104(例如，图1B中的沟道区108和图1C中的源极区和漏极区110)与晶体衬底102连续。也就是，从体衬底形成半导体主体104。在替代的实施例(未示出)中，电介质层设置于半导体主体与衬底之间，并且半导体主体与衬底不连续，例如，如绝缘体上硅(SOI)衬底会出现的情况一样。
在实施例中，沟道区108的高度(H1)近似在30-50纳米的范围中，并且宽度(W1)近似在10-30纳米的范围中。在该实施例中，沟道区108的高度(H1)比源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)小大约1-2纳米。同样，沟道区108的宽度(W1)比源极区和漏极区110的位于侧壁间隔体112下方的部分的宽度(W2)小大约2-4纳米。在实施例中，源极区和漏极区110的位于侧壁间隔体112下方的部分的高度(H2)比沟道区108的高度(H1)大大约1-7％。在该实施例中，源极区和漏极区110的位于侧壁间隔体112下方的部分的宽度(W2)比沟道区108的宽度(W1)大大约6-40％。
以下描述了图1A-1C中的半导体器件100的可能的实施例。在第一个示例中，图2A示出根据本发明的实施例的具有颈状半导体主体的半导体器件的平面视图。参考图2A，沟道区108通过台阶特征120耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
在第二个示例中，图2B示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。参考图2B，沟道区108通过刻面(facet)特征130耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
在第三个示例中，图2C示出根据本发明的另一个实施例的具有颈状半导体主体的另一个半导体器件的平面视图。参考图2C，沟道区108通过圆化拐角特征140耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。栅极电极堆叠体106被描绘成虚线，从而为下层的沟道区108提供透明度。同样，通过围绕源极区和漏极区110的长虚线来描绘包含较大尺寸的不在间隔体112下方的源极区和漏极区110的部分的可选方案。
因此，再次参考图2B和2C，在实施例中，沟道区108通过缓变(graded)特征(例如，120或140)耦合到源极区和漏极区110的位于侧壁间隔体112下方的部分。在实施例中，缓变特征在半导体器件110的运行期间减小了重叠电容和扩散电阻。
在实施例中，如以下结合工艺流程600和700所更详细地描述的，半导体器件100设置于与具有沟道区的第二半导体器件相同的衬底102上方。在该实施例中，第二半导体器件的沟道区的最窄宽度大于半导体器件100的沟道区108的最窄宽度(例如，W1)。
半导体器件100可以是包含栅极、沟道区和源极/漏极区对的任何半导体器件。在实施例中，半导体器件100是例如但不限于MOS-FET或微机电系统(MEMS)的半导体器件。在一个实施例中，半导体器件100是三维的MOS-FET，并且是隔离的器件或者是多个嵌套的器件中的一个器件。会理解，对于典型的集成电路来说，可以在单个衬底上制造N沟道和P沟道晶体管二者，以形成CMOS集成电路。
衬底102可以由能够承受制造工艺并且电荷能够在其中迁移的半导体材料构成，并且因此半导体主体104也可以由这种半导体材料构成。在实施例中，衬底102是体衬底，并且半导体主体104与体衬底102连续。在实施例中，衬底102由晶体硅、硅/锗或掺杂有电荷载流子的锗层构成，所述电荷载流子例如但不限于磷、砷、硼或它们的组合。在一个实施例中，衬底102中的硅原子的浓度大于97％，或者，替代地，掺杂剂原子的浓度小于1％。在另一个实施例中，衬底102由生长在不同的晶体衬底顶上的外延层构成，例如，生长在硼掺杂的体硅单晶衬底顶上的硅外延层。衬底102还可以包括设置于体晶体衬底与外延层之间的绝缘层，以形成例如绝缘体上硅衬底。在所述示例中，半导体主体104可以是隔离的半导体主体。在实施例中，绝缘层由例如但不限于二氧化硅、氮化硅、氮氧化硅或高k电介质层的材料构成。替代地，衬底102可以由Ⅲ-Ⅴ族材料构成。在实施例中，衬底102由例如但不限于氮化镓、磷化镓、砷化镓、磷化铟、锑化铟、砷化铟镓、砷化铝镓、磷化铟镓、或它们的组合的Ⅲ-Ⅴ族材料构成。半导体主体104可以由多种半导体材料构成，所述多种半导体材料中的每种半导体材料可以包括附加的掺杂原子。在一个实施例中，衬底102由晶体硅构成，并且电荷载流子掺杂剂杂质原子是例如但不限于硼、砷、铟或磷的原子。在另一个实施例中，衬底102由Ⅲ-Ⅴ族材料构成，并且电荷载流子掺杂剂杂质原子是例如但不限于碳、硅、锗、氧、硫、硒或碲的原子。在另一个实施例中，半导体主体104是未掺杂的或仅轻度掺杂的。另外，在一个实施例中，可以在半导体器件100的制造中消除常规器件制造中通常使用的晕轮(halo)掺杂。应该理解的是，在实施例中，半导体主体104的材料与衬底102的材料不同。
在另一个实施例中，半导体器件100是例如但不限于fin-FET或三栅极器件的非平面器件。在这种实施例中，半导体主体104由三维主体构成，或者从三维主体形成。在一个这种实施例中，栅极电极堆叠体106至少包围三维主体的顶表面和一对侧壁。在另一个实施例中，例如在纳米线器件中，将半导体主体104制造为分立的三维主体。在一个这种实施例中，栅极电极堆叠体100完全包围半导体主体104的一部分。
栅极电极堆叠体106可以包括栅极电极和下层的栅极电介质层。在实施例中，栅极电极堆叠体106的栅极电极由金属栅极构成，并且栅极电介质层由高K材料构成。例如，在一个实施例中，栅极电介质层由例如但不限于氧化铪、氮氧化铪、硅酸铪、氧化镧、氧化锆、硅酸锆、氧化钽、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、铅钽钪氧化物、铌酸铅锌、或它们的组合之类的材料构成。此外，栅极电介质层的一部分可以包括由半导体主体104的顶部几层形成的自然氧化物层。在实施例中，栅极电介质层由顶部高K部分和由半导体材料的氧化物构成的下层部分构成。在一个实施例中，栅极电介质层由氧化铪的顶部部分和二氧化硅或氮氧化硅的底部部分构成。
在一个实施例中，栅极电极由例如但不限于金属氮化物、金属碳化物、金属硅化物、金属铝化物、铪、锆、钛、钽、铝、钌、钯、铂、钴、镍、或导电金属氧化物之类的金属层构成。在具体实施例中，栅极电极由形成于金属功函数设定层上方的非功函数设定填充材料构成。在实施例中，栅极电极由P型材料构成。在另一个实施例中，栅极电极由N型材料构成。在另一个实施例中，栅极电极由中间带隙材料构成。在特定的这种实施例中，相应的沟道区是未掺杂的或仅轻度掺杂的。
在实施例中，侧壁间隔体112由例如但不限于二氧化硅、碳化硅、氮氧化硅或氮化硅的绝缘电介质材料构成。类似地，电介质层114可以由例如但不限于二氧化硅、碳化硅、氮氧化硅或氮化硅的绝缘电介质材料构成。
在本发明的实施例的精神和范围内还考虑了形成诸如以上所描述的那些器件之类的器件的方法。在第一个示例中，图3示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程300。
参考工艺流程300的部分A，形成厚鳍状物302，对牺牲栅极304进行构图，通过均厚沉积和随后的蚀刻来形成栅极间隔体306，并且形成源极-漏极区308。另外，可以沉积层间电介质膜310并对其进行抛光，以暴露牺牲栅极304。参考工艺流程300的部分B，去除牺牲栅极304，并且蚀刻厚鳍状物302，以形成具有减小的厚度(例如，减小大约1-5纳米范围内的量)的减薄的鳍状物312。参考工艺流程300的部分C，在减薄的鳍状物312之上形成永久的栅极堆叠体320。例如，可以形成高k栅极电介质层和金属栅极电极。在实施例中，减薄的鳍状物312提供改进的短沟道效应，而源极区和漏极区308的位于间隔体306下方的较宽的部分有助于减小外部电阻。
在实施例中，牺牲栅极304由适合于在替换栅极操作时去除的材料构成。在一个实施例中，牺牲栅极304由多晶硅、非晶硅、二氧化硅、氮化硅、或它们的组合构成。在另一个实施例中，在牺牲栅极304上方形成诸如二氧化硅或氮化硅层之类的保护性覆盖层(未示出)。在实施例中，包括了下层的虚设栅极电介质层(也未示出)。在实施例中，牺牲栅极304包括侧壁间隔体306，侧壁间隔体306可由适合于最终将永久栅极结构与邻近的导电接触部电隔离的材料构成。例如，在一个实施例中，间隔体306由例如但不限于二氧化硅、氮氧化硅、氮化硅、或碳掺杂的氮化硅的电介质材料构成。
在实施例中，通过干法蚀刻或湿法蚀刻工艺来去除牺牲栅极304。在一个实施例中，牺牲栅极304由多晶硅或非晶硅构成，并且利用使用SF6的干法蚀刻工艺来去除牺牲栅极304。在另一个实施例中，牺牲栅极304由多晶硅或非晶硅构成，并且利用使用NH4OH或四甲胺羟化物的水溶液的湿法蚀刻工艺来去除牺牲栅极304。在一个实施例中，牺牲栅极304由氮化硅构成，并且利用使用磷酸水溶液的湿法蚀刻来去除牺牲栅极304。
在对存在的其它半导体特征没有不利影响的情况下，可以通过将鳍状物302的一部分去除的任何适合的技术(例如通过利用干法蚀刻或湿法蚀刻工艺)来将鳍状物302减薄，以形成312。在一个实施例中，可以通过利用使用NF3、HBr、SF6/Cl或Cl2的干法等离子体蚀刻来将鳍状物302减薄，以形成312。
在第二个示例中，图4示出根据本发明的实施例的制造具有颈状半导体主体的半导体器件的方法中的工艺流程400。参考工艺流程400的部分A，形成薄鳍状物412，对牺牲栅极404进行构图，并且形成薄源极-漏极区408。参考工艺流程400的部分B，通过均厚沉积和随后的蚀刻来形成栅极间隔体406，并且例如通过外延生长来形成厚源极区和漏极区418。此外，可以沉积层间电介质膜410并对其进行抛光，以暴露牺牲栅极404。然后去除牺牲栅极404，如部分B中所描绘的那样。参考工艺流程400的部分C，在薄鳍状物412上形成永久的栅极堆叠体420。例如，可以形成高k栅极电介质层和金属栅极电极。在实施例中，薄鳍状物412提供改进的短沟道效应，而源极区和漏极区408/418的位于间隔体406下方的较宽的部分有助于减小外部电阻。可以如以上结合工艺流程300所描述的那样来执行牺牲栅极的形成和替换。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成半导体主体。栅极电极堆叠体形成于半导体主体的一部分之上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区、以及半导体主体中的位于栅极电极堆叠体的两侧上的源极区和漏极区。侧壁间隔体形成于邻近栅极电极堆叠体处并且形成于源极区和漏极区的仅一部分之上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。
在一个这种实施例中，形成栅极电极堆叠体包括：形成牺牲栅极电极堆叠体、去除牺牲栅极电极堆叠体、以及形成永久的栅极电极堆叠体。在该实施例中，形成沟道区包括：在去除牺牲栅极电极堆叠体之后并且在形成永久的栅极电极堆叠体之前，将暴露的半导体主体的一部分减薄，例如，如结合工艺流程300所描述的那样。在另一个这种实施例中，形成栅极电极堆叠体包括：形成牺牲栅极电极堆叠体、去除牺牲栅极电极堆叠体、以及形成永久的栅极电极堆叠体。在该实施例中，形成源极区和漏极区包括：在去除牺牲栅极电极堆叠体之前扩展暴露的半导体主体的一部分，例如，如结合工艺流程400所描述的那样。
图5A包括根据本发明的实施例的驱动电流增益(如％Idsat增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线500A。图5B包括根据本发明的实施例的驱动电流增益(如％Idlin增益)作为具有颈状半导体主体的半导体器件的硅沟道区厚度(以微米表示)的函数与作为没有颈状半导体主体的半导体器件的硅沟道区厚度的函数进行对比的曲线500B。参考曲线500A和500B，将根据预先的硅宽度(Wsi)限定形成的鳍状物与具有在替换栅极操作期间限定的减薄的硅宽度(Wsi)的鳍状物(例如，如结合工艺流程300所描述的那样)进行比较。曲线揭示了减薄的鳍状物器件的预期驱动电流增益。
在第二方面，提供了形成不同宽度的半导体主体的方法。这种工艺可以使得能够在同一管芯内形成不同的鳍状物宽度。因此，可以在同一管芯上实现使用用于高性能应用的较宽的鳍状物宽度器件和用于低功率(低待机泄漏)应用的较低的鳍状物宽度器件。
在第一个示例中，图6示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程600。
参考工艺流程600的部分A，衬底602上方(例如，晶体硅衬底上方)的用于最终鳍状物形成的硬掩模603A/603B的形成包括硬掩模层的沉积和构图。已构图的硬掩模层603A/603B包括用于最终薄鳍状物形成的区域604和用于最终厚鳍状物形成的区域606。参考工艺流程600的部分B，利用抗蚀剂层608来遮住将维持较宽的宽度的鳍状物(例如，在区域606中)，并且蚀刻暴露的硬掩模603A来减小线的宽度。参考工艺流程600的部分C，然后去除抗蚀剂层608(例如包括灰化工艺)，并且将新的硬掩模图案603A/603B转移到衬底602中，以形成鳍状物610A和610B。替代地，在实施例中，可以在鳍状物被蚀刻到衬底中之后、并且在牺牲栅极的构图之前执行附加的光刻鳍状物减薄。在实施例中，由间隔体构图流程首先形成硬掩模区603A/603B，所述间隔体构图流程可以用于有效地使被用于形成特征的光刻工艺的间距加倍。工艺流程600维持了间隔体构图流程的间距。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，形成抗蚀剂层并对其进行构图，以覆盖第二区并暴露第一区。随后，蚀刻第一区的鳍状物形成特征，以形成减薄的鳍状物形成特征，其中每个特征具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第三宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，利用第一和第二区的鳍状物形成半导体器件。在一个这种实施例中，衬底是单晶硅衬底，并且将硬掩模图案转移到衬底包括形成单晶硅鳍状物。
在第二个示例中，图7示出根据本发明的实施例的制造具有不同宽度的半导体主体的半导体器件的方法中的工艺流程700。
参考工艺流程700的部分A，衬底702上方(例如，晶体硅衬底上方)的用于鳍状物形成的硬掩模703A/703B的形成包括硬掩模层的沉积和构图。已构图的硬掩模层703A/703B包括用于薄鳍状物形成的区域704和用于厚鳍状物形成的区域706。然后将硬掩模图案703A/703B转移到衬底702中，以形成对应的鳍状物。然后可以执行牺牲栅极构图以及延伸源极和漏极的形成。同样，可以沉积层间电介质材料并对其进行抛光，以露出牺牲栅极。然后去除牺牲栅极。参考工艺流程700的部分B，利用抗蚀剂层708来遮住将保持较宽的宽度的鳍状物710B(例如，在区域706中)。鳍状物减薄蚀刻用于减小鳍状物710A的鳍状物宽度。参考工艺流程700的部分C，去除抗蚀剂层708(例如包括灰化工艺)，并且可以利用较薄的鳍状物710A和较宽的鳍状物710B来执行标准器件制造技术。在实施例中，由间隔体构图流程首先形成硬掩模区703A/703B，所述间隔体构图流程可以用于有效地使被用于形成特征的光刻工艺的间距加倍。工艺流程700维持了间隔体构图流程的间距。
因此，在实施例中，制造半导体器件的方法包括在衬底上方形成硬掩模图案。硬掩模图案包括具有鳍状物形成特征的第一区，其中每个特征具有第一宽度。硬掩模图案还包括具有鳍状物形成特征的第二区，其中每个特征具有近似等于第一宽度的第二宽度。随后，将硬掩模图案转移到衬底，以形成具有鳍状物的第一区，其中每个鳍状物具有第一宽度；并且形成具有鳍状物的第二区，其中每个鳍状物具有第二宽度。随后，形成抗蚀剂层并对其进行蚀刻，以覆盖具有鳍状物的第二区并暴露具有鳍状物的第一区。随后，蚀刻第一区的鳍状物，以形成减薄的鳍状物，其中每个减薄的鳍状物具有小于第二宽度的第三宽度。随后，去除抗蚀剂层。随后，利用第一和第二区的鳍状物形成半导体器件。在一个这种实施例中，衬底是单晶硅衬底，并且将硬掩模图案转移到衬底包括形成单晶硅鳍状物。
本文中所描述的工艺可以用于制造一个或多个半导体器件。半导体器件可以是晶体管或类似器件。例如，在实施例中，半导体器件是用于逻辑或存储器的金属氧化物半导体(MOS)晶体管，或是双极晶体管。同样，在实施例中，半导体器件具有三维的架构，例如三栅极器件、独立访问的双栅极器件、或FIN-FET。
图8示出根据本发明的一种实施方式的计算设备800。计算设备800容纳板802。板802可以包括多个部件，包括但不限于处理器804和至少一个通信芯片806。处理器804与板802物理地和电气地耦合。在一些实施方式中，至少一个通信芯片806也与板802物理地和电气地耦合。在其它实施方式中，通信芯片806是处理器804的一部分。
取决于其应用，计算设备800可以包括其它部件，所述其它部件可以或可以不与板802物理地和电气地耦合。这些其它部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘，等等)。
通信芯片806使得能够进行用于到和来自计算设备800的数据的传送的无线通信。术语“无线”和其衍生词可以用于描述可以通过使用调制的电磁辐射、经由非固态介质传送数据的电路、设备、系统、方法、技术、通信信道，等等。所述术语并不暗示相关联的设备不包含任何线路，尽管在一些实施例中它们可能不包含。通信芯片806可以实施多种无线标准或协议中的任何一种，所述多种无线标准或协议包括但不限于Wi-Fi(IEEE802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、及它们的衍生物，以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备800可以包括多个通信芯片806。例如，第一通信芯片806可以专用于诸如Wi-Fi和蓝牙的较短距离的无线通信，并且第二通信芯片806可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它的较远距离的无线通信。
计算设备800的处理器804包括封装在处理器804内的集成电路管芯。在本发明的一些实施方式中，处理器的集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。术语“处理器”可以指代处理来自寄存器和/存储器的电子数据以将该电子数据转换成可以在寄存器和/或存储器中存储的其它电子数据的任何器件或器件的部分。
通信芯片806还包括封装在通信芯片806内的集成电路管芯。根据本发明的另一种实施方式，通信芯片的集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。
在进一步的实施方式中，计算设备800内容纳的另一个部件可以包含集成电路管芯，该集成电路管芯包括一个或多个器件，例如根据本发明的实施方式所制造的MOS-FET晶体管。
在各种实施方式中，计算设备800可以是膝上型电脑、上网本、笔记本电脑、超极本、智能手机、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或数字录像机。在进一步的实施方式中，计算设备800可以是处理数据的任何其它电子设备。
因此，已经公开了具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法。在实施例中，半导体器件包括设置于衬底上方的半导体主体。栅极电极堆叠体设置于半导体主体的一部分上，以限定半导体主体中的位于栅极电极堆叠体下方的沟道区。在栅极电极堆叠体的两侧上的半导体主体中限定了源极区和漏极区。侧壁间隔体设置于邻近栅极电极堆叠体处，并且设置于源极区和漏极区的仅一部分上。相较于半导体主体的沟道区的高度和宽度，源极区和漏极区的位于侧壁间隔体下方的部分具有更大的高度和宽度。在一个实施例中，半导体器件设置于与具有沟道区的第二半导体器件相同的衬底上方，并且第二半导体器件的沟道区的最窄的宽度大于半导体器件的沟道区的最窄的宽度。

Claims (24)

1.一种半导体器件，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有宽度，在所述宽度处所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分与所述沟道区相接，所述宽度比所述半导体主体的所述沟道区的宽度更大。
2.如权利要求1所述的半导体器件，其中所述源极区和所述漏极区的不位于所述侧壁间隔体下方的部分具有比所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分的所述宽度更大的宽度。
3.如权利要求1所述的半导体器件，其中所述源极区和所述漏极区的不位于所述侧壁间隔体下方的部分具有与所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分的所述宽度大体上相同的宽度。
4.如权利要求1所述的半导体器件，其中所述源极区和所述漏极区的至少一部分是所述源极区和所述漏极区的外延部分。
5.如权利要求4所述的半导体器件，其中所述源极区和所述漏极区的所述外延部分包括与所述沟道区不同的半导体材料。
6.如权利要求1所述的半导体器件，其中所述衬底是晶体衬底，并且所述半导体主体与所述晶体衬底连续。
7.如权利要求1所述的半导体器件，其中电介质层设置于所述半导体主体与所述衬底之间，并且所述半导体主体与所述衬底不连续。
8.如权利要求1所述的半导体器件，其中所述沟道区具有近似在10-30纳米的范围中的宽度，并且所述沟道区的所述宽度比所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分的所述宽度小大约2-4纳米。
9.如权利要求1所述的半导体器件，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分的所述宽度比所述沟道区的所述宽度大大约6-40%。
10.如权利要求1所述的半导体器件，其中所述沟道区通过台阶特征耦合到所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分。
11.如权利要求1所述的半导体器件，其中所述沟道区通过缓变特征耦合到所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分。
12.如权利要求11所述的半导体器件，其中所述缓变特征包括刻面。
13.如权利要求11所述的半导体器件，其中所述缓变特征包括圆化拐角。
14.如权利要求11所述的半导体器件，其中所述缓变特征在所述半导体器件的运行期间减小了重叠电容和扩散电阻。
15.如权利要求1所述的半导体器件，其中所述半导体器件设置于与具有沟道区的第二半导体器件相同的衬底上方，并且其中所述第二半导体器件的所述沟道区的最窄宽度大于所述半导体器件的所述沟道区的最窄宽度。
16.一种计算设备，包括：
板；以及
耦合到所述板的器件，所述器件包括集成电路结构，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有宽度，在所述宽度处所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分与所述沟道区相接，所述宽度比所述半导体主体的所述沟道区的宽度更大。
17.如权利要求16所述的计算设备，进一步包括：
耦合到所述板的存储器。
18.如权利要求16所述的计算设备，进一步包括：
耦合到所述板的通信芯片。
19.如权利要求16所述的计算设备，其中所述器件是封装集成电路管芯。
20.如权利要求16所述的计算设备，其中所述计算设备选自由以下项组成的组中：移动电话、膝上型电脑、台式计算机、服务器和机顶盒。
21.一种半导体器件，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有比所述半导体主体的所述沟道区的宽度更大的宽度，其中所述沟道区具有近似在10-30纳米的范围中的宽度，并且所述沟道区的所述宽度比所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分的所述宽度小大约2-4纳米。
22.一种半导体器件，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有比所述半导体主体的所述沟道区的宽度更大的宽度，其中所述沟道区通过台阶特征耦合到所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分。
23.一种半导体器件，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有比所述半导体主体的所述沟道区的宽度更大的宽度，其中所述沟道区通过缓变特征耦合到所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分，并且其中所述缓变特征包括刻面。
24.一种半导体器件，包括：
设置在衬底上的半导体主体；
设置在所述半导体主体的一部分上方的栅极电极堆叠体，用于限定所述半导体主体中的位于所述栅极电极堆叠体下方的沟道区和在所述栅极电极堆叠体的任一侧上在所述半导体主体中的源极区和漏极区；以及
邻近所述栅极电极堆叠体设置的并且在所述源极区和所述漏极区的仅一部分上方的侧壁间隔体，其中所述源极区和所述漏极区的位于所述侧壁间隔体下方的所述部分具有比所述半导体主体的所述沟道区的宽度更大的宽度，其中所述半导体器件设置于与具有沟道区的第二半导体器件相同的衬底上方，并且其中所述第二半导体器件的所述沟道区的最窄宽度大于所述半导体器件的所述沟道区的最窄宽度。
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CN113540080A (zh) 2021-10-22
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US20130313610A1 (en) 2013-11-28
US20200235241A1 (en) 2020-07-23
TWI565077B (zh) 2017-01-01
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TW201826543A (zh) 2018-07-16
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US8941214B2 (en) 2015-01-27
TW201342603A (zh) 2013-10-16
DE112011105996T5 (de) 2014-09-04
US10319843B2 (en) 2019-06-11
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US20230013575A1 (en) 2023-01-19
US10651310B2 (en) 2020-05-12
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US12015087B2 (en) 2024-06-18
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US20150147863A1 (en) 2015-05-28
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US20170012132A1 (en) 2017-01-12
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US11164975B2 (en) 2021-11-02
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