CN111900088A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN111900088A CN111900088A CN201910368379.4A CN201910368379A CN111900088A CN 111900088 A CN111900088 A CN 111900088A CN 201910368379 A CN201910368379 A CN 201910368379A CN 111900088 A CN111900088 A CN 111900088A
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Abstract
本发明一种半导体器件及其形成方法,包括步骤:提供衬底,所述衬底上形成有若干分隔排列的鳍部;在所述衬底上形成横跨所述鳍部的伪栅结构;在所述衬底上形成、所述伪栅结构的侧壁上形成第一层间介电层,且所述第一层间介电层的顶部低于所述伪栅结构的顶部;定义切断开口图形;沿所述切断开口图形,刻蚀所述伪栅结构,直至暴露出所述衬底,形成切断开口;在所述第一层间介电层上形成第二层间介电层,且所述第二层间介电层填充满所述切断开口,所述第二层间介电层顶部与所述伪栅结构顶部齐平;本发明使得所形成的半导体器件性能稳定。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展,半导体器件朝着更高的元件密度,以及更高的集成度的方向发展。器件作为最基本的半导体器件,目前正被广泛应用,传统的平面器件对沟道电流的控制能力变弱,产生短沟道效应而导致漏电流,最终影响半导体器件的电学性能。
为了克服器件的短沟道效应,抑制漏电流,现有技术提出了鳍式场效应晶体管(Fin FET),鳍式场效应晶体管是一种常见的多栅器件,鳍式场效应晶体管的结构包括:位于半导体衬底表面的鳍部和隔离结构,所述隔离结构覆盖部分所述鳍部的侧壁,且隔离结构表面低于鳍部顶部;位于隔离结构表面,以及鳍部的顶部和侧壁表面的栅极结构;位于所述栅极结构两侧的鳍部内的源区和漏区。
然而,随着半导体器件的尺寸缩小,器件密度的提高,形成鳍式场效应晶体管的工艺难度增大,且所形成的鳍式场效应晶体管的性能也不稳定。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法,使得所形成的半导体器件性能稳定。
为解决上述问题,本发明提供半导体器件的形成方法,包括步骤:提供衬底,所述衬底上形成有若干分隔排列的鳍部;在所述衬底上形成横跨所述鳍部的伪栅结构;在所述衬底上以及所述伪栅结构的侧壁上形成第一层间介电层,且所述第一层间介电层的顶部低于所述伪栅结构的顶部;定义切断开口图形;沿所述切断开口图形,刻蚀所述伪栅结构,直至暴露出所述衬底,形成切断开口;在所述第一层间介电层上形成第二层间介电层,且所述第二层间介电层填充满所述切断开口,所述第二层间介电层的顶部与所述伪栅结构的顶部齐平。
可选的,形成所述切断开口的方法为干法刻蚀法。
可选的,所述干法刻蚀法采用四氟化碳、六氟化硫外加氮气和氧气作为刻蚀气氛,其中所述四氟化碳的气体流量范围是50~2005sccm,所述六氟化硫的气体流量为5~500sccm,所述氮气的气体流量为6~300sccm,所述氧气的气体流量为1~250sccm,刻蚀压强为1~150毫托,刻蚀处理时间为10~2000s,电压为50~300V,功率为200~500W。
可选的,在形成第二层间介电层之前,还包括,在所述伪栅结构的侧壁及所述切断开口的侧壁形成绝缘层。
可选的,所述绝缘层采用单层或者叠层。
可选的,所述绝缘层为单层时,采用的材料为氮化硅或者氮氧化硅或者含硼的碳氮化硅或者碳氮化硅中的一种。
可选的,所述绝缘层为叠层时采用氮化硅或者氮氧化硅或者含硼的碳氮化硅或者碳氮化硅中的多种组合。
可选的,所述第一层间介电层的材料为氧化硅或者碳化硅或者氮氧化硅或者氮化硅中一种或者多种组合。
可选的,形成所述第一层间介电层的工艺为化学气相沉积法或者原子层沉积法。
可选的,所述第二层间介电层的材料为氧化硅或者碳化硅或者氮氧化硅或者氮化硅的一种或者多种组合。
可选的,形成所述第二层间介电层的工艺为化学气相沉积法或者原子层沉积法或者物理气相沉积法。
利用上述方法形成的一种半导体器件,包括:衬底;若干分隔排列的鳍部,位于所述衬底上;伪栅结构,位于所述衬底上,横跨所述鳍部;第一层间介电层,位于所述衬底上和所述伪栅结构的侧壁上,且顶部低于所述伪栅结构的顶部;切断开口,位于相应的所述伪栅结构内,且暴露出所述衬底;第二层间介电层,位于所述第一层间介电层上,填满所述切断开口。
与现有技术相比,本发明的技术方案具有以下优点:
定义切断开口图形后,在所述伪栅结构内形成所述切断开口,在所述切断开口内填充所述第二层间介电层,不会在所述切断开口的侧壁上出现桥接的问题;这是由于所述切断开口的存在给所述第二层间介电层的填充提供了足够的空间,所述切断开口足够大,那么在所述第二层间介电层填充的时候,所述切断开口内的气体对所述第二层间介电层的作用越小,使得所述第二层间介电层的填充变得容易;同时由于填充所述切断开口时,所述第二层间介电层受到的气体作用力小,这样能够避免所述第二层间介电层在填充所述切断开口时在内部形成孔洞,从而避免由于孔洞的存在而导致漏电流以及桥接问题的产生,提高半导体器件的性能和稳定性。
进一步,在所述伪栅结构的侧壁及所述切断开口的侧壁形成绝缘层,由于所述绝缘层的存在,在后续的加工工艺中能够增大接触插塞与金属栅极之间的距离,从而改善两者之间的桥接问题。
附图说明
图1至图6是一种图形结构形成过程的结构示意图;
图7至图14是本发明第一实施例中半导体器件形成过程的结构示意图;
图15至图26是本发明第二实施例中半导体器件形成过程的结构示意图。
具体实施方式
目前形成的半导体器件的性能稳定性差,具体形成过程参考图1至图6。
图1至图6是一种半导体器件形成过程的结构示意图。
参考图1,提供衬底1,所述衬底1上形成有若干分隔排列的鳍部2。
参考图2,在所述衬底1上形成隔离结构3。
参考图3,在所述衬底1上形成所述伪栅结构4,且所述伪栅结构4横跨所述鳍部2。
参考图4,刻蚀相邻所述鳍部2之间的部分所述伪栅结构4,在所述伪栅结构4内形成切断开口5。
参考图5,在所述切断开口5的侧壁上、所述伪栅结构4的侧壁上形成侧墙6。
参考图6,在所述切断开口5内填充层间介电层7。
发明人发现,利用上述方法在所述切断开口5内在形成所述层间介电层7时,所述层间介电层7更容易依附在所述切断开口5侧壁的侧墙6上,且在所述切断开口5内形成的所述层间介电层7之间容易有孔洞,从而在半导体使用的过程中容易出现桥接的问题,影响半导体器件的性能。
发明人研究发现,在对应所述伪栅结构内形成切断开口之后,在所述伪栅结构侧壁形成侧墙之前,在所述切断开口内沉积所述层间介电层,所述层间介电层容易填满所述开口,且在所述层间介电层内不会出现孔洞的现象,可以消除所述层间介电层在填充所述切断开口时产生的边缘问题,从而提高半导体器件的使用性能以及稳定性,避免引起桥接的问题。
同时发明人发现,先形成切断开口之后,在所述切断开口的侧壁上容易形成厚度很薄的绝缘层,由于绝缘层的存在,还能增加接触插塞与金属栅极之间的距离,从而提高半导体器件使用的稳定性。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细地说明。
第一实施例
图7至图14是本发明第一实施例中半导体器件形成过程的结构示意图。
首先参考图7,提供衬底100,在所述衬底100上形成有若干分隔排列的鳍部200。
本实施例中,所述衬底100的材料为单晶硅;其他实施例中,所述基底100可以是单晶硅,多晶硅或非晶硅;所述衬底100也可以是硅、锗、锗化硅、砷化镓等半导体材料。
形成所述鳍部200的方法包括:先在所述衬底100上形成光刻胶层;曝光、显影工艺后,在所述光刻胶层内形成光刻胶图案;之后以图案化后的光刻胶层为掩膜刻蚀所述衬底100,从而在衬底100上形成鳍部200。
参考图8至图9,在所述衬底100上形成横跨所述鳍部200的所述伪栅结构300。
图9为图8沿着剖线A-A的剖面图。
本实施例中,所述伪栅结构300的材料为多晶硅;其他实施例中,所述伪栅结构300的材料还可为非晶碳或者氮化硅。
形成所述伪栅结构300的方法包括:在所述衬底100的表面形成栅极氧化层(图中未画出),在所述栅极氧化层上形成栅极层,在所述栅极层上形成图形化层,所述图形化层覆盖需要形成所述伪栅结构300的对应区域;以图形化层为掩膜,刻蚀所述栅极层以及所述栅极氧化层,直至暴露出所述衬底100。
参考图10至图11,在所述衬底100上形成第一层间介电层(ILD)400,刻蚀所述第一层间介电层400,使得所述第一层间介电层400的顶部低于所述伪栅结构300的顶部。
图11为图10在剖线A-A的剖面图。
本实施例中,所述第一层间介电层400的材料采用氧化硅;其他实施例中,所述第一层间介电层400还可以采用碳化硅或者氮氧化硅或者氮化硅或者聚合物或者聚苯并恶唑(PBO)等介电材料。
本实施例中,形成所述第一层间介电层400工艺为化学气相沉积工艺;所述第一层间介电层400的工艺参数包括采用的气体包括氧气、氨气(NH3)、和N(SiH3)3气体,氧气的流量为20sccm~10000sccm,氨气(NH3)气体的流量为20sccm~10000sccm,N(SiH3)3气体的流量为20sccm~10000sccm,腔室压强为0.01~10托,温度为30℃~90℃。
其他实施例中,还可以采用原子层沉积法或者等离子体增强化学气相沉积法等方法形成所述第一层间介电层400。
本实施例中,采用干法刻蚀所述第一层间介电层400,直至所述第一层间介电层400的顶部低于所述伪栅结构300的顶部;刻蚀所述第一层间介电层400的工艺参数包括,选用氦气(He)、氨气(NH3)以及NF3气体作为刻蚀气氛,其中所述氦气(He)的气体流量范围是600sccm~2000sccm,所述氨气(NH3)的气体流量为200sccm~5000sccm,所述NF3气体流量为20sccm~2000sccm,刻蚀压强为2~100毫托,刻蚀处理时间为20~1000s。
参考图12,定义切断开口图形,沿着所述切断开口图形,刻蚀所述伪栅结构300,直至暴露出所述衬底100,形成切断开口500。
本实施例中,所述切断开口500位于传输晶体管、上拉晶体管和下拉晶体管之间。
本实施例中,采用干法刻蚀形成所述切断开口500;其他实施例中,还可以采用湿法刻蚀等方法形成所述切断开口500。
本实施例中,所述干法刻蚀的工艺参数包括采用四氟化碳、六氟化硫外加氮气和氧气作为刻蚀气氛,其中所述四氟化碳的气体流量范围是50~2005sccm,所述六氟化硫的气体流量为5~500sccm,所述氮气的气体流量为6~300sccm,所述氧气的气体流量为1~250sccm,刻蚀压强为1~150毫托,刻蚀处理时间为10~2000s,电压为50~300V,功率为200~500W。
本实施例中,所述切断开口500的宽度为30-60纳米;当所述切断开口500的宽度小于30纳米的时,在后续的工艺,由于切断开口500的宽度太小,所述切断开口500内部的气压较大,不易于填充层间介电层;同时填充的层间介电层的内部易形成孔洞,致密性差,容易产生桥接的问题而影响半导体器件的性能;当所述切断开口500的宽度大于60纳米的时,由于所述切断开口500的宽度较大,不利于形成集成度高的半导体器件。
参考图13至图14,在所述第一层间介电层400上形成第二层间介电层(ILD)600,且所述第二层间介电层600填充满所述切断开口500,所述第二层间介电层600顶部与所述伪栅结构300顶部齐平。
图14是图13在剖线A-A的剖面图。
本实施例中,由于所述切断开口500的存在为所述第二层间介电层600的填充提供了足够的空间,易于在所述切断开口500内形成质量较好的所述第二层间介电层600;这是由于所述切断开口500为所述第二层间介电层600的填充提供足够大的空间,所述切断开口500内部的气压较小,这样在填充所述第二层间介电层600时,所述切断开口500内部的气体对所述第二层间介电层600作用小,便于形成致密性好的所述第二层间介电层600,从而能够避免在所述第二层间介电层600形成孔洞而造成漏电或者桥接得问题,影响半导体器件的质量与使用的稳定性。
本实施例中,所述第二层间介电层600的材料为氧化硅;其他实施例中,所述第二层间介电层600还可以采用碳化硅或者氮氧化硅或者氮化硅或者聚合物或者聚苯并恶唑(PBO)等介电材料。
本实施例中,所述第二层间介电层600的材料与所述第一层间介电层400的材料一样;其他实施例中,所述第二层间介电层600的材料与所述第一层间介电层400的材料还可以不一样。
本实施例中,形成所述第二层间介电层600工艺为化学气相沉积工艺;所述第二层间介电层600的工艺参数包括采用的气体包括氧气、氨气(NH3)、和N(SiH3)3气体,氧气的流量为20sccm~10000sccm,氨气(NH3)气体的流量为20sccm~10000sccm,N(SiH3)3气体的流量为20sccm~10000sccm,腔室压强为0.01~10托,温度为30℃~90℃。
其他实施例中,还可以采用原子层沉积法或者物理等方法形成所述第二层间介电层600。
本实施例中,形成所述第二层间介电层600后,通过化学机械研磨的方式使其平坦化;其他实施例中,还可采用机械研磨工艺使得所述第二层间介电层600的顶部与所述伪栅结构300的顶部齐平。
本实施例中,采用化学机械研磨的方式的原因在于化学机械研磨方法综合了化学研磨和机械研磨的优势,可以保证获得表面平整度高的所述第二层间介电层600,有助于形成质量好的半导体器件。
利用上述方法形成的一种半导体器件,所述半导体器件包括衬底100;若干分隔排列的鳍部200,位于所述衬底100上;伪栅结构300,位于所述衬底100上,且横跨所述鳍部200;第一层间介电层400,位于所述衬底100上和所述伪栅结构300的侧壁上,且顶部低于所述伪栅结构300的顶部;切断开口500,位于相应的所述伪栅结构300内;第二层间介电层600,位于所述第一层间介电层400上,填满所述切断开口500。
第二实施例
图15至图26是本发明第二实施例中半导体器件形成过程的结构示意图。
参考图15,提供衬底100,所述衬底100上形成有若干分隔排列的鳍部200和隔离结构201。
本实施例中,形成所述鳍部200的方法与第一实施例中形成所述鳍部200的方法相同。
本实施例中,在所述衬底100上形成有隔离结构201;其他实施例中,也可在所述衬底100上不形成所述隔离结构201。
本实施例中,所述隔离结构201采用氮氧化硅材料;其他实施例中,所述隔离结构201的材料还可为氧化硅或者氮化硅或者碳氧化硅或者碳氮化硅或碳氮氧化硅的一种或者多种组合。
本实施例中,所述隔离结构201采用浅隔离结构。
本实施例中,所述隔离结构201用于后的刻蚀过程中,作为刻蚀停止层。
所述隔离结构201的形成步骤包括:在所述衬底100上形成覆盖鳍部200的隔离结构膜(未图示);回刻蚀隔离结构膜,形成所述隔离结构201。
形成所述隔离结构膜的工艺为沉积工艺,如流体化学气相沉积工艺。采用流体化学气相沉积工艺形成隔离结构膜,使隔离结构膜的填充性能较好。
形成隔离结构膜所采用的流体化学气相沉积工艺的步骤包括:在衬底100上形成隔离流体层;进行水汽退火,使所述隔离流体层形成隔离结构膜。
所述水汽退火的参数包括:采用的气体包括氧气、臭氧和气态水,退火温度为350℃~750℃。
参考图16至图17,在所述衬底100上形成横跨所述鳍部200的伪栅结构300,在所述伪栅结构300上形成有掩膜层301。
图17是图16在剖线A-A的剖面图。
本实施例中,在所述伪栅结构300上还形成有掩膜层301;其他实施例中,在所述伪栅结构300上还可以不形成所述掩膜层301。
本实施例中,所述掩膜层301的材料为碳化硅;其他实施例中,所述掩膜层301还可采用氧化硅或者氮化硅等。
参考图18至图19,在所述伪栅结构300侧壁上形成侧墙302。
图19为图18在剖线A-A的剖面图。
本实施例中,形成所述伪栅极结构300之后,还包括在所述伪栅极结构300侧壁形成侧墙302;其他实施例中,在伪栅结构300的侧壁上还可不形成所述侧墙302。
所述侧墙302用于定义后续形成的源漏掺杂层的位置,且所述侧墙302用作保护所述伪栅结构300侧壁,避免后续形成的栅极层出现形貌缺陷,影响半导体结构的电学性能。
本实施例中,所述侧墙302包括第一侧墙3021和第二侧墙3022,第一侧墙3021位于所述伪栅结构300和所述掩膜层301的侧壁上,第二侧墙3022位于所述第一侧墙3021侧壁上,第一侧墙用于定义轻掺杂区的位置,第一侧墙和第二侧墙用于定义源漏掺杂层的位置;其他实施例中,还可形成单层结构的所述侧墙302。
本实施例中,所述侧墙302采用叠层结构;其他实施例中,所述侧墙302还可以采用单层结构。
本实施例中,所述第一侧墙3021的材料和所述第二侧墙3022的材料不同。
本实施例中,所述第一侧墙3021的材料为氮氧化硅;其他实施例中,所述第一侧墙3021的材料还可为氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅。
本实施例中,所述第二侧墙3022的材料为碳氧化硅;其他实施例中,所述第二侧墙3022的材料还可为氧化硅、氮氧化硅、氮化硅、碳氮氧化硅。
本实施例中,所述第一侧墙3021的厚度为1~7纳米。
本实施例中,所述第二侧墙3022的厚度为6~15纳米。
参考图20至图21,在所述衬底100上形成第一层间介电层(ILD)400,刻蚀所述第一层间介电层400,使得所述第一层间介电层400的顶部低于侧墙302的顶部。
图21为图20在剖线A-A的剖面图。
本实施例中,采用原子层沉积方法形成所述第一层间介电层400;其他实施例中,还可采用化学气相沉积法或者物理气相沉积法。
本实施例中,所述第一层间介电层400的材料采用碳化硅;其他实施例中,还可以采用氧化硅或者氮氧化硅或者氮化硅或者聚合物或者聚苯并恶唑(PBO)等介电材料。
参考图22,定义切断开口图形,沿着所述切断开口图形,刻蚀所述伪栅结构300,直至暴露出所述衬底100,形成切断开口500。
本实施例中,形成所述切断开口500的方法与第一实施例中一样。
参考图23至图24,在所述第二侧墙3022的侧壁上、所述切断开口500的侧壁形成绝缘层501。
图24是图23在剖线A-A的剖面图。
本实施例中,在所述切断开口500的侧壁上、所述第二侧墙3022的侧壁上形成绝缘层501;其他实施例中,还可不形成所述绝缘层501。
本实施例中,由于所述绝缘层501的存在,能够增大接触插塞与金属栅极之间的距离,从而改善两者之间的桥接问题,提高半导体器件使用的稳定性以及性能。
本实施例中,所述绝缘层501的厚度3~20nm;当所述绝缘层501的厚度小于3nm时,导电插塞到金属栅极之间距离太小,同时工艺窗口也变得更小,不利于形成稳定的半导体器件;当所述绝缘层501的厚度大于20nm时,绝缘层500太厚,给所述绝缘层501的填充带来问题,同时浪费材料。
本实施例中,所述绝缘层501采用单层结构;其他实施例中,所述绝缘层501还可以采用叠层结构。
本实施例中,所述绝缘层501的材料采用氮化硅;其他实施例中,当所述绝缘层501采用单层时,所述绝缘层501还可采用氮氧化硅或者含硼的碳氮化硅或者碳氮化硅中的一种;当所述绝缘层501采用叠层时,所述绝缘层501的材料还可以采用氮化硅或者氮氧化硅或者含硼的碳氮化硅或者碳氮化硅中的多种组合。
本实施例中,采用化学气相沉积的方法形成绝缘层材料,工艺参数包括:采用的气体包括DCS气体掺杂SiH2Cl2或者氨气(NH3),所述气体的流量为1500~4000sccm;温度为200~600℃;刻蚀压强为1~10毫托。
本实施例中,刻蚀所述绝缘层材料形成所述绝缘层501,直至暴露出所述衬底100,刻蚀的工艺为选用四氟化碳(CF4)、CH3F气体和氧气(O2)作为刻蚀气氛;所述四氟化碳(CF4)气体的气体流量范围是5~100sccm、所述CH3F气体的气体流量范围是8~250sccm;所述氧气(O2)的气体流量范围是10~400sccm;采用的源射频功率RF的范围是50~300W;电压范围是30~~100V;刻蚀处理时间为4~~50s;刻蚀压强为10~2000毫托。
参考图25至图26,在所述第一层间介电层400上形成第二层间介电层600,且所述第二层间介电层600填充满所述切断开口500,所述第二层间介电层600顶部与所述掩膜层301的顶部齐平。
图26是图25在剖线A-A的剖面图。
本实施例中,所述第二层间介电层600的材料为氧化硅;其他实施例中,所述第二层间介电层600还可以采用碳化硅或者氮氧化硅或者氮化硅或者聚合物或者聚苯并恶唑(PBO)等介电材料。
本实施例中,采用化学气相沉积的方法形成所述第二层间介电层600。
其他实施例中,还可以采用原子层沉积法或者等离子体增强化学气相沉积法或者物理等方法形成所述第二层间介电层600。
本实施例中,形成所述第二层间介电层600后,通过化学机械研磨的方式使其平坦化;其他实施例中,还可采用机械研磨工艺使得所述第二层间介电层600的顶部与所述掩膜层301的顶部齐平。
上述方法形成的一种半导体器件,所述半导体器件包括衬底100;若干分隔排列的鳍部200,位于所述衬底100上;隔离结构201,位于所述衬底100上;伪栅结构300,位于所述衬底100上,且横跨所述鳍部200;掩膜层301,位于所述伪栅结构300上;第一侧墙3021,位于所述伪栅结构300和所述掩膜层301的侧壁上;第二侧墙3022,位于所述第一侧墙3021的侧壁上;第一层间介电层400,位于所述衬底100上和所述第二侧墙3022的侧壁上,且顶部低于所述第二侧墙3022的顶部;切断开口500,位于相应的所述伪栅结构300内;绝缘层501,位于所述切断开口500的侧壁上及所述第二侧墙3022的侧壁上;第二层间介电层600,位于所述第一层间介电层400上,填满所述切断开口500。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (12)
1.一种半导体器件的形成方法,其特征在于,包括:
提供衬底,所述衬底上形成有若干分隔排列的鳍部;
在所述衬底上形成横跨所述鳍部的伪栅结构;
在所述衬底上以及所述伪栅结构的侧壁上形成第一层间介电层,且所述第一层间介电层的顶部低于所述伪栅结构的顶部;
定义切断开口图形;
沿所述切断开口图形,刻蚀所述伪栅结构,直至暴露出所述衬底,形成切断开口;
在所述第一层间介电层上形成第二层间介电层,且所述第二层间介电层填充满所述切断开口,所述第二层间介电层的顶部与所述伪栅结构的顶部齐平。
2.如权利要求1所述半导体器件的形成方法,其特征在于,形成所述切断开口的方法为干法刻蚀法。
3.如权利要求2所述半导体器件的形成方法,其特征在于,所述干法刻蚀法采用四氟化碳、六氟化硫外加氮气和氧气作为刻蚀气氛,其中所述四氟化碳的气体流量范围是50~2005sccm,所述六氟化硫的气体流量为5~500sccm,所述氮气的气体流量为6~300sccm,所述氧气的气体流量为1~250sccm,刻蚀压强为1~150毫托,刻蚀处理时间为10~2000s,电压为50~300V,功率为200~500W。
4.如权利要求1所述半导体器件的形成方法,其特征在于,在形成第二层间介电层之前,还包括:
在所述伪栅结构的侧壁及所述切断开口的侧壁形成绝缘层。
5.如权利要求4所述半导体器件的形成方法,其特征在于,所述绝缘层采用单层或者叠层。
6.如权利要求5所述半导体器件的形成方法,其特征在于,所述绝缘层为单层时,采用的材料为氮化硅或者氮氧化硅或者碳氮化硅中的一种。
7.如权利要求5所述半导体器件的形成方法,其特征在于,所述绝缘层为叠层时采用氮化硅或者氮氧化硅或者碳氮化硅中的多种组合。
8.如权利要求1所述半导体器件的形成方法,其特征在于,所述第一层间介电层的材料为氧化硅或者碳化硅或者氮氧化硅或者氮化硅中一种或者多种组合。
9.权利要求8所述半导体器件的形成方法,其特征在于,形成所述第一层间介电层的工艺为化学气相沉积法或者原子层沉积法。
10.如权利要求1所述半导体器件的形成方法,其特征在于,所述第二层间介电层的材料为氧化硅或者碳化硅或者氮氧化硅或者氮化硅的一种或者多种组合。
11.如权利要求10所述半导体器件的形成方法,其特征在于,形成所述第二层间介电层的工艺为化学气相沉积法或者原子层沉积法或者物理气相沉积法。
12.一种采用权利要求1至11任意一项方法形成的半导体器件,其特征在于,包括:
衬底;
若干分隔排列的鳍部,位于所述衬底上;
伪栅结构,位于所述衬底上,横跨所述鳍部;
第一层间介电层,位于所述衬底上和所述伪栅结构的侧壁上,且顶部低于所述伪栅结构的顶部;
切断开口,位于相应的所述伪栅结构内,且暴露出所述衬底;
第二层间介电层,位于所述第一层间介电层上,填满所述切断开口。
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