TWI715317B - 半導體裝置的製造方法及半導體裝置 - Google Patents

半導體裝置的製造方法及半導體裝置 Download PDF

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TWI715317B
TWI715317B TW108143412A TW108143412A TWI715317B TW I715317 B TWI715317 B TW I715317B TW 108143412 A TW108143412 A TW 108143412A TW 108143412 A TW108143412 A TW 108143412A TW I715317 B TWI715317 B TW I715317B
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TW202020993A (zh
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吳顯揚
林大鈞
潘國華
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種半導體裝置的製造方法，包括：於基板上形成複數個交替層堆疊；從複數個交替層堆疊建構複數個奈米片；且於複數個奈米片之上形成複數個閘極介電質。此方法能夠調整奈米片的寬度、厚度、間距與堆疊數量，並可用於單一基板上。此設計彈性設計對電路性能與功率運用的設計最佳化提供廣泛的調整範圍。

Description

半導體裝置的製造方法及半導體裝置
本發明實施例是關於一種半導體裝置的製造方法，特別是關於一種閘極結構的製造方法。
半導體裝置用於大量的電子裝置之中，如電腦、手機以及其他裝置。半導體裝置包括形成於半導體晶圓（wafer）上的積體電路，於半導體晶圓之上沉積許多型態的薄膜材料，及圖案化薄膜材料以形成積體電路。積體電路包括場效電晶體（field-effect transistor, FET）如金屬氧化物半導體電晶體。
半導體產業其中一個目標為不斷地縮小單一場效電晶體的尺寸並增加其速度。為了達到這些目標而研究且實施鰭狀場效電晶體（finFET）、多閘極電晶體（multiple gate transistor）與全繞式閘極（gate all-around）電晶體。然而，隨著不斷地縮小尺寸，即便是這樣的新裝置結構仍會面臨許多嶄新的難題。
本發明實施例提供一種半導體裝置的製造方法，包括：於基板上形成第一交替層堆疊，其中形成第一交替層堆疊的步驟包括於基板上交替沉積第一半導體材料的第一層與第二半導體材料的第二層，第二半導體材料與第一半導體材料不同；於基板上形成第二交替層堆疊，距第一交替層堆疊第一距離，其中形成第二交替層堆疊的步驟包括於基板上交替沉積第一半導體材料的第一層與第二半導體材料的第二層，且其中相對該第一交替層堆疊的第一層，第二交替層堆疊的第一層具有較大的厚度；從第一交替層堆疊建構第一奈米片堆疊且從第二交替層堆疊建構第二奈米片堆疊，其中建構第一與第二奈米片堆疊的步驟包括：從第一交替層堆疊圖案化第一鰭片，且從第二交替層堆疊圖案化第二鰭片；以及從第一交替層堆疊移除第一層且從第二交替層堆疊移除第一層，使得第二交替層堆疊相鄰的剩餘層間之距離大於第一交替層堆疊相鄰的剩餘層間之距離；以及於第一奈米片堆疊之上形成第一閘極介電質，且於第二奈米片堆疊之上形成第二閘極介電質。
本發明實施例提供一種半導體裝置的製造方法，包括：於基板上的第一交替層堆疊中蝕刻凹口，其中第一交替層堆疊包括交替的第一層與第二層，第一層包括第一半導體材料而第二層包括第二半導體材料，第一半導體材料與第二半導體材料不同，其中第一交替層堆疊的第一層具有第一平均厚度，而第一交替層堆疊的第二層具有第二平均厚度，其中透過控制第一交替層堆疊的第一層與第二層的磊晶成長，決定第一平均厚度與第二平均厚度；於第一交替層堆疊中形成第二交替層堆疊，其中形成第二交替層堆疊的步驟包括於凹口中沉積交替的第一層與第二層，第一層包括第一半導體材料，而第二層包括第二半導體材料，其中第二交替層堆疊的第一層具有第三平均厚度，而第二交替層堆疊的第二層具有第四平均厚度，第三平均厚度與第一平均厚度不同，且第四平均厚度與第二平均厚度不同，其中透過控制第二交替層堆疊的第一層與第二層的磊晶成長，決定第三平均厚度與第四平均厚度；從第一交替層堆疊建構第一奈米片堆疊，且從第二交替層堆疊建構第二奈米片堆疊，其中建構第一與第二奈米片堆疊的步驟包括：從第一交替層堆疊圖案化第一鰭片，且從第二交替層堆疊圖案化第二鰭片；以及從第一交替層堆疊與第二交替層堆疊移除第一層與第二層的其中之一；以及於第一奈米片堆疊之上形成第一閘極介電質，且於第二奈米片堆疊之上形成第二閘極介電質。
本發明實施例提供一種半導體裝置，包括：第一奈米片堆疊，其中第一閘極介電質圍繞第一奈米片堆疊的每個奈米片，其中第一奈米片堆疊的相鄰奈米片以第一平均間距彼此隔離；以及第二奈米片堆疊，距第一奈米片堆疊第一距離，其中第二閘極介電質圍繞第二奈米片堆疊的每個奈米片，其中第二奈米片堆疊的相鄰奈米片以第二平均間距彼此隔離，其中第二平均間距大於第一平均間距。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在……下方」、「在……之下」、「下方的」、「在……之上」、「上方的」等類似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
第1至21C圖繪示出形成兩水平全繞式閘極電晶體彼此距一距離的示意圖，其相對彼此具有調節的閘極介電質的厚度以及∕或組成、薄片（sheet）厚度、薄片間距、薄片寬度及堆疊數量。第22至28圖繪示出形成三個水平全繞式閘極電晶體彼此距不同距離的示意圖，其相對彼此具有調節的閘極介電質的厚度以及∕或組成、薄片厚度、薄片間距、薄片寬度及堆疊數量。第1、2A、6A、7A、8A、9、10A、11、12A、17、18A、19A、20A與21A為三維（three-dimensional, 3D）示意圖。第2B、3、4A、4B、4C、4D、5A、5B、6B、7B、8B、10B、12B、18B、19B、20B、21B、22、23、24、25、26、27、28A與28B是沿著參考剖面B-B（繪示於第2A、6A、12A與18A圖中）所繪示的剖面圖。第12C、13、14、15、16、18C、19C、20C與21C是沿著參考剖面C-C（繪示於第12A與18A圖中）所繪示的剖面圖。
現在參照第1圖，此圖式是根據一些實施例繪示出摻質（dopant）抗擊穿佈植（anti-punch-through implant, APT implant）至原材料（source material）100中的示意圖。原材料100可為基板101之形式，例如可為半導體基板如矽基板、矽鍺基板、鍺基板、III-V族材料基板（如GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb以及∕或GaInAsP；或前述之組合）或者是使用如具有高帶間穿遂（band-to-band tunneling, BTBT）的其他半導體材料所形成的基板。基板101可為摻雜或未摻雜。可使用n型或p型雜質（impurity）摻雜基板101。在一些實施例中，基板101可為塊狀（bulk）半導體基板如為晶圓的塊狀矽基板、絕緣體上覆半導體（semiconductor-on-insulator, SOI）基板、多層或梯度（gradient）基板或類似基板。
進行第一佈植製程103（如第1圖中箭頭所表示）以佈植第一摻質至基板101的第一源極區。在一實施例中，對於如抗擊穿佈植可佈植第一摻質。然而，可利用任何合適的佈植製程。
第2A圖是製造全繞式閘極電晶體時中間階段的多層結構200之三維示意圖。第2B圖是沿著第2圖中的剖面B-B所繪示的多層結構200之剖面圖。第2A與2B圖中，第一交替（alternating）層堆疊203a形成於基板101上。第一交替層堆疊203a包括第一半導體材料的第一半導體層205a（如SiGe層）與第二半導體材料的第二半導體層207a（如Si層）所交替的膜層。在一些實施例中，第一半導體層205a（如SiGe層）與第二半導體層207a（如Si層）的每層磊晶（epitaxially）生成於其下方層上。交替層堆疊203a可包括任何數量的第一半導體層205a（如SiGe層）與任何數量的第二半導體層207a（如Si層）。磊晶成長可使用化學氣相沉積（chemical vapor deposition, CVD）、金屬有機化學氣相沉積（metal organic CVD, MOCVD）、分子束磊晶（molecular beam epitaxy, MBE）、液相磊晶（liquid phase epitaxy, LPE）、氣相磊晶（vapor phase epitaxy, VPE）、超高真空化學氣相沉積（ultrahigh vacuum CVD, UHVCVD）、類似製程或前述之組合。第一半導體層205a（如SiGe層）與任何數量的第二半導體層207a（如Si層）的每層可為IV族材料如Si、Ge、SiGe、SiGeSn、SiC或類似物；III-V族化合物材料如GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb、GaInAsP或類似物。
交替層堆疊203a可包括任何數量的第一半導體層205a（如SiGe層）與任何數量的第二半導體層207a（如Si層）。如圖所示，例如，交替層堆疊203a具有5層第一半導體層205a（如SiGe層）與四層第二導體層207a（如Si層）。透過用於形成第一交替層堆疊的磊晶成長循環之數量，可分別調整第一半導體層205a（如SiGe層）與第二半導體層207a（如Si層）的數量。
第3圖繪示出圖案化並蝕刻溝槽305至交替層堆疊203a中之示意圖。可利用微影技術圖案化交替層堆疊203a。一般而言，光阻材料（未繪示）沉積於交替層堆疊203a之上。以輻射（如光）通過圖案化光罩（reticle）照射光阻材料（曝光），使曝露於能量的光阻材料的這些部分中發生反應。顯影光阻材料以移除一部分的光阻材料，其中剩餘的光阻材料保護下方材料在後續製程步驟中不受影響。
圖案化後，如第3圖所繪示，蝕刻溝槽305使其具有垂直輪廓（profile）。蝕刻製程可為乾式蝕刻。蝕刻製程可包括反應離子蝕刻（reactive ion etch, RIE）、中子束蝕刻（neutral beam etch, NBE）、感應耦合電漿（inductively coupled plasma, ICP）蝕刻、電容耦合電漿（capacitively coupled plasma, CCP）蝕刻、離子束蝕刻（ion beam etch, IBE）、類似蝕刻製程或前述之組合。蝕刻製程可為非等向性（anisotropic）。在一些實施例中，蝕刻製程可包括使用第一氣體的電漿，其包括四氟化碳（carbon tetrafluoride, CF4 ）、六氟乙烷（hexafluoroethane, C2 F6 ）、八氟丙烷（octafluoropropane, C3 F8 ）、三氟甲烷（fluoroform, CHF3 ）、二氟甲烷（difluoromethane, CH2 F2 ）、氟甲烷（fluoromethane, CH3 F）、氟化碳（如Cx Fy ，其中x可在1至5的範圍，而y可在4至8的範圍）、類似物或前述之組合。電漿更可使用第二氣體，其包括氮氣（N2 ）、氫氣（H2 ）、氧氣（O2 ）、氬氣（Ar）、氙氣（Xe）、氦氣（He）、一氧化碳（CO）、二氧化碳（CO2 ）、羰基硫（COS）、類似物或前述之組合。蝕刻製程中可視需要地供應惰性（inert）氣體。溝槽305可接觸基板101的頂表面，或可蝕刻溝槽305至低於基板101頂表面的深度。
第4A圖繪示出間隔物（spacer）層310形成於溝槽305的側壁與底表面上及形成於交替層堆疊203a最高表面之上的實施例。可使用介電材料如氮化矽、碳氮氧化矽（silicon carbon-oxynitride）或類似物形成間隔物層310。
第4B圖繪示出移除間隔物層310水平部分的示意圖。在一實施例中，利用非等向性蝕刻製程移除裝置水平部分之上的間隔物層310。由於間隔物層310在裝置水平部分及沿著溝槽305的側壁之厚度不同，留下沿著溝槽305側壁的間隔物311，而露出溝槽305底表面與交替層堆疊203a的最高表面。
第4C圖繪示出於溝槽305中形成第二交替層堆疊203b的實施例。第二交替層堆疊203b包括第一半導體材料的第一半導體層205b（如SiGe層）與第二半導體材料的第二半導體層207b（如Si層）的交替膜層。在一些實施例中，第一半導體層205b（如SiGe層）與第二半導體層207b（如Si層）的每層磊晶生成於其下方層上。第二交替層堆疊203b可包括任何數量的第一半導體層205b（如SiGe層）與任何數量的第二半導體層207b（如Si層）。如圖所示，例如，交替層堆疊203b具有四層第一半導體層205b（如SiGe層）與三層第二導體層207b（如Si層）。透過用於形成第二交替層堆疊203b的磊晶成長循環之數量，可分別調整第一半導體層205a（如SiGe層）與第二半導體層207a（如Si層）的數量。
第4D圖繪示出形成第二交替層堆疊203b的另一實施例。不同於第4A至4C圖中所繪示的實施例，第4D圖中所繪示的實施例並不包含形成間隔物。第二交替層堆疊203b形成於溝槽305中，其具有第一半導體材料的第一半導體層205b（如SiGe層）與第二半導體材料的第二半導體層207b（如Si層）的交替膜層，於溝槽305的側壁與底部順應地形成。第一半導體層205b（如SiGe層）與第二半導體層207b（如Si層）的每層順應地磊晶生成於其下方層上。
第一半導體層205a的平均厚度與第一半導體層205b的平均厚度可不相同，而第二半導體層207a的平均厚度與第二半導體層207b的平均厚度可不相同。膜層的相對平均厚度將決定裝置的奈米片（nanosheet）間之薄片間距。較大的薄片間距可於奈米片上產生較厚的輸出入（input-output, IO）閘極氧化物，其用於如輸出入裝置。在一實施例中，透過調節反應氣體的流速、生成溫度或各層磊晶成長期間的時間長度而控制膜層的磊晶成長，以決定第一半導體層205與第二半導體層207的相對平均厚度。相對於第一交替層堆疊203a的第一半導體層205a，第二交替層堆疊203b的第一半導體層205b可具有較大的厚度。相對於第一交替層堆疊203a的第一半導體層207a，第二交替層堆疊203b的第一半導體層207b可具有較大的厚度。第一半導體層205a的平均厚度可在約5nm至約30nm的範圍，第二半導體層207a的平均厚度可在約3nm至約30nm的範圍，第一半導體層205b的平均厚度可在約8nm至約40nm的範圍，而第二半導體層207b的平均厚度可在約3nm至約40nm的範圍。第一半導體層205a與第二半導體層207a的平均厚度比例可在約10:1至約1:6的範圍。第一半導體層205b與第二半導體層207b的平均厚度比例可在約10:1至約1:5的範圍。
在一些實施例中，第一半導體層205a與205b的材料與第二半導體層207a與207b的材料不同。例如，第一半導體層205a與205b可為SiGe層，而第二半導體層207a與207b可為Si層或SiC層。在另一實施例中，例如，第一半導體層205a與205b可為Si層或SiC層，而第二半導體層207a與207b可SiGe層。材料的差異可提供不同的應變（strain）以及∕或可提供第一半導體層205a與205b及第二半導體層207a與207b間的蝕刻選擇性，由以下內容將可清楚看出。
第5A與5B圖繪示出具有預期高度以及∕或數量的膜層之第一與第二交替層堆疊203a與203b的實施例，將沉積硬遮罩層209。繪示於第5A圖中的實施例從以上繪示於第4C圖中的實施例接著進行，而繪示於第5B圖中的實施例從以上繪示於第4D圖中的實施例接著進行。如第5A與5B圖中所繪示，硬遮罩層209可沉積於交替層堆疊203a與203b的最高表面之上。可利用沉積製程於沉積腔中形成硬遮罩層209，或可利用任何其他合適的製程於第一與第二交替層堆疊203a與203b之上形成硬遮罩層209。硬遮罩209可包括次膜層（sublayer）如墊（pad）氧化層與上方的墊氮化層。墊氧化層可為包括氧化矽的薄膜，可利用如熱氧化（thermal oxidation）製程形成墊氧化層。墊氧化層可作為第一與第二交替層堆疊203a與203b及上方的墊氮化層之間的黏著層（adhesion layer）。在一些實施例中，墊氮化層由氮化矽、氮氧化矽、碳氮化矽、類似物或前述之組合所形成，並可利用如低壓化學氣相沉積（low pressure CVD, LPCVD）或電漿輔助化學氣相沉積（plasma enhanced CVD, PECVD）形成墊氮化層。
第6A圖為多層結構200的三維示意圖，而第6B圖為沿著第6A圖中的剖面B-B所繪示的多層結構200之剖面圖。第6A與6B圖繪示的實施例是在硬遮罩層209已沉積於多層結構200的頂表面上後（如第5A與5B圖中所繪示），進行圖案化製程以於多層結構200中形成溝槽301。在一些實施例中，利用微影技術圖案化硬遮罩層209。一般而言，光阻材料（未繪示）沉積於硬遮罩209之上。通過圖案化的光罩照射輻射（如光）於光阻材料，使光阻材料曝露於能量的這些部分中發生反應。顯影光阻材料以移除一部分的光阻材料，其中剩餘光阻材料保護下方的材料在後續製程步驟中不受影響，後續製程步驟如蝕刻。
第6A與6B圖中，對多層結構200進行圖案化製程以形成溝槽301後，交替層堆疊203的剩餘區域與下方的基板101形成了鰭片（fin），如第一鰭片303a與第二鰭片303b（共同稱為鰭片303）。如第6A與6B圖中所示，鰭片303包括部分的交替層堆疊203a與203b（如部分的第一半導體層205a與205b（SiGe層）與部分的第二半導體層207a與207b（Si層））及部分的基板101。如第4A至4C與5A圖所繪示，在第二交替層堆疊203b形成於被間隔物311覆蓋的側壁之間的實施例中，蝕刻第二鰭片303b也移除了間隔物311。如以上第4D與5B圖中所示，在第二交替層堆疊203b順應地（conformally）形成於溝槽305的側壁與底部上之實施例中，蝕刻第二鰭片303b移除了非水平之部分的第一半導體層205c與第二半導體層207c。如以下將更詳細地討論，鰭片303將用以形成一或多個n型鰭狀場效電晶體以及∕或p型鰭狀場效電晶體的水平奈米片。儘管第2B圖繪示了兩個鰭片（第一鰭片303a與第二鰭片303b），應能理解可使用任何合適數量與型態的鰭片。
可圖案化鰭片303a與303b，使其具有介於4nm至100nm的不同寬度。例如，在一實施例中，鰭片303a的寬度可在約4nm至約100nm的範圍，而鰭片303b的寬度可在約4nm至約100nm的範圍。鰭片303a的寬度與鰭片303b的寬度之比例可在約25:1至約1:25的範圍。圖案化鰭片303將決定後續步驟中所形成之奈米片的寬度（薄片寬度）。較大的薄片寬度（或Weff ，奈米片有效寬度）使更高速度性能得以實現。較小的薄片寬度則使低功率應用（lower power application）得以實現。
根據一些實施例，第7A與7B圖繪示出形成淺溝槽隔離（shallow trench isolation, STI）區313的示意圖。第7A與7B圖中，介電絕緣材料沉積鄰近於鰭片303a與303b以形成淺溝槽隔離區313。淺溝槽隔離區313可由合適的介電材料所形成，如氧化矽、氮化矽、氮氧化矽、摻氟矽酸鹽玻璃（fluoride-doped silicate glass, FSG）、低介電常數介電質如摻碳氧化物、極（extremely）低介電常數介電質如多孔（porous）摻碳二氧化矽、聚合物如聚醯亞胺（polyimide）、類似物或前述之組合。淺溝槽隔離區313可包括襯層（liner，未繪示）與襯層之上的介電絕緣材料。可形成襯層為順應層（conformal layer），其水平部分與垂直部分具有彼此接近的厚度。在一些實施例中，利用製程如化學氣相沉積、流動式（flowable）化學氣相沉積或旋轉塗佈玻璃（spin-on glass）製程形成淺溝槽隔離區313，但可使用任何可接受的製程。接著，可對淺溝槽隔離區313進行一或多種硬遮罩移除製程以移除硬遮罩209，並移除淺溝槽隔離區313於鰭片303頂表面之上延伸的部分，可利用如化學機械研磨（chemical mechanical polishing, CMP）蝕刻製程或類似製程進行移除製程。
第8A與8B圖中，凹蝕（recessing）淺溝槽隔離區313以露出鰭片303的側壁。在一實施例中，利用一或多種選擇性蝕刻製程凹蝕淺溝槽隔離區313。交替層堆疊203a與203b的高度決定了凹口（recess）的深度。在一實施例中，凹口延伸至一深度，使最底層的第一半導體層205a與205b露出。或者，於淺溝槽隔離區313的上表面之下可留下最底層的第一半導體層205a與205b（如SiGe層）。
參照第9圖，虛置（dummy）閘極氧化層401形成於露出的鰭片303之上。在一些實施例中，可利用熱氧化、化學氣相沉積、濺射（sputtering）或本發明所屬技術領域中熟知而用於形成虛置閘極氧化層104的任何其他方法形成虛置閘極氧化層401。在一些實施例中，虛置閘極氧化層401可由與淺溝槽隔離區313相同的材料所形成。在其他實施例中，虛置閘極氧化層可由一或多種合適的介電材料所形成，如氧化矽、氮化矽、低介電常數介電質如摻碳氧化物、極低介電常數介電質如多孔摻碳二氧化矽、聚合物如聚醯亞胺、類似物或前述之組合。在其他實施例中，虛置閘極氧化層401包括具有高介電常數（k值，如大於3.9）的介電材料。材料可包括氮化矽、氮氧化物、金屬氧化物如HfO2 、HfZrOx 、HfSiOx 、HfTiOx 、HfAlOx 、類似物或前述之組合及多層。
參照第10A與10B圖，形成虛置閘極金屬堆疊419。虛置金屬層411沉積於虛置閘極氧化層401（繪示於第9圖中）之上。在一實施例中，虛置金屬層411為導電材料且可選自於下列之群組，包括：多晶矽（polycrystalline-silicon, poly-Si）、多晶矽鍺（poly-crystalline silicon-germanium, poly-SiGe）、金屬氮化物、金屬矽化物、金屬氧化物與金屬。在一實施例中，可利用物理氣相沉積（physical vapor deposition, PVD）、化學氣相沉積、濺射沉積或本發明所屬技術領域中熟知而用於沉積導電材料的其他技術沉積虛置金屬層411。可使用其他導電或非導電材料。沉積虛置金屬層411之後可平坦化其頂表面。
可利用製程如化學氣相沉積或旋轉塗佈玻璃製程，於虛置金屬層411之上沉積第一硬遮罩層413，但可利用任何可接受的製程。在一實施例中，第一硬遮罩層413可為氧化層（如氧化矽）。接著利用製程如化學氣相沉積或旋轉塗佈玻璃製程，於第一硬遮罩層413之上沉積第二硬遮罩層415，但可利用任何可接受的製程。圖案化第一硬遮罩層413與第二硬遮罩層415以於虛置金屬層411之上形成虛置閘極硬遮罩層堆疊417。在一實施例中，使用虛置閘極硬遮罩層堆疊417進行多晶矽蝕刻及虛置氧化物移除製程，以圖案化虛置金屬層411與虛置閘極氧化層401。圖案化時，從鰭片303的源極∕汲極區移除部分的虛置金屬層411與部分的虛置氧化層401，而在鰭片303的通道區之上留下部分的虛置金屬層411與部分的虛置氧化層401以形成虛置金屬閘極電極412。虛置金屬閘極電極412包括圖案化的虛置金屬層411與設置於圖案化的虛置金屬層411之下的圖案化的虛置閘極氧化層401。虛置金屬閘極電極412與虛置閘極硬遮罩層堆疊417共同形成虛置金屬閘極堆疊419。
虛置金屬閘極堆疊419將用以從鰭片303的露出部分定義及形成源極∕汲極區。接著將移除虛置金屬閘極堆疊419，以進行製程從鰭片303的露出部分（鰭片303的中間部分）定義及形成通道區，如以下所述。
現在參照第11圖，間隔物層431沉積於虛置金屬閘極堆疊419、鰭片303與淺溝槽隔離區313的上表面之上。在一實施例中，間隔物層431由氮化矽所形成並可具有單一層結構。在其他實施例中，間隔物層431可具有包括複數層的複合結構。例如，氮化矽層可形成於氧化矽層之上。在一實施例中，間隔物層431可順應地形成於鰭片303的磊晶源極∕汲極區、虛置金屬閘極堆疊419的側壁與上表面兩者及淺溝槽隔離區313的上表面上。在一實施例中，可利用原子層沉積（atomic layer deposition, ALD）、化學氣相沉積、類似製程或前述之組合形成間隔物層431。
接著，第12A、12B與12C圖繪示出進行非等向性蝕刻製程的示意圖，其移除了部分的間隔物層431與部分的鰭片303（如303a與303b）。可使用虛置金屬閘極堆疊419作為蝕刻遮罩，進行非等向性蝕刻製程。在一些實施例中，非等向性蝕刻後，間隔物431的側壁因非等向性蝕刻而與鰭片303各自的側壁對準（aligned）。第12C圖是沿著第12A圖中的剖面C-C所繪示的示意圖，剖面C-C通過鰭片303b並垂直於虛置金屬閘極堆疊419。以303b作為範例，沿著剖面C-C所繪示的示意圖代表在所有鰭片303上進行的製程與結構。如第12C圖中所繪示，非等向性蝕刻也可蝕刻凹口105至鰭片303其中一側上的基板101之上表面中。
接著，第13圖中，是沿著第12A圖中剖面C-C所繪示的示意圖，進行側向（lateral）選擇性蝕刻製程以凹蝕露出的第一半導體材料。可使用對第一半導體材料具選擇性的蝕刻劑進行側向選擇性蝕刻製程，如以下第19A、19B與19C圖的討論中所述。在第13圖的範例中，第一半導體層205由第一半導體材料（如SiGe）所形成，因此，側向選擇性蝕刻凹蝕了第一半導體層205。
接著，第14圖中，是沿著第12A圖中剖面C-C所繪示的示意圖，形成介電材料409以填充移除第一半導體材料而留下的空間，留下的空間是從以上參照第13圖所討論之第一半導體層205的露出部分移除第一半導體材料而產生的。介電材料409可為低介電常數介電材料，如SiO2 、SiN、SiCN或SiOCN，並可利用合適的沉積方法如原子層沉積形成介電材料409。
接著，第15圖中，是沿著第12A圖中剖面C-C所繪示的示意圖，沉積介電材料409後，可進行非等向性蝕刻製程以修整（trim）沉積的介電材料409，使得僅有部分的沉積介電材料409留下，其填充了從第一半導體層205移除第一半導體材料而留下的空間。修整製程後，沉積的介電材料409的剩餘部分形成了內（inner）間隔物410。內間隔物410用以隔離金屬閘極與形成於後續製程中的源極∕汲極區。在第15圖的範例中，內間隔物410的側壁與第二半導體層207的側壁對準。
接著，第16圖中，是沿著第12A圖中剖面C-C所繪示的示意圖，源極∕汲極區503形成於基板101的凹口105中。於凹口105中磊晶生成材料而形成了源極∕汲極區503，可利用合適的方法如金屬有機化學氣相沉積、分子束磊晶、液相磊晶、氣相磊晶、選擇性磊晶成長（selective epitaxial growth, SEG）、類似方法或前述之組合形成源極∕汲極區503。磊晶源極∕汲極區503填充了相鄰的鰭片303之間的空間。磊晶源極∕汲極區503可具有從鰭片303表面抬升（raised）的表面並具有刻面（facet）。在一些實施例中，相鄰的源極∕汲極區503可合併形成連續的磊晶源極∕汲極區133。如以下第17圖中所示，相鄰的源極∕汲極區503並未合併而保留各自的源極∕汲極區503。可根據所形成的裝置型態調整源極∕汲極區133的材料。在一些實施例中，所製得的全繞式閘極場效電晶體為n型鰭狀場效電晶體，而源極∕汲極區503包括碳化矽（SiC）、磷化矽（SiP）、摻磷碳化矽（SiCP）或類似物。在一些實施例中，所製得的全繞式閘極場效電晶體為p型鰭狀場效電晶體，而源極∕汲極區503包括SiGe，p型雜質如硼或銦。
可使用摻質佈植磊晶源極∕汲極區503並接著進行退火製程。佈植製程可包括形成並圖案化遮罩如光阻，以覆蓋在佈植製程欲保護的全繞式閘極場效電晶體裝置之區域。源極∕汲極區503可具有介於約1E19cm-3 至約1E21cm-3 之範圍的雜質濃度（如摻質）。可於p型電晶體的源極∕汲極區503中佈植p型雜質如硼或銦。可於n型電晶體的源極∕汲極區503中佈植n型雜質如磷或砷。在一些實施例中，成長時可於原位（in-situ）摻雜磊晶源極∕汲極區。
接著，第17圖中，繪示出三維示意圖，層間介電質（interlayer dielectric, ILD）513形成於磊晶源極∕汲極區503之上。形成層間介電質513前，可於磊晶源極∕汲極區503之上形成接觸蝕刻停止層（contact etch stop layer, CESL，未繪示）。接觸蝕刻停止層在後續蝕刻製程中可作為蝕刻停止層，並可包括合適材料如氧化矽、氮化矽、氮氧化矽、前述之組合或類似物，且可利用合適的形成方法如化學氣相沉積、物理氣相沉積、前述之組合或類似方法形成接觸蝕刻停止層。層間介電質513形成於接觸蝕刻停止層之上及虛置金屬閘極堆疊419的兩側上的磊晶源極∕汲極區503之上。在一些實施例中，層間介電質513可包括介電材料如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass, PSG）、硼矽酸鹽玻璃（borosilicate glass, BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass, BPSG）、未摻雜矽酸鹽玻璃（undoped silicate glass, USG）或類似物，並可利用任何合適的方法如化學氣相沉積、電漿輔助化學氣相沉積、流動式化學氣相沉積或高密度電漿（high density plasma）沉積介電材料。接著，可平坦化層間介電質513，使其與虛置金屬閘極堆疊419的頂表面（繪示於第17圖中）實質上共表面，並露出虛置金屬閘極堆疊419的頂表面。在一實施例中，可利用如化學機械研磨平坦化層間介電質513以移除部分的層間介電質513，在其他實施例中，可使用其他平坦化技術如蝕刻。
第18A、18B與18C圖中，層間介電質513一旦形成於磊晶源極∕汲極區503之上且虛置金屬閘極堆疊419的頂表面一旦露出後，在一或多個蝕刻步驟中移除虛置金屬閘極電極412與虛置閘極硬遮罩層堆疊417（繪示於第10圖中）。蝕刻步驟對虛置金屬閘極電極412與虛置閘極氧化層401的材料可具有選擇性，蝕刻可為乾式或濕式蝕刻。蝕刻虛置金屬閘極電極412時，虛置閘極氧化層401可作為蝕刻停止層。移除虛置金屬閘極電極412後可接著蝕刻虛置閘極氧化層401。開口形成於被層間介電質513覆蓋的源極∕汲極區503間，而露出圖案化鰭片303的通道區。部分的間隔物層431沿著層間介電質513的側壁留下而形成側壁間隔物441。
第19A、19B與19C圖中，對鰭片303露出的通道區部分進行處理以移除第一半導體層205。於鰭片303的通道區部分中進行第一半導體層205（如SiGe層）的選擇性移除製程。在第一半導體205a與205b由SiGe所形成且第二半導體層207a與207b由Si所形成的一實施例中，可利用如n型場效電晶體SiGe選擇性移除製程移除第一半導體層205a與205b。在一些實施例中，選擇性移除製程可使用相對於矽以較快的速率選擇性地蝕刻矽鍺之蝕刻劑，如NH4 OH:H2 O2 :H2 O（氨-過氧化物混合物，ammonia peroxide mixture, APM）、H2 SO4 +H2 O2 （硫酸-過氧化物混合物，sulfuric acid peroxide, SPM）或類似物。可使用其他合適的製程與材料。此選擇性蝕刻製程移除了第一半導體層205a與205b（如SiGe層）。
再者，雖然並未特別說明，應能理解可於任一鰭片303的通道區中形成n型場效電晶體裝置，或可於任一鰭片303的通道區中形成p型場效電晶體裝置。雖然並未特別說明，也應能理解可於其中一鰭片303的通道區中形成n型場效電晶體裝置，並可於另一鰭片303的通道區中形成p型場效電晶體裝置。例如，在形成兩個n型場效電晶體裝置的一實施例中，被選擇性移除的第一半導體層205a與205b可包括SiGe，剩餘的第二半導體層207a與207b可包括Si，而源極∕汲極區503可包括碳化矽、磷化矽、摻磷碳化矽或類似物。在形成兩個p型場效電晶體裝置的另一實施例中，被選擇性移除的第一半導體層205a與205b可包括Si，剩餘的第二半導體層207a與207b可包括SiGe，而源極∕汲極區503包括SiGe與p型雜質如硼或銦。在形成兩個p型場效電晶體裝置的其他實施例中，被選擇性移除的第一半導體層205a與205b可包括SiGe，剩餘的第二半導體層207a與207b可包括Si，而源極∕汲極區503包括SiGe與p型雜質如硼或銦。
選擇性移除第一半導體層205a與205b後，鰭片303中留下了第二半導體層207a與207b，在此分別稱為第一奈米片堆疊407a與第二奈米片堆疊407b。使用奈米片結構的全繞式閘極電晶體裝置可為邏輯裝置（logic device）、靜態隨機存取記憶體（static random access memory, SRAM）裝置、輸出入裝置、靜電放電（electro-static discharge, ESD）裝置或被動元件（passive device）。在另一實施例中，蝕刻後，可留下淺溝槽隔離區313的上表面之下的最底層第一半導體層205a與205b（如SiGe層），其作為鰭片303a與303b之中的應力層（stress layer）以提供鰭片材料一定的應變（strain）或鬆弛（relaxation）。
在第一半導體層205a與205b（如SiGe層）由SiGe所形成且第二半導體層207a與207b（如Si層）由Si所形成的一實施例中，可利用Si移除製程移除第二半導體層207a與207b（如Si層）。在一些實施例中，移除製程可利用濕式蝕刻，其使用四甲基氫氧化銨（tetramethylammonium hydroxide, TMAH）溶液或類似溶液。可使用其他製程與材料。此蝕刻製程移除了第二半導體層207a與207b。因此，從鰭片303形成了第二奈米片405a與405b（未特別繪示）。
第20A、20B與20C圖中，第一閘極介電質521a與第二閘極介電質521b形成於第一奈米片407a與第二奈米片407b的露出部分之上及其移除虛置金屬閘極堆疊419所騰空（vacated）的空間中。在一實施例中，第一與第二閘極介電質521a與521b（因此共同稱為閘極介電質521）可包括一層界面介電質（interfacial dielectric），其上覆有高介電常數介電層。例如界面介電質可為氧化物或類似物，利用熱氧化、原子層沉積、化學氣相沉積或類似製程所形成。高介電常數介電層可具有高於約7.0的介電常數。高介電常數介電層可包括金屬氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb與前述之組合的矽化物。高介電常數介電層的形成方法可包括原子層沉積、化學氣相沉積、分子束沉積（molecular beam deposition, MBD）、類似方法或前述之組合。其他實施例可將閘極介電質521的其他材料納入考量，如不具有高介電常數的材料。如第20C圖中所繪示，閘極介電質521覆蓋了第19C圖中移除第一半導體層205而露出的奈米片407之表面與內間隔物410。
如第20B圖中所繪示，可形成第一與第二閘極介電質521a與521b使其各自具有不同的厚度。較厚的閘極介電質適合用於輸出入裝置中的奈米片。核心裝置（core device）可使用較薄的閘極介電質，其在相鄰的奈米片間具有較小的間距，可防止核心裝置因較大的電容而劣化（degradation）。在一實施例中，調整反應氣體流速、生成溫度或沉積閘極介電質期間的時間長度，決定第一與第二閘極介電質521a與521b的相對平均厚度。第二閘極介電質521b可具有第二閘極介電質厚度，其大於第一閘極介電質521a的第一閘極介電質厚度。第一閘極介電質521a的平均厚度可在約1nm至約5nm的範圍，而第二閘極介電質521b可在約2.5nm至約7nm的範圍。
也可形成第一與第二閘極介電質521a與521b使其具有不同的組成。例如，第一閘極介電質521a可包括SiO2 、SiON、Si3 N4 、HfOx 、LaOx 以及∕或AlOx ，而第二閘極介電質521b可包括不同比例的第一閘極介電質521a的SiO2 、SiON、Si3 N4 、HfOx 、LaOx 以及∕或AlOx 。
第21A、21B與21C圖中，金屬閘極結構525形成於閘極介電質521上以形成金屬閘極電極。金屬閘極結構525可為多層結構。例如，金屬閘極結構525可包括順應地形成於閘極介電質上的蓋層（capping layer）、順應地形成於蓋層上的一或多層功函數調整層（work function tuning layer），以及含金屬材料如金屬，形成於功函數調整層上並填充移除虛置金屬閘極堆疊419所騰空的空間。在一範例中，蓋層可包括利用原子層沉積、化學氣相沉積或類似製程於閘極介電質上形成的第一次層（sub-layer），由TiN或類似材料所形成，以及利用原子層沉積、化學氣相沉積或類似製程於第一次層上形成的第二次層，由TaN或類似材料所形成。功函數調整層可由TiAl、TiN或類似材料所形成，且可利用原子層沉積、化學氣相沉積或類似製程形成功函數調整層。含金屬材料可為鎢、鋁、鈷、銣、前述之組合或類似材料，且可利用化學氣相沉積、物理氣相沉積、類似製程或前述之組合形成含金屬材料。如第21C圖中所繪示，金屬閘極結構525填充了奈米片407間剩餘的空間其位於閘極介電質521圍繞的空腔（cavity）之中。接著，可進行平坦化製程如化學機械研磨以移除金屬閘極結構與閘極介電質過多的部分，其位於層間介電質513與515的頂表面之上，因而產生如第21A與21B圖中所繪示的結構。
第22至28B圖是根據另一實施例，繪示出形成三個水平全繞式閘極電晶體的示意圖，其彼此相鄰且相距較大的距離，且相對於彼此具有調整的閘極介電質厚度以及∕或組成、薄片厚度、薄片間距、薄片寬度與堆疊數量。
第22圖繪示出三個鰭片303a、303b與303c的示意圖，是從第5A或5B圖沿著第2A圖中的剖面B-B所繪示的剖面圖中的結構所圖案化。繪示於第22圖中的實施例與繪示於第6B圖中的實施例的差異在於第一交替層堆疊203a被圖案化而分別形成兩個鰭片303a與303c。第三鰭片303c的第一與第二半導體層205c與207c可具有與第一鰭片303a的第一及第二半導體層205a與207b實質上相同的數量與厚度，但可圖案化鰭片303a、303b與303c使其各具有不同的寬度。例如，在一實施例中，鰭片303a的寬度可在約4nm至約100nm的範圍，鰭片303b的寬度可在約4nm至約100nm的範圍，而鰭片303c的寬度可在約4nm至約100nm的範圍。鰭片303a、303b與303c的圖案化將決定鰭片在後續步驟中產生的奈米片之寬度（薄片寬度）。較大的薄片寬度（或Weff ，奈米片有效寬度）使更高速度性能得以實現。較小的薄片寬度則使低功率應用得以實現。鰭片303a、303b與303c將用以形成一或多個n型鰭狀場效電晶體以及∕或p型鰭狀場效電晶體的水平奈米片。雖然第22圖中繪示出三個鰭片（第一鰭片303a、第二鰭片303b與第三鰭片303c），應能理解可使用任何合適數量與型態的鰭片303。
第23圖繪示出利用以上第7B圖中所示的步驟形成淺溝槽隔離區313的示意圖，但其具有三個鰭片303而非兩個鰭片。第24圖繪示出利用以上第8B圖中所示的步驟凹蝕淺溝槽隔離區313的示意圖，但其具有三個鰭片303而非兩個鰭片。第25圖繪示出利用以上第10B圖中所示的步驟於第一、第二與第三鰭片303a、303b與303c之上形成虛置金屬閘極堆疊419的示意圖，但其具有三個鰭片303而非兩個鰭片。第26圖繪示出利用以上第19B圖中所示的步驟形成第一、第二與第三奈米片堆疊407a、407b與408c的示意圖，但其具有三個鰭片303而非兩個鰭片。應能理解第23至26圖中所繪示的中間步驟與以上第8B至19B圖中所繪示的步驟實質上相同，但其具有三個鰭片303而非兩個鰭片。此外，雖然第23至26圖中繪示出三個鰭片（第一鰭片303a、第二鰭片303b與第三鰭片303c），應能理解可使用任何合適數量與型態的鰭片。
第27圖中，第一、第二與第三閘極介電質521a、521b與521c分別形成於第一奈米片堆疊407a、第二奈米片堆疊407b與第三奈米片堆疊407c的露出部分之上，而第一、第二與第三閘極介電質521a、521b與521c（因此共同稱為閘極介電質521）可為界面介電質。其他實施例可將閘極介電質521的其他材料納入考量，如不具有高介電常數的材料。
可形成第一、第二與第三閘極介電質521a、521b與521c使其各自具有不同的厚度。較厚的閘極介電質適合用於輸出入裝置，而較薄的閘極介電質適合用於核心裝置。調整沉積閘極介電質期間的時間長度可決定第一、第二與第三閘極介電質521a、521b與521c的相對平均厚度。在一實施例中，第一閘極介電質521a的平均厚度可在約1nm至約5nm的範圍，第二閘極介電質521b的平均厚度可在約2.5nm至約7nm的範圍，而第三閘極介電質521c的平均厚度可在約1nm至約7nm的範圍。在一實施例中，為了以第三閘極介電質521c作為裝置的一部分而使其使用較低功率而具有較高的可靠度（reliability），第三閘極介電質521c的平均厚度實質上大於第一閘極介電質521a的平均厚度，並實質上小於二閘極介電質521b的平均厚度。
也可形成第一、第二與第三閘極介電質521a、521b與521c使其具有不同組成。例如第一閘極介電質521a可包括SiO2 、SiON、Si3 N4 、HfOx 、LaOx 以及∕或AlOx ，而第二閘極介電質521b與第三閘極介電質521c可包括不同比例的第一閘極介電質521a的SiO2 、SiON、Si3 N4 、HfOx 、LaOx 以及∕或AlOx 。
第28A圖中，利用以上第10B圖中所示的步驟於閘極介電質521上形成金屬閘極結構525，但其具有三個鰭片303而非兩個鰭片。第28B圖繪示出另一實施例，其中頂部的奈米片407c被移除而導致相對於第一奈米片堆疊407a，第三奈米片堆疊407c具有較少的奈米片。在其他實施例中，可從第一、第二與第三奈米片堆疊407a、407b與407c移除不同數量的奈米片。應能理解可在製程任何適宜的步驟中移除奈米片。例如，形成第26圖中所繪示的第三奈米片堆疊後，可利用適當的Si選擇性移除製程移除頂部的奈米片407c。減少第三奈米片堆疊407c的堆疊數量可使其用於裝置的一部份，其需要較低功率而具有較高的可靠度。此外，雖然第28A與28B圖中繪示出三個奈米片堆疊407a、408b與408c，應能理解可產生任何合適數量的奈米片堆疊。
以上揭露的實施例包括全繞式閘極電晶體的製造方法，可調整奈米片寬度、奈米片厚度、奈米片間距與堆疊數量。此奈米片結構的調整可用於單一晶圓上。這樣的設計彈性對電路性能與功率運用的設計最佳化提供廣泛的調整範圍。較大的奈米片寬度使更高速度性能得以實現，且較小的奈米片寬度以及∕或減少堆疊數量則可使低功率應用得以實現。增加薄片間距（堆疊中相鄰的奈米片之間的距離）使較厚的輸出入閘極氧化物得以用於實現奈米片結構輸出入裝置。可製造使用奈米片結構的全繞式閘極電晶體使其彼此相鄰或彼此分離開，並可將其用於邏輯裝置、靜態隨機存取記憶體裝置、輸出入裝置、靜電放電裝置或被動元件。
根據一實施例，半導體裝置的製造方法包括：於基板上形成第一交替層堆疊，其中形成第一交替層堆疊的步驟包括於基板上交替沉積第一半導體材料的第一層與第二半導體材料的第二層，第二半導體材料與第一半導體材料不同；於基板上形成第二交替層堆疊，距第一交替層堆疊第一距離，其中形成第二交替層堆疊的步驟包括於基板上交替沉積第一半導體材料的第一層與第二半導體材料的第二層，且其中相對該第一交替層堆疊的第一層，第二交替層堆疊的第一層具有較大的厚度；從第一交替層堆疊建構第一奈米片堆疊且從第二交替層堆疊建構第二奈米片堆疊，其中建構第一與第二奈米片堆疊的步驟包括：從第一交替層堆疊圖案化第一鰭片，且從第二交替層堆疊圖案化第二鰭片；以及從第一交替層堆疊移除第一層且從第二交替層堆疊移除第一層，使得第二交替層堆疊相鄰的剩餘層間之距離大於第一交替層堆疊相鄰的剩餘層間之距離；以及於第一奈米片堆疊之上形成第一閘極介電質，且於第二奈米片堆疊之上形成第二閘極介電質。在一實施例中，形成第一閘極介電質使其包括第一閘極介電質厚度，且形成第二閘極介電質使其包括第二閘極介電質厚度，第二閘極介電質厚度大於第一閘極介電質厚度。在一實施例中，形成第一與第二閘極介電質使其包括不同材料。在一實施例中，透過控制用於形成第一交替層堆疊的磊晶成長循環之數量，形成第一交替層堆疊使其包括第一數量的交替層；其中透過控制用於形成第二交替層堆疊的磊晶成長循環之數量，形成第二交替層堆疊使其包括第二數量的交替層；且其中第一數量與第二數量不同。在一實施例中，形成第二交替層堆疊的第二層使其相對於第一交替層堆疊的第二層具有較大的厚度。
根據另一實施例，半導體裝置的製造方法包括：於基板上的第一交替層堆疊中蝕刻凹口，其中第一交替層堆疊包括交替的第一層與第二層，第一層包括第一半導體材料而第二層包括第二半導體材料，第一半導體材料與第二半導體材料不同，其中第一交替層堆疊的第一層具有第一平均厚度，而第一交替層堆疊的第二層具有第二平均厚度，其中透過控制第一交替層堆疊的第一層與第二層的磊晶成長，決定第一平均厚度與第二平均厚度；於第一交替層堆疊中形成第二交替層堆疊，其中形成第二交替層堆疊的步驟包括於凹口中沉積交替的第一層與第二層，第一層包括第一半導體材料，而第二層包括第二半導體材料，其中第二交替層堆疊的第一層具有第三平均厚度，而第二交替層堆疊的第二層具有第四平均厚度，第三平均厚度與第一平均厚度不同，且第四平均厚度與第二平均厚度不同，其中透過控制第二交替層堆疊的第一層與第二層的磊晶成長，決定第三平均厚度與第四平均厚度；從第一交替層堆疊建構第一奈米片堆疊，且從第二交替層堆疊建構第二奈米片堆疊，其中建構第一與第二奈米片堆疊的步驟包括：從第一交替層堆疊圖案化第一鰭片，且從第二交替層堆疊圖案化第二鰭片；以及從第一交替層堆疊與第二交替層堆疊移除第一層與第二層的其中之一；以及於第一奈米片堆疊之上形成第一閘極介電質，且於第二奈米片堆疊之上形成第二閘極介電質。在一實施例中，形成第一奈米片堆疊使其具有第一寬度，且形成第二奈米片堆疊使其具有第二寬度，第一寬度與第二寬度不同。在一實施例中，形成第一與第二奈米片堆疊使其包括不同數量的奈米片。在一實施例中，形成第二交替層堆疊的步驟更包括：於凹口的側壁上形成間隔物；以及於間隔物的側壁間的凹口中交替沉積第一半導體材料的第一層與第二半導體材料的第二層。在一實施例中，圖案化第二鰭片的步驟包括將間隔物蝕刻掉。在一實施例中，形成第二交替層堆疊的步驟更包括於凹口的底部與側壁上順應地交替沉積第一半導體材料的第一層與第二半導體材料的第二層。在一實施例中，圖案化第二鰭片的步驟包括將第二交替層堆疊的外部部份蝕刻掉，使其剩餘部分僅包括交替的第一半導體材料之水平第一層與第二半導體材料之水平第二層。
根據更另一實施例，半導體裝置包括：第一奈米片堆疊，其中第一閘極介電質圍繞第一奈米片堆疊的每個奈米片，其中第一奈米片堆疊的相鄰奈米片以第一平均間距彼此隔離；以及第二奈米片堆疊，距第一奈米片堆疊第一距離，其中第二閘極介電質圍繞第二奈米片堆疊的每個奈米片，其中第二奈米片堆疊的相鄰奈米片以第二平均間距彼此隔離，其中第二平均間距大於第一平均間距。在一實施例中，第一閘極介電質具有第一平均厚度，而第二閘極介電質具有第二平均厚度，第二平均厚度大於第一平均厚度。在一實施例中，第一與第二奈米片堆疊包括不同數量的奈米片。在一實施例中，第一奈米片堆疊的奈米片具有第一平均厚度，而第二奈米片堆疊的奈米片具有第二平均厚度，第二平均厚度大於第一平均厚度。在一實施例中，第一奈米片堆疊包括部份的邏輯元件，而第二奈米片堆疊包括部份的輸出入裝置。在一實施例中，第三奈米片堆疊距第一奈米片堆疊第二距離，第二距離小於第一距離，且其中第一奈米片堆疊具有第一寬度，而第三奈米片堆疊具有第二寬度，第一寬度大於第二寬度。在一實施例中，第三奈米片堆疊距第一奈米片堆疊第二距離，第二距離小於第一距離，其中第三閘極介電質圍繞第三奈米片堆疊的每個奈米片，其中第一閘極介電質具有第一平均厚度，第二閘極介電質具有第二平均厚度，第三閘極介電質具有第三平均厚度，第三平均厚度大於第一平均厚度，第三平均厚度小於第二平均厚度。在一實施例中，第三奈米片堆疊距第一奈米片堆疊第二距離，第二距離小於第一距離，且其中第一與第三奈米片堆疊包括不同數量的奈米片。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
100:原材料 101:基板 103:佈植製程 105:凹口 200:多層結構 203a:第一交替層堆疊 203b:第二交替層堆疊 205a、205b、205c:第一半導體層 207a、207b、207c:第二半導體層 209:硬遮罩層 301、305:溝槽 303a:第一鰭片 303b:第二鰭片 303c:第三鰭片 310、311:間隔物 313:淺溝槽隔離區 401:虛置閘極氧化層 407a:第一奈米片堆疊 407b:第二奈米片堆疊 407c:第三奈米片堆疊 409:介電材料 410:內間隔物 411:虛置金屬層 412:虛置金屬閘極電極 413:第一硬遮罩層 415:第二硬遮罩層 417:虛置閘極硬遮罩層堆疊 419:虛置閘極金屬堆疊 431:間隔物層 441:側壁間隔物 503:源極∕汲極區 513:層間介電質 521a:第一閘極介電質 521b:第二閘極介電質 521c:第三閘極介電質 525:金屬閘極結構 B-B、C-C:剖面
以下將配合所附圖式詳述本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本發明實施例的特徵。 第1圖、第2A至2B圖、第3圖、第4A至4D圖、第5A至5B圖、第6A至6B圖、第7A至7B圖、第8A至8B圖、第9圖、第10A至10B圖、第11圖、第12A至12C圖、第13至17圖、第18A至18C圖、第19A至19C圖、第20A至20C圖、第21A至21C圖是根據一些實施例，繪示出形成半導體裝置的中間階段之各種剖面圖與透視圖，其是透過形成並圖案化半導體材料的兩交替層堆疊所形成。 第22至27圖、第28A至28B圖是根據一些實施例，繪示出圖案化半導體材料的三個交替層堆疊的中間階段之各種剖面圖。
101:基板
207b:半導體層
303a:第一鰭片
303b:第二鰭片
313:淺溝槽隔離區
407a:第一奈米片堆疊
521a:第一閘極介電質
521b:第二閘極介電質

Claims (9)

  1. 一種半導體裝置的製造方法，包括：於一基板上形成一第一交替層(alternating layer)堆疊，其中形成該第一交替層堆疊的步驟包括於該基板上交替沉積一第一半導體材料的多個第一層與一第二半導體材料的多個第二層，該第二半導體材料與該第一半導體材料不同；於該基板上形成一第二交替層堆疊，距該第一交替層堆疊一第一距離，其中形成該第二交替層堆疊的步驟包括於該基板上交替沉積該第一半導體材料的多個第一層與該第二半導體材料的多個第二層，且其中相對於該第一交替層堆疊的該些第一層，該第二交替層堆疊的該些第一層具有較大的厚度；從該第一交替層堆疊建構一第一奈米片(nanosheet)堆疊且從該第二交替層堆疊建構一第二奈米片堆疊，其中建構該第一與該第二奈米片堆疊的步驟包括：從該第一交替層堆疊圖案化一第一鰭片(fin)，且從該第二交替層堆疊圖案化一第二鰭片；以及從該第一交替層堆疊移除該些第一層且從該第二交替層堆疊移除該些第一層，使得該第二交替層堆疊相鄰的剩餘層間之距離大於該第一交替層堆疊相鄰的剩餘層間之距離；以及於該第一奈米片堆疊之上形成一第一閘極介電質，且於該第二奈米片堆疊之上形成一第二閘極介電質，其中形成該第一閘極介電質使其包括一第一閘極介電質厚度，且形成該第二閘極介電質使其包括一第二閘極介電質厚度，該第二閘極介電質厚度大於該第一閘極介電質厚度。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中透過控制用於形成該第一交替層堆疊的磊晶成長(epitaxial growth)循環之數量，形 成該第一交替層堆疊使其包括一第一數量的交替層；其中透過控制用於形成該第二交替層堆疊的磊晶成長循環之數量，形成該第二交替層堆疊使其包括一第二數量的交替層；且其中該第一數量與該第二數量不同。
  3. 如申請專利範圍第1或2項中任一項所述之半導體裝置的製造方法，其中形成該第二交替層堆疊的該些第二層使其相對於該第一交替層堆疊的該些第二層具有較大的厚度。
  4. 一種半導體裝置的製造方法，包括：於一基板上的一第一交替層堆疊中蝕刻一凹口(recess)，其中該第一交替層堆疊包括交替的多個第一層與多個第二層，該些第一層包括一第一半導體材料而該些第二層包括一第二半導體材料，該第一半導體材料與該第二半導體材料不同，其中該第一交替層堆疊的該些第一層具有一第一平均厚度，而該第一交替層堆疊的該些第二層具有一第二平均厚度，其中透過控制該第一交替層堆疊的該些第一層與該些第二層的磊晶成長，決定該第一平均厚度與該第二平均厚度；於該第一交替層堆疊中形成一第二交替層堆疊，其中形成該第二交替層堆疊的步驟包括於該凹口中沉積交替的多個第一層與多個第二層，該些第一層包括該第一半導體材料，而該些第二層包括該第二半導體材料，其中該第二交替層堆疊的該些第一層具有一第三平均厚度，而該第二交替層堆疊的該些第二層具有一第四平均厚度，該第三平均厚度與該第一平均厚度不同，且該第四平均厚度與該第二平均厚度不同，其中透過控制該第二交替層堆疊的該些第一層與該些第二層的磊晶成長，決定該第三平均厚度與該第四平均厚度；從該第一交替層堆疊建構一第一奈米片堆疊，且從該第二交替層堆疊建構一第二奈米片堆疊，其中建構該第一與該第二奈米片堆疊的步驟包括：從該第一交替層堆疊圖案化一第一鰭片，且從該第二交替層堆疊圖案化一 第二鰭片；以及從該第一交替層堆疊與該第二交替層堆疊移除該些第一層與該些第二層的其中之一；以及於該第一奈米片堆疊之上形成一第一閘極介電質，且於該第二奈米片堆疊之上形成一第二閘極介電質。
  5. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中形成該第一奈米片堆疊使其具有一第一寬度，且形成該第二奈米片堆疊使其具有一第二寬度，該第一寬度與該第二寬度不同。
  6. 如申請專利範圍第4或5項所述之半導體裝置的製造方法，其中形成該第二交替層堆疊的步驟更包括：於該凹口的多個側壁上形成一間隔物(spacer)；以及於該間隔物的多個側壁間的該凹口中交替沉積該第一半導體材料的多個第一層與該第二半導體材料的多個第二層。
  7. 一種半導體裝置，包括一第一奈米片堆疊，其中一第一閘極介電質圍繞該第一奈米片堆疊的每個奈米片，其中該第一奈米片堆疊的相鄰奈米片以一第一平均間距(spacing)彼此隔離；以及一第二奈米片堆疊，距該第一奈米片堆疊一第一距離，其中一第二閘極介電質圍繞該第二奈米片堆疊的每個奈米片，其中該第二奈米片堆疊的相鄰奈米片以一第二平均間距彼此隔離，其中該第二平均間距大於該第一平均間距，其中該第一閘極介電質具有一第一平均厚度，該第二閘極介電質具有一第二平均厚度，且該第二平均厚度大於該第一平均厚度。
  8. 如申請專利範圍第7項所述之半導體裝置，其中一第三奈米片堆疊距該第一奈米片堆疊一第二距離，該第二距離小於該第一距離，該第一與該 第三奈米片堆疊包括不同數量的奈米片，且其中該第一奈米片堆疊具有一第一寬度，而該第三奈米片堆疊具有一第二寬度，該第一寬度大於該第二寬度。
  9. 如申請專利範圍第7項所述之半導體裝置，其中一第三奈米片堆疊距該第一奈米片堆疊一第二距離，該第二距離小於該第一距離，該第一與該第三奈米片堆疊包括不同數量的奈米片，其中一第三閘極介電質圍繞該第三奈米片堆疊的每個奈米片，其中該第三閘極介電質具有一第三平均厚度，該第三平均厚度大於該第一平均厚度，該第三平均厚度小於該第二平均厚度。
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