CN111244038A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN111244038A
CN111244038A CN201911194723.9A CN201911194723A CN111244038A CN 111244038 A CN111244038 A CN 111244038A CN 201911194723 A CN201911194723 A CN 201911194723A CN 111244038 A CN111244038 A CN 111244038A
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CN111244038B (zh
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吴显扬
林大钧
潘国华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开实施例提供一种半导体装置的制造方法及半导体装置，该半导体装置的制造方法包括：于基板上形成多个交替层堆叠；从多个交替层堆叠建构多个纳米片；且于多个纳米片之上形成多个栅极介电质。此方法能够调整纳米片的宽度、厚度、间距与堆叠数量，并可用于单一基板上。此设计弹性设计对电路性能与功率运用的设计最佳化提供广泛的调整范围。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明实施例涉及一种半导体装置的制造方法，特别涉及一种栅极结构的制造方法。
背景技术
半导体装置用于大量的电子装置之中，如电脑、手机以及其他装置。半导体装置包括形成于半导体晶圆(wafer)上的集成电路，于半导体晶圆之上沉积许多形态的薄膜材料，及图案化薄膜材料以形成集成电路。集成电路包括场效晶体管(field-effecttransistor,FET)如金属氧化物半导体晶体管。
半导体产业其中一个目标为不断地缩小单一场效晶体管的尺寸并增加其速度。为了达到这些目标而研究且实施鳍状场效晶体管(finFET)、多栅极晶体管(multiple gatetransistor)与全绕式栅极(gate all-around)晶体管。然而，随着不断地缩小尺寸，即便是这样的新装置结构仍会面临许多崭新的难题。
发明内容
本发明实施例提供一种半导体装置的制造方法，包括：于基板上形成第一交替层堆叠，其中形成第一交替层堆叠的步骤包括于基板上交替沉积第一半导体材料的第一层与第二半导体材料的第二层，第二半导体材料与第一半导体材料不同；于基板上形成第二交替层堆叠，距第一交替层堆叠第一距离，其中形成第二交替层堆叠的步骤包括于基板上交替沉积第一半导体材料的第一层与第二半导体材料的第二层，且其中相对该第一交替层堆叠的第一层，第二交替层堆叠的第一层具有较大的厚度；从第一交替层堆叠建构第一纳米片堆叠且从第二交替层堆叠建构第二纳米片堆叠，其中建构第一与第二纳米片堆叠的步骤包括：从第一交替层堆叠图案化第一鳍片，且从第二交替层堆叠图案化第二鳍片；以及从第一交替层堆叠移除第一层且从第二交替层堆叠移除第一层，使得第二交替层堆叠相邻的剩余层间的距离大于第一交替层堆叠相邻的剩余层间的距离；以及于第一纳米片堆叠之上形成第一栅极介电质，且于第二纳米片堆叠之上形成第二栅极介电质。
本发明实施例提供一种半导体装置的制造方法，包括：于基板上的第一交替层堆叠中蚀刻凹口，其中第一交替层堆叠包括交替的第一层与第二层，第一层包括第一半导体材料而第二层包括第二半导体材料，第一半导体材料与第二半导体材料不同，其中第一交替层堆叠的第一层具有第一平均厚度，而第一交替层堆叠的第二层具有第二平均厚度，其中通过控制第一交替层堆叠的第一层与第二层的外延成长，决定第一平均厚度与第二平均厚度；于第一交替层堆叠中形成第二交替层堆叠，其中形成第二交替层堆叠的步骤包括于凹口中沉积交替的第一层与第二层，第一层包括第一半导体材料，而第二层包括第二半导体材料，其中第二交替层堆叠的第一层具有第三平均厚度，而第二交替层堆叠的第二层具有第四平均厚度，第三平均厚度与第一平均厚度不同，且第四平均厚度与第二平均厚度不同，其中通过控制第二交替层堆叠的第一层与第二层的外延成长，决定第三平均厚度与第四平均厚度；从第一交替层堆叠建构第一纳米片堆叠，且从第二交替层堆叠建构第二纳米片堆叠，其中建构第一与第二纳米片堆叠的步骤包括：从第一交替层堆叠图案化第一鳍片，且从第二交替层堆叠图案化第二鳍片；以及从第一交替层堆叠与第二交替层堆叠移除第一层与第二层的其中之一；以及于第一纳米片堆叠之上形成第一栅极介电质，且于第二纳米片堆叠之上形成第二栅极介电质。
本发明实施例提供一种半导体装置，包括：第一纳米片堆叠，其中第一栅极介电质围绕第一纳米片堆叠的每个纳米片，其中第一纳米片堆叠的相邻纳米片以第一平均间距彼此隔离；以及第二纳米片堆叠，距第一纳米片堆叠第一距离，其中第二栅极介电质围绕第二纳米片堆叠的每个纳米片，其中第二纳米片堆叠的相邻纳米片以第二平均间距彼此隔离，其中第二平均间距大于第一平均间距。
附图说明
以下将配合说明书附图详述本发明实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制且仅用以说明例示。事实上，可任意地放大或缩小元件的尺寸，以清楚地表现出本发明实施例的特征。
图1至图21C是根据一些实施例，示出形成半导体装置的中间阶段的各种剖面图与透视图，其是通过形成并图案化半导体材料的两交替层堆叠所形成。
图22至图28B是根据一些实施例，示出图案化半导体材料的三个交替层堆叠的中间阶段的各种剖面图。
附图标记说明：
100～原材料
101～基板
103～布植制程
105～凹口
200～多层结构
203a～第一交替层堆叠
203b～第二交替层堆叠
205a、205b、205c～第一半导体层
207a、207b、207c～第二半导体层
209～硬遮罩层
301、305～沟槽
303a～第一鳍片
303b～第二鳍片
303c～第三鳍片
310、311～间隔物
313～浅沟槽隔离区
401～虚置栅极氧化层
407a～第一纳米片堆叠
407b～第二纳米片堆叠
407c～第三纳米片堆叠
409～介电材料
410～内间隔物
411～虚置金属层
412～虚置金属栅极电极
413～第一硬遮罩层
415～第二硬遮罩层
417～虚置栅极硬遮罩层堆叠
419～虚置栅极金属堆叠
431～间隔物层
441～侧壁间隔物
503～源极/漏极区
513～层间介电质
521a～第一栅极介电质
521b～第二栅极介电质
521c～第三栅极介电质
525～金属栅极结构
B-B、C-C～剖面
具体实施方式
以下公开提供了许多的实施例或范例，用于实施所提供的标的物的不同元件。各元件和其配置的具体范例描述如下，以简化本发明实施例的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明实施例可能在各种范例中重复参考数值以及/或字母。如此重复是为了简明和清楚的目的，而非用以表示所讨论的不同实施例及/或配置之间的关系。
再者，其中可能用到与空间相对用词，例如“在……下方”、“在……之下”、“下方的”、“在……之上”、“上方的”等类似用词，是为了便于描述附图中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。
图1至图21C示出形成两水平全绕式栅极晶体管彼此距一距离的示意图，其相对彼此具有调节的栅极介电质的厚度以及/或组成、薄片(sheet)厚度、薄片间距、薄片宽度及堆叠数量。图22至图28B示出形成三个水平全绕式栅极晶体管彼此距不同距离的示意图，其相对彼此具有调节的栅极介电质的厚度以及/或组成、薄片厚度、薄片间距、薄片宽度及堆叠数量。图1、图2A、图6A、图7A、图8A、图9、图10A、图11、图12A、图17、图18A、图19A、图20A与图21A为三维(three-dimensional,3D)示意图。
图2B、图3、图4A、图4B、图4C、图4D、图5A、图5B、图6B、图7B、图8B、图10B、图12B、图18B、图19B、图20B、图21B、图22、图23、图24、图25、图26、图27、图28A与图28B是沿着参考剖面B-B(示出于图2A、图6A、图12A与图18A中)所示出的剖面图。图12C、图13、图14、图15、图16、图18C、图19C、图20C与图21C是沿着参考剖面C-C(示出于图12A与图18A中)所示出的剖面图。
现在参照图1，此附图是根据一些实施例示出掺质(dopant)抗击穿布植(anti-punch-through implant,APT implant)至原材料(source material)100中的示意图。原材料100可为基板101的形式，例如可为半导体基板如硅基板、硅锗基板、锗基板、III-V族材料基板(如GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb以及/或GaInAsP；或前述的组合)或者是使用如具有高带间穿遂(band-to-band tunneling,BTBT)的其他半导体材料所形成的基板。基板101可为掺杂或未掺杂。可使用n型或p型杂质(impurity)掺杂基板101。在一些实施例中，基板101可为块状(bulk)半导体基板如为晶圆的块状硅基板、绝缘体上覆半导体(semiconductor-on-insulator,SOI)基板、多层或梯度(gradient)基板或类似基板。
进行第一布植制程103(如图1中箭头所表示)以布植第一掺质至基板101的第一源极区。在一实施例中，对于如抗击穿布植可布植第一掺质。然而，可利用任何合适的布植制程。
图2A是制造全绕式栅极晶体管时中间阶段的多层结构200的三维示意图。图2B是沿着图2A中的剖面B-B所示出的多层结构200的剖面图。图2A至图2B中，第一交替(alternating)层堆叠203a形成于基板101上。第一交替层堆叠203a包括第一半导体材料的第一半导体层205a(如SiGe层)与第二半导体材料的第二半导体层207a(如Si层)所交替的膜层。在一些实施例中，第一半导体层205a(如SiGe层)与第二半导体层207a(如Si层)的每层外延(epitaxially)生成于其下方层上。交替层堆叠203a可包括任何数量的第一半导体层205a(如SiGe层)与任何数量的第二半导体层207a(如Si层)。外延成长可使用化学气相沉积(chemical vapor deposition,CVD)、金属有机化学气相沉积(metal organic CVD,MOCVD)、分子束外延(molecular beam epitaxy,MBE)、液相外延(liquid phase epitaxy,LPE)、气相外延(vapor phase epitaxy,VPE)、超高真空化学气相沉积(ultrahigh vacuumCVD,UHVCVD)、类似制程或前述的组合。第一半导体层205a(如SiGe层)与任何数量的第二半导体层207a(如Si层)的每层可为IV族材料如Si、Ge、SiGe、SiGeSn、SiC或类似物；III-V族化合物材料如GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb、GaInAsP或类似物。
交替层堆叠203a可包括任何数量的第一半导体层205a(如SiGe层)与任何数量的第二半导体层207a(如Si层)。如图所示，例如，交替层堆叠203a具有5层第一半导体层205a(如SiGe层)与四层第二导体层207a(如Si层)。通过用于形成第一交替层堆叠的外延成长循环的数量，可分别调整第一半导体层205a(如SiGe层)与第二半导体层207a(如Si层)的数量。
图3示出图案化并蚀刻沟槽305至交替层堆叠203a中的示意图。可利用微影技术图案化交替层堆叠203a。一般而言，光刻胶材料(未示出)沉积于交替层堆叠203a之上。以辐射(如光)通过图案化光罩(reticle)照射光刻胶材料(曝光)，使曝露于能量的光刻胶材料的这些部分中发生反应。显影光刻胶材料以移除一部分的光刻胶材料，其中剩余的光刻胶材料保护下方材料在后续制程步骤中不受影响。
图案化后，如图3所示出，蚀刻沟槽305使其具有垂直轮廓(profile)。蚀刻制程可为干式蚀刻。蚀刻制程可包括反应离子蚀刻(reactive ion etch,RIE)、中子束蚀刻(neutral beam etch,NBE)、感应耦合等离子体(inductively coupled plasma,ICP)蚀刻、电容耦合等离子体(capacitively coupled plasma,CCP)蚀刻、离子束蚀刻(ion beametch,IBE)、类似蚀刻制程或前述的组合。蚀刻制程可为非等向性(anisotropic)。在一些实施例中，蚀刻制程可包括使用第一气体的等离子体，其包括四氟化碳(carbontetrafluoride,CF4)、六氟乙烷(hexafluoroethane,C2F6)、八氟丙烷(octafluoropropane,C3F8)、三氟甲烷(fluoroform,CHF3)、二氟甲烷(difluoromethane,CH2F2)、氟甲烷(fluoromethane,CH3F)、氟化碳(如CxFy，其中x可在1至5的范围，而y可在4至8的范围)、类似物或前述的组合。等离子体还可使用第二气体，其包括氮气(N2)、氢气(H2)、氧气(O2)、氩气(Ar)、氙气(Xe)、氦气(He)、一氧化碳(CO)、二氧化碳(CO2)、羰基硫(COS)、类似物或前述的组合。蚀刻制程中可视需要地供应惰性(inert)气体。沟槽305可接触基板101的顶表面，或可蚀刻沟槽305至低于基板101顶表面的深度。
图4A示出间隔物(spacer)层310形成于沟槽305的侧壁与底表面上及形成于交替层堆叠203a最高表面之上的实施例。可使用介电材料如氮化硅、碳氮氧化硅(siliconcarbon-oxynitride)或类似物形成间隔物层310。
图4B示出移除间隔物层310水平部分的示意图。在一实施例中，利用非等向性蚀刻制程移除装置水平部分之上的间隔物层310。由于间隔物层310在装置水平部分及沿着沟槽305的侧壁的厚度不同，留下沿着沟槽305侧壁的间隔物311，而露出沟槽305底表面与交替层堆叠203a的最高表面。
图4C示出于沟槽305中形成第二交替层堆叠203b的实施例。第二交替层堆叠203b包括第一半导体材料的第一半导体层205b(如SiGe层)与第二半导体材料的第二半导体层207b(如Si层)的交替膜层。在一些实施例中，第一半导体层205b(如SiGe层)与第二半导体层207b(如Si层)的每层外延生成于其下方层上。第二交替层堆叠203b可包括任何数量的第一半导体层205b(如SiGe层)与任何数量的第二半导体层207b(如Si层)。如图所示，例如，交替层堆叠203b具有四层第一半导体层205b(如SiGe层)与三层第二导体层207b(如Si层)。通过用于形成第二交替层堆叠203b的外延成长循环的数量，可分别调整第一半导体层205a(如SiGe层)与第二半导体层207a(如Si层)的数量。
图4D示出形成第二交替层堆叠203b的另一实施例。不同于图4A至图4C中所示出的实施例，图4D中所示出的实施例并不包含形成间隔物。第二交替层堆叠203b形成于沟槽305中，其具有第一半导体材料的第一半导体层205b(如SiGe层)与第二半导体材料的第二半导体层207b(如Si层)的交替膜层，于沟槽305的侧壁与底部顺应地形成。第一半导体层205b(如SiGe层)与第二半导体层207b(如Si层)的每层顺应地外延生成于其下方层上。
第一半导体层205a的平均厚度与第一半导体层205b的平均厚度可不相同，而第二半导体层207a的平均厚度与第二半导体层207b的平均厚度可不相同。膜层的相对平均厚度将决定装置的纳米片(nanosheet)间的薄片间距。较大的薄片间距可于纳米片上产生较厚的输出入(input-output,IO)栅极氧化物，其用于如输出入装置。在一实施例中，通过调节反应气体的流速、生成温度或各层外延成长期间的时间长度而控制膜层的外延成长，以决定第一半导体层205与第二半导体层207的相对平均厚度。相对于第一交替层堆叠203a的第一半导体层205a，第二交替层堆叠203b的第一半导体层205b可具有较大的厚度。相对于第一交替层堆叠203a的第一半导体层207a，第二交替层堆叠203b的第一半导体层207b可具有较大的厚度。第一半导体层205a的平均厚度可在约5nm至约30nm的范围，第二半导体层207a的平均厚度可在约3nm至约30nm的范围，第一半导体层205b的平均厚度可在约8nm至约40nm的范围，而第二半导体层207b的平均厚度可在约3nm至约40nm的范围。第一半导体层205a与第二半导体层207a的平均厚度比例可在约10:1至约1:6的范围。第一半导体层205b与第二半导体层207b的平均厚度比例可在约10:1至约1:5的范围。
在一些实施例中，第一半导体层205a与205b的材料与第二半导体层207a与207b的材料不同。例如，第一半导体层205a与205b可为SiGe层，而第二半导体层207a与207b可为Si层或SiC层。在另一实施例中，例如，第一半导体层205a与205b可为Si层或SiC层，而第二半导体层207a与207b可SiGe层。材料的差异可提供不同的应变(strain)以及/或可提供第一半导体层205a与205b及第二半导体层207a与207b间的蚀刻选择性，由以下内容将可清楚看出。
图5A与图5B示出具有预期高度以及/或数量的膜层的第一与第二交替层堆叠203a与203b的实施例，将沉积硬遮罩层209。示出于图5A中的实施例从以上示出于图4C中的实施例接着进行，而示出于图5B中的实施例从以上示出于图4D中的实施例接着进行。如图5A与图5B中所示出，硬遮罩层209可沉积于交替层堆叠203a与203b的最高表面之上。可利用沉积制程于沉积腔中形成硬遮罩层209，或可利用任何其他合适的制程于第一与第二交替层堆叠203a与203b之上形成硬遮罩层209。硬遮罩209可包括次膜层(sublayer)如垫(pad)氧化层与上方的垫氮化层。垫氧化层可为包括氧化硅的薄膜，可利用如热氧化(thermaloxidation)制程形成垫氧化层。垫氧化层可作为第一与第二交替层堆叠203a与203b及上方的垫氮化层之间的粘着层(adhesion layer)。在一些实施例中，垫氮化层由氮化硅、氮氧化硅、碳氮化硅、类似物或前述的组合所形成，并可利用如低压化学气相沉积(low pressureCVD,LPCVD)或等离子体辅助化学气相沉积(plasma enhanced CVD,PECVD)形成垫氮化层。
图6A为多层结构200的三维示意图，而图6B为沿着图6A中的剖面B-B所示出的多层结构200的剖面图。图6A与图6B示出的实施例是在硬遮罩层209已沉积于多层结构200的顶表面上后(如图5A与图5B中所示出)，进行图案化制程以于多层结构200中形成沟槽301。在一些实施例中，利用微影技术图案化硬遮罩层209。一般而言，光刻胶材料(未示出)沉积于硬遮罩209之上。通过图案化的光罩照射辐射(如光)于光刻胶材料，使光刻胶材料曝露于能量的这些部分中发生反应。显影光刻胶材料以移除一部分的光刻胶材料，其中剩余光刻胶材料保护下方的材料在后续制程步骤中不受影响，后续制程步骤如蚀刻。
图6A与图6B中，对多层结构200进行图案化制程以形成沟槽301后，交替层堆叠203的剩余区域与下方的基板101形成了鳍片(fin)，如第一鳍片303a与第二鳍片303b(共同称为鳍片303)。如图6A与图6B中所示，鳍片303包括部分的交替层堆叠203a与203b(如部分的第一半导体层205a与205b(SiGe层)与部分的第二半导体层207a与207b(Si层))及部分的基板101。如图4A至图4C与图5A所示出，在第二交替层堆叠203b形成于被间隔物311覆盖的侧壁之间的实施例中，蚀刻第二鳍片303b也移除了间隔物311。如以上图4D与图5B中所示，在第二交替层堆叠203b顺应地(conformally)形成于沟槽305的侧壁与底部上的实施例中，蚀刻第二鳍片303b移除了非水平的部分的第一半导体层205c与第二半导体层207c。如以下将更详细地讨论，鳍片303将用以形成一或多个n型鳍状场效晶体管以及/或p型鳍状场效晶体管的水平纳米片。尽管图2B示出了两个鳍片(第一鳍片303a与第二鳍片303b)，应能理解可使用任何合适数量与形态的鳍片。
可图案化鳍片303a与303b，使其具有介于4nm至100nm的不同宽度。例如，在一实施例中，鳍片303a的宽度可在约4nm至约100nm的范围，而鳍片303b的宽度可在约4nm至约100nm的范围。鳍片303a的宽度与鳍片303b的宽度的比例可在约25:1至约1:25的范围。图案化鳍片303将决定后续步骤中所形成的纳米片的宽度(薄片宽度)。较大的薄片宽度(或Weff，纳米片有效宽度)使更高速度性能得以实现。较小的薄片宽度则使低功率应用(lowerpower application)得以实现。
根据一些实施例，图7A与图7B示出形成浅沟槽隔离(shallow trench isolation,STI)区313的示意图。图7A与图7B中，介电绝缘材料沉积邻近于鳍片303a与303b以形成浅沟槽隔离区313。浅沟槽隔离区313可由合适的介电材料所形成，如氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(fluoride-doped silicate glass,FSG)、低介电常数介电质如掺碳氧化物、极(extremely)低介电常数介电质如多孔(porous)掺碳二氧化硅、聚合物如聚酰亚胺(polyimide)、类似物或前述的组合。浅沟槽隔离区313可包括衬层(liner，未示出)与衬层之上的介电绝缘材料。可形成衬层为顺应层(conformal layer)，其水平部分与垂直部分具有彼此接近的厚度。在一些实施例中，利用制程如化学气相沉积、流动式(flowable)化学气相沉积或旋转涂布玻璃(spin-on glass)制程形成浅沟槽隔离区313，但可使用任何可接受的制程。接着，可对浅沟槽隔离区313进行一或多种硬遮罩移除制程以移除硬遮罩209，并移除浅沟槽隔离区313于鳍片303顶表面之上延伸的部分，可利用如化学机械研磨(chemicalmechanical polishing,CMP)蚀刻制程或类似制程进行移除制程。
图8A与图8B中，凹蚀(recessing)浅沟槽隔离区313以露出鳍片303的侧壁。在一实施例中，利用一或多种选择性蚀刻制程凹蚀浅沟槽隔离区313。交替层堆叠203a与203b的高度决定了凹口(recess)的深度。在一实施例中，凹口延伸至一深度，使最底层的第一半导体层205a与205b露出。或者，于浅沟槽隔离区313的上表面之下可留下最底层的第一半导体层205a与205b(如SiGe层)。
参照图9，虚置(dummy)栅极氧化层401形成于露出的鳍片303之上。在一些实施例中，可利用热氧化、化学气相沉积、溅射(sputtering)或本发明所属技术领域中熟知而用于形成虚置栅极氧化层104的任何其他方法形成虚置栅极氧化层401。在一些实施例中，虚置栅极氧化层401可由与浅沟槽隔离区313相同的材料所形成。在其他实施例中，虚置栅极氧化层可由一或多种合适的介电材料所形成，如氧化硅、氮化硅、低介电常数介电质如掺碳氧化物、极低介电常数介电质如多孔掺碳二氧化硅、聚合物如聚酰亚胺、类似物或前述的组合。在其他实施例中，虚置栅极氧化层401包括具有高介电常数(k值，如大于3.9)的介电材料。材料可包括氮化硅、氮氧化物、金属氧化物如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx、类似物或前述的组合及多层。
参照图10A与图10B，形成虚置栅极金属堆叠419。虚置金属层411沉积于虚置栅极氧化层401(示出于图9中)之上。在一实施例中，虚置金属层411为导电材料且可选自于下列的群组，包括：多晶硅(polycrystalline-silicon,poly-Si)、多晶硅锗(poly-crystallinesilicon-germanium,poly-SiGe)、金属氮化物、金属硅化物、金属氧化物与金属。在一实施例中，可利用物理气相沉积(physical vapor deposition,PVD)、化学气相沉积、溅射沉积或本发明所属技术领域中熟知而用于沉积导电材料的其他技术沉积虚置金属层411。可使用其他导电或非导电材料。沉积虚置金属层411之后可平坦化其顶表面。
可利用制程如化学气相沉积或旋转涂布玻璃制程，于虚置金属层411之上沉积第一硬遮罩层413，但可利用任何可接受的制程。在一实施例中，第一硬遮罩层413可为氧化层(如氧化硅)。接着利用制程如化学气相沉积或旋转涂布玻璃制程，于第一硬遮罩层413之上沉积第二硬遮罩层415，但可利用任何可接受的制程。图案化第一硬遮罩层413与第二硬遮罩层415以于虚置金属层411之上形成虚置栅极硬遮罩层堆叠417。在一实施例中，使用虚置栅极硬遮罩层堆叠417进行多晶硅蚀刻及虚置氧化物移除制程，以图案化虚置金属层411与虚置栅极氧化层401。图案化时，从鳍片303的源极/漏极区移除部分的虚置金属层411与部分的虚置氧化层401，而在鳍片303的通道区之上留下部分的虚置金属层411与部分的虚置氧化层401以形成虚置金属栅极电极412。虚置金属栅极电极412包括图案化的虚置金属层411与设置于图案化的虚置金属层411之下的图案化的虚置栅极氧化层401。虚置金属栅极电极412与虚置栅极硬遮罩层堆叠417共同形成虚置金属栅极堆叠419。
虚置金属栅极堆叠419将用以从鳍片303的露出部分定义及形成源极/漏极区。接着将移除虚置金属栅极堆叠419，以进行制程从鳍片303的露出部分(鳍片303的中间部分)定义及形成通道区，如以下所述。
现在参照图11，间隔物层431沉积于虚置金属栅极堆叠419、鳍片303与浅沟槽隔离区313的上表面之上。在一实施例中，间隔物层431由氮化硅所形成并可具有单一层结构。在其他实施例中，间隔物层431可具有包括多个层的复合结构。例如，氮化硅层可形成于氧化硅层之上。在一实施例中，间隔物层431可顺应地形成于鳍片303的外延源极/漏极区、虚置金属栅极堆叠419的侧壁与上表面两者及浅沟槽隔离区313的上表面上。在一实施例中，可利用原子层沉积(atomic layer deposition,ALD)、化学气相沉积、类似制程或前述的组合形成间隔物层431。
接着，图12A、图12B与图12C示出进行非等向性蚀刻制程的示意图，其移除了部分的间隔物层431与部分的鳍片303(如303a与303b)。可使用虚置金属栅极堆叠419作为蚀刻遮罩，进行非等向性蚀刻制程。在一些实施例中，非等向性蚀刻后，间隔物431的侧壁因非等向性蚀刻而与鳍片303各自的侧壁对准(aligned)。图12C是沿着图12A中的剖面C-C所示出的示意图，剖面C-C通过鳍片303b并垂直于虚置金属栅极堆叠419。以303b作为范例，沿着剖面C-C所示出的示意图代表在所有鳍片303上进行的制程与结构。如图12C中所示出，非等向性蚀刻也可蚀刻凹口105至鳍片303其中一侧上的基板101的上表面中。
接着，图13中，是沿着图12A中剖面C-C所示出的示意图，进行侧向(lateral)选择性蚀刻制程以凹蚀露出的第一半导体材料。可使用对第一半导体材料具选择性的蚀刻剂进行侧向选择性蚀刻制程，如以下图19A、图19B与图19C的讨论中所述。在图13的范例中，第一半导体层205由第一半导体材料(如SiGe)所形成，因此，侧向选择性蚀刻凹蚀了第一半导体层205。
接着，图14中，是沿着图12A中剖面C-C所示出的示意图，形成介电材料409以填充移除第一半导体材料而留下的空间，留下的空间是从以上参照图13所讨论的第一半导体层205的露出部分移除第一半导体材料而产生的。介电材料409可为低介电常数介电材料，如SiO2、SiN、SiCN或SiOCN，并可利用合适的沉积方法如原子层沉积形成介电材料409。
接着，图15中，是沿着图12A中剖面C-C所示出的示意图，沉积介电材料409后，可进行非等向性蚀刻制程以修整(trim)沉积的介电材料409，使得仅有部分的沉积介电材料409留下，其填充了从第一半导体层205移除第一半导体材料而留下的空间。修整制程后，沉积的介电材料409的剩余部分形成了内(inner)间隔物410。内间隔物410用以隔离金属栅极与形成于后续制程中的源极/漏极区。在图15的范例中，内间隔物410的侧壁与第二半导体层207的侧壁对准。
接着，图16中，是沿着图12A中剖面C-C所示出的示意图，源极/漏极区503形成于基板101的凹口105中。于凹口105中外延生成材料而形成了源极/漏极区503，可利用合适的方法如金属有机化学气相沉积、分子束外延、液相外延、气相外延、选择性外延成长(selective epitaxial growth,SEG)、类似方法或前述的组合形成源极/漏极区503。外延源极/漏极区503填充了相邻的鳍片303之间的空间。外延源极/漏极区503可具有从鳍片303表面抬升(raised)的表面并具有刻面(facet)。在一些实施例中，相邻的源极/漏极区503可合并形成连续的外延源极/漏极区133。如以下图17中所示，相邻的源极/漏极区503并未合并而保留各自的源极/漏极区503。可根据所形成的装置形态调整源极/漏极区133的材料。在一些实施例中，所制得的全绕式栅极场效晶体管为n型鳍状场效晶体管，而源极/漏极区503包括碳化硅(SiC)、磷化硅(SiP)、掺磷碳化硅(SiCP)或类似物。在一些实施例中，所制得的全绕式栅极场效晶体管为p型鳍状场效晶体管，而源极/漏极区503包括SiGe，p型杂质如硼或铟。
可使用掺质布植外延源极/漏极区503并接着进行退火制程。布植制程可包括形成并图案化遮罩如光刻胶，以覆盖在布植制程欲保护的全绕式栅极场效晶体管装置的区域。源极/漏极区503可具有介于约1E19cm-3至约1E21cm-3的范围的杂质浓度(如掺质)。可于p型晶体管的源极/漏极区503中布植p型杂质如硼或铟。可于n型晶体管的源极/漏极区503中布植n型杂质如磷或砷。在一些实施例中，成长时可于原位(in-situ)掺杂外延源极/漏极区。
接着，图17中，示出三维示意图，层间介电质(interlayer dielectric,ILD)513形成于外延源极/漏极区503之上。形成层间介电质513前，可于外延源极/漏极区503之上形成接触蚀刻停止层(contact etch stop layer,CESL，未示出)。接触蚀刻停止层在后续蚀刻制程中可作为蚀刻停止层，并可包括合适材料如氧化硅、氮化硅、氮氧化硅、前述的组合或类似物，且可利用合适的形成方法如化学气相沉积、物理气相沉积、前述的组合或类似方法形成接触蚀刻停止层。层间介电质513形成于接触蚀刻停止层之上及虚置金属栅极堆叠419的两侧上的外延源极/漏极区503之上。在一些实施例中，层间介电质513可包括介电材料如氧化硅、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicateglass,BSG)、掺硼磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)、未掺杂硅酸盐玻璃(undoped silicate glass,USG)或类似物，并可利用任何合适的方法如化学气相沉积、等离子体辅助化学气相沉积、流动式化学气相沉积或高密度等离子体(high densityplasma)沉积介电材料。接着，可平坦化层间介电质513，使其与虚置金属栅极堆叠419的顶表面(示出于图17中)实质上共表面，并露出虚置金属栅极堆叠419的顶表面。在一实施例中，可利用如化学机械研磨平坦化层间介电质513以移除部分的层间介电质513，在其他实施例中，可使用其他平坦化技术如蚀刻。
图18A、图18B与图18C中，层间介电质513一旦形成于外延源极/漏极区503之上且虚置金属栅极堆叠419的顶表面一旦露出后，在一或多个蚀刻步骤中移除虚置金属栅极电极412与虚置栅极硬遮罩层堆叠417(示出于图10中)。蚀刻步骤对虚置金属栅极电极412与虚置栅极氧化层401的材料可具有选择性，蚀刻可为干式或湿式蚀刻。蚀刻虚置金属栅极电极412时，虚置栅极氧化层401可作为蚀刻停止层。移除虚置金属栅极电极412后可接着蚀刻虚置栅极氧化层401。开口形成于被层间介电质513覆盖的源极/漏极区503间，而露出图案化鳍片303的通道区。部分的间隔物层431沿着层间介电质513的侧壁留下而形成侧壁间隔物441。
图19A、图19B与图19C中，对鳍片303露出的通道区部分进行处理以移除第一半导体层205。于鳍片303的通道区部分中进行第一半导体层205(如SiGe层)的选择性移除制程。在第一半导体205a与205b由SiGe所形成且第二半导体层207a与207b由Si所形成的一实施例中，可利用如n型场效晶体管SiGe选择性移除制程移除第一半导体层205a与205b。在一些实施例中，选择性移除制程可使用相对于硅以较快的速率选择性地蚀刻硅锗的蚀刻剂，如NH4OH:H2O2:H2O(氨-过氧化物混合物，ammonia peroxide mixture,APM)、H2SO4+H2O2(硫酸-过氧化物混合物，sulfuric acid peroxide,SPM)或类似物。可使用其他合适的制程与材料。此选择性蚀刻制程移除了第一半导体层205a与205b(如SiGe层)。
再者，虽然并未特别说明，应能理解可于任一鳍片303的通道区中形成n型场效晶体管装置，或可于任一鳍片303的通道区中形成p型场效晶体管装置。虽然并未特别说明，也应能理解可于其中一鳍片303的通道区中形成n型场效晶体管装置，并可于另一鳍片303的通道区中形成p型场效晶体管装置。例如，在形成两个n型场效晶体管装置的一实施例中，被选择性移除的第一半导体层205a与205b可包括SiGe，剩余的第二半导体层207a与207b可包括Si，而源极/漏极区503可包括碳化硅、磷化硅、掺磷碳化硅或类似物。在形成两个p型场效晶体管装置的另一实施例中，被选择性移除的第一半导体层205a与205b可包括Si，剩余的第二半导体层207a与207b可包括SiGe，而源极/漏极区503包括SiGe与p型杂质如硼或铟。在形成两个p型场效晶体管装置的其他实施例中，被选择性移除的第一半导体层205a与205b可包括SiGe，剩余的第二半导体层207a与207b可包括Si，而源极/漏极区503包括SiGe与p型杂质如硼或铟。
选择性移除第一半导体层205a与205b后，鳍片303中留下了第二半导体层207a与207b，在此分别称为第一纳米片堆叠407a与第二纳米片堆叠407b。使用纳米片结构的全绕式栅极晶体管装置可为逻辑装置(logic device)、静态随机存取存储器(static randomaccess memory,SRAM)装置、输出入装置、静电放电(electro-static discharge,ESD)装置或无源元件(passive device)。在另一实施例中，蚀刻后，可留下浅沟槽隔离区313的上表面之下的最底层第一半导体层205a与205b(如SiGe层)，其作为鳍片303a与303b之中的应力层(stress layer)以提供鳍片材料一定的应变(strain)或松弛(relaxation)。
在第一半导体层205a与205b(如SiGe层)由SiGe所形成且第二半导体层207a与207b(如Si层)由Si所形成的一实施例中，可利用Si移除制程移除第二半导体层207a与207b(如Si层)。在一些实施例中，移除制程可利用湿式蚀刻，其使用四甲基氢氧化铵(tetramethylammonium hydroxide,TMAH)溶液或类似溶液。可使用其他制程与材料。此蚀刻制程移除了第二半导体层207a与207b。因此，从鳍片303形成了第二纳米片405a与405b(未特别示出)。
图20A、图20B与图20C中，第一栅极介电质521a与第二栅极介电质521b形成于第一纳米片407a与第二纳米片407b的露出部分之上及其移除虚置金属栅极堆叠419所腾空(vacated)的空间中。在一实施例中，第一与第二栅极介电质521a与521b(因此共同称为栅极介电质521)可包括一层界面介电质(interfacial dielectric)，其上覆有高介电常数介电层。例如界面介电质可为氧化物或类似物，利用热氧化、原子层沉积、化学气相沉积或类似制程所形成。高介电常数介电层可具有高于约7.0的介电常数。高介电常数介电层可包括金属氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb与前述的组合的硅化物。高介电常数介电层的形成方法可包括原子层沉积、化学气相沉积、分子束沉积(molecular beam deposition,MBD)、类似方法或前述的组合。其他实施例可将栅极介电质521的其他材料纳入考量，如不具有高介电常数的材料。如图20C中所示出，栅极介电质521覆盖了图19C中移除第一半导体层205而露出的纳米片407的表面与内间隔物410。
如图20B中所示出，可形成第一与第二栅极介电质521a与521b使其各自具有不同的厚度。较厚的栅极介电质适合用于输出入装置中的纳米片。核心装置(core device)可使用较薄的栅极介电质，其在相邻的纳米片间具有较小的间距，可防止核心装置因较大的电容而劣化(degradation)。在一实施例中，调整反应气体流速、生成温度或沉积栅极介电质期间的时间长度，决定第一与第二栅极介电质521a与521b的相对平均厚度。第二栅极介电质521b可具有第二栅极介电质厚度，其大于第一栅极介电质521a的第一栅极介电质厚度。第一栅极介电质521a的平均厚度可在约1nm至约5nm的范围，而第二栅极介电质521b可在约2.5nm至约7nm的范围。
也可形成第一与第二栅极介电质521a与521b使其具有不同的组成。例如，第一栅极介电质521a可包括SiO2、SiON、Si3N4、HfOx、LaOx以及/或AlOx，而第二栅极介电质521b可包括不同比例的第一栅极介电质521a的SiO2、SiON、Si3N4、HfOx、LaOx以及/或AlOx。
图21A、图21B与图21C中，金属栅极结构525形成于栅极介电质521上以形成金属栅极电极。金属栅极结构525可为多层结构。例如，金属栅极结构525可包括顺应地形成于栅极介电质上的盖层(capping layer)、顺应地形成于盖层上的一或多层功函数调整层(workfunction tuning layer)，以及含金属材料如金属，形成于功函数调整层上并填充移除虚置金属栅极堆叠419所腾空的空间。在一范例中，盖层可包括利用原子层沉积、化学气相沉积或类似制程于栅极介电质上形成的第一次层(sub-layer)，由TiN或类似材料所形成，以及利用原子层沉积、化学气相沉积或类似制程于第一次层上形成的第二次层，由TaN或类似材料所形成。功函数调整层可由TiAl、TiN或类似材料所形成，且可利用原子层沉积、化学气相沉积或类似制程形成功函数调整层。含金属材料可为钨、铝、钴、铷、前述的组合或类似材料，且可利用化学气相沉积、物理气相沉积、类似制程或前述的组合形成含金属材料。如图21C中所示出，金属栅极结构525填充了纳米片407间剩余的空间其位于栅极介电质521围绕的空腔(cavity)之中。接着，可进行平坦化制程如化学机械研磨以移除金属栅极结构与栅极介电质过多的部分，其位于层间介电质513与515的顶表面之上，因而产生如图21A与图21B中所示出的结构。
图22至图28B是根据另一实施例，示出形成三个水平全绕式栅极晶体管的示意图，其彼此相邻且相距较大的距离，且相对于彼此具有调整的栅极介电质厚度以及/或组成、薄片厚度、薄片间距、薄片宽度与堆叠数量。
图22示出三个鳍片303a、303b与303c的示意图，是从图5A或图5B沿着图2A中的剖面B-B所示出的剖面图中的结构所图案化。示出于图22中的实施例与示出于图6B中的实施例的差异在于第一交替层堆叠203a被图案化而分别形成两个鳍片303a与303c。第三鳍片303c的第一与第二半导体层205c与207c可具有与第一鳍片303a的第一及第二半导体层205a与207b实质上相同的数量与厚度，但可图案化鳍片303a、303b与303c使其各具有不同的宽度。例如，在一实施例中，鳍片303a的宽度可在约4nm至约100nm的范围，鳍片303b的宽度可在约4nm至约100nm的范围，而鳍片303c的宽度可在约4nm至约100nm的范围。鳍片303a、303b与303c的图案化将决定鳍片在后续步骤中产生的纳米片的宽度(薄片宽度)。较大的薄片宽度(或Weff，纳米片有效宽度)使更高速度性能得以实现。较小的薄片宽度则使低功率应用得以实现。鳍片303a、303b与303c将用以形成一或多个n型鳍状场效晶体管以及/或p型鳍状场效晶体管的水平纳米片。虽然图22中示出三个鳍片(第一鳍片303a、第二鳍片303b与第三鳍片303c)，应能理解可使用任何合适数量与形态的鳍片303。
图23示出利用以上图7B中所示的步骤形成浅沟槽隔离区313的示意图，但其具有三个鳍片303而非两个鳍片。图24示出利用以上图8B中所示的步骤凹蚀浅沟槽隔离区313的示意图，但其具有三个鳍片303而非两个鳍片。图25示出利用以上图10B中所示的步骤于第一、第二与第三鳍片303a、303b与303c之上形成虚置金属栅极堆叠419的示意图，但其具有三个鳍片303而非两个鳍片。图26示出利用以上图19B中所示的步骤形成第一、第二与第三纳米片堆叠407a、407b与408c的示意图，但其具有三个鳍片303而非两个鳍片。应能理解图23至图26中所示出的中间步骤与以上图8B至图19B中所示出的步骤实质上相同，但其具有三个鳍片303而非两个鳍片。此外，虽然图23至图26中示出三个鳍片(第一鳍片303a、第二鳍片303b与第三鳍片303c)，应能理解可使用任何合适数量与形态的鳍片。
图27中，第一、第二与第三栅极介电质521a、521b与521c分别形成于第一纳米片堆叠407a、第二纳米片堆叠407b与第三纳米片堆叠407c的露出部分之上，而第一、第二与第三栅极介电质521a、521b与521c(因此共同称为栅极介电质521)可为界面介电质。其他实施例可将栅极介电质521的其他材料纳入考量，如不具有高介电常数的材料。
可形成第一、第二与第三栅极介电质521a、521b与521c使其各自具有不同的厚度。较厚的栅极介电质适合用于输出入装置，而较薄的栅极介电质适合用于核心装置。调整沉积栅极介电质期间的时间长度可决定第一、第二与第三栅极介电质521a、521b与521c的相对平均厚度。在一实施例中，第一栅极介电质521a的平均厚度可在约1nm至约5nm的范围，第二栅极介电质521b的平均厚度可在约2.5nm至约7nm的范围，而第三栅极介电质521c的平均厚度可在约1nm至约7nm的范围。在一实施例中，为了以第三栅极介电质521c作为装置的一部分而使其使用较低功率而具有较高的可靠度(reliability)，第三栅极介电质521c的平均厚度实质上大于第一栅极介电质521a的平均厚度，并实质上小于二栅极介电质521b的平均厚度。
也可形成第一、第二与第三栅极介电质521a、521b与521c使其具有不同组成。例如第一栅极介电质521a可包括SiO2、SiON、Si3N4、HfOx、LaOx以及/或AlOx，而第二栅极介电质521b与第三栅极介电质521c可包括不同比例的第一栅极介电质521a的SiO2、SiON、Si3N4、HfOx、LaOx以及/或AlOx。
图28A中，利用以上图10B中所示的步骤于栅极介电质521上形成金属栅极结构525，但其具有三个鳍片303而非两个鳍片。图28B示出另一实施例，其中顶部的纳米片407c被移除而导致相对于第一纳米片堆叠407a，第三纳米片堆叠407c具有较少的纳米片。在其他实施例中，可从第一、第二与第三纳米片堆叠407a、407b与407c移除不同数量的纳米片。应能理解可在制程任何适宜的步骤中移除纳米片。例如，形成图26中所示出的第三纳米片堆叠后，可利用适当的Si选择性移除制程移除顶部的纳米片407c。减少第三纳米片堆叠407c的堆叠数量可使其用于装置的一部分，其需要较低功率而具有较高的可靠度。此外，虽然图28A与图28B中示出三个纳米片堆叠407a、408b与408c，应能理解可产生任何合适数量的纳米片堆叠。
以上公开的实施例包括全绕式栅极晶体管的制造方法，可调整纳米片宽度、纳米片厚度、纳米片间距与堆叠数量。此纳米片结构的调整可用于单一晶圆上。这样的设计弹性对电路性能与功率运用的设计最佳化提供广泛的调整范围。较大的纳米片宽度使更高速度性能得以实现，且较小的纳米片宽度以及/或减少堆叠数量则可使低功率应用得以实现。增加薄片间距(堆叠中相邻的纳米片之间的距离)使较厚的输出入栅极氧化物得以用于实现纳米片结构输出入装置。可制造使用纳米片结构的全绕式栅极晶体管使其彼此相邻或彼此分离开，并可将其用于逻辑装置、静态随机存取存储器装置、输出入装置、静电放电装置或无源元件。
根据一实施例，半导体装置的制造方法包括：于基板上形成第一交替层堆叠，其中形成第一交替层堆叠的步骤包括于基板上交替沉积第一半导体材料的第一层与第二半导体材料的第二层，第二半导体材料与第一半导体材料不同；于基板上形成第二交替层堆叠，距第一交替层堆叠第一距离，其中形成第二交替层堆叠的步骤包括于基板上交替沉积第一半导体材料的第一层与第二半导体材料的第二层，且其中相对该第一交替层堆叠的第一层，第二交替层堆叠的第一层具有较大的厚度；从第一交替层堆叠建构第一纳米片堆叠且从第二交替层堆叠建构第二纳米片堆叠，其中建构第一与第二纳米片堆叠的步骤包括：从第一交替层堆叠图案化第一鳍片，且从第二交替层堆叠图案化第二鳍片；以及从第一交替层堆叠移除第一层且从第二交替层堆叠移除第一层，使得第二交替层堆叠相邻的剩余层间的距离大于第一交替层堆叠相邻的剩余层间的距离；以及于第一纳米片堆叠之上形成第一栅极介电质，且于第二纳米片堆叠之上形成第二栅极介电质。在一实施例中，形成第一栅极介电质使其包括第一栅极介电质厚度，且形成第二栅极介电质使其包括第二栅极介电质厚度，第二栅极介电质厚度大于第一栅极介电质厚度。在一实施例中，形成第一与第二栅极介电质使其包括不同材料。在一实施例中，通过控制用于形成第一交替层堆叠的外延成长循环的数量，形成第一交替层堆叠使其包括第一数量的交替层；其中通过控制用于形成第二交替层堆叠的外延成长循环的数量，形成第二交替层堆叠使其包括第二数量的交替层；且其中第一数量与第二数量不同。在一实施例中，形成第二交替层堆叠的第二层使其相对于第一交替层堆叠的第二层具有较大的厚度。
根据另一实施例，半导体装置的制造方法包括：于基板上的第一交替层堆叠中蚀刻凹口，其中第一交替层堆叠包括交替的第一层与第二层，第一层包括第一半导体材料而第二层包括第二半导体材料，第一半导体材料与第二半导体材料不同，其中第一交替层堆叠的第一层具有第一平均厚度，而第一交替层堆叠的第二层具有第二平均厚度，其中通过控制第一交替层堆叠的第一层与第二层的外延成长，决定第一平均厚度与第二平均厚度；于第一交替层堆叠中形成第二交替层堆叠，其中形成第二交替层堆叠的步骤包括于凹口中沉积交替的第一层与第二层，第一层包括第一半导体材料，而第二层包括第二半导体材料，其中第二交替层堆叠的第一层具有第三平均厚度，而第二交替层堆叠的第二层具有第四平均厚度，第三平均厚度与第一平均厚度不同，且第四平均厚度与第二平均厚度不同，其中通过控制第二交替层堆叠的第一层与第二层的外延成长，决定第三平均厚度与第四平均厚度；从第一交替层堆叠建构第一纳米片堆叠，且从第二交替层堆叠建构第二纳米片堆叠，其中建构第一与第二纳米片堆叠的步骤包括：从第一交替层堆叠图案化第一鳍片，且从第二交替层堆叠图案化第二鳍片；以及从第一交替层堆叠与第二交替层堆叠移除第一层与第二层的其中之一；以及于第一纳米片堆叠之上形成第一栅极介电质，且于第二纳米片堆叠之上形成第二栅极介电质。在一实施例中，形成第一纳米片堆叠使其具有第一宽度，且形成第二纳米片堆叠使其具有第二宽度，第一宽度与第二宽度不同。在一实施例中，形成第一与第二纳米片堆叠使其包括不同数量的纳米片。在一实施例中，形成第二交替层堆叠的步骤还包括：于凹口的侧壁上形成间隔物；以及于间隔物的侧壁间的凹口中交替沉积第一半导体材料的第一层与第二半导体材料的第二层。在一实施例中，图案化第二鳍片的步骤包括将间隔物蚀刻掉。在一实施例中，形成第二交替层堆叠的步骤还包括于凹口的底部与侧壁上顺应地交替沉积第一半导体材料的第一层与第二半导体材料的第二层。在一实施例中，图案化第二鳍片的步骤包括将第二交替层堆叠的外部部分蚀刻掉，使其剩余部分仅包括交替的第一半导体材料的水平第一层与第二半导体材料的水平第二层。
根据更另一实施例，半导体装置包括：第一纳米片堆叠，其中第一栅极介电质围绕第一纳米片堆叠的每个纳米片，其中第一纳米片堆叠的相邻纳米片以第一平均间距彼此隔离；以及第二纳米片堆叠，距第一纳米片堆叠第一距离，其中第二栅极介电质围绕第二纳米片堆叠的每个纳米片，其中第二纳米片堆叠的相邻纳米片以第二平均间距彼此隔离，其中第二平均间距大于第一平均间距。在一实施例中，第一栅极介电质具有第一平均厚度，而第二栅极介电质具有第二平均厚度，第二平均厚度大于第一平均厚度。在一实施例中，第一与第二纳米片堆叠包括不同数量的纳米片。在一实施例中，第一纳米片堆叠的纳米片具有第一平均厚度，而第二纳米片堆叠的纳米片具有第二平均厚度，第二平均厚度大于第一平均厚度。在一实施例中，第一纳米片堆叠包括部分的逻辑元件(logic device)，而第二纳米片堆叠包括部分的输出入装置(IO device)。在一实施例中，第三纳米片堆叠距第一纳米片堆叠第二距离，第二距离小于第一距离，且其中第一纳米片堆叠具有第一宽度，而第三纳米片堆叠具有第二宽度，第一宽度大于第二宽度。在一实施例中，第三纳米片堆叠距第一纳米片堆叠第二距离，第二距离小于第一距离，其中第三栅极介电质围绕第三纳米片堆叠的每个纳米片，其中第一栅极介电质具有第一平均厚度，第二栅极介电质具有第二平均厚度，第三栅极介电质具有第三平均厚度，第三平均厚度大于第一平均厚度，第三平均厚度小于第二平均厚度。在一实施例中，第三纳米片堆叠距第一纳米片堆叠第二距离，第二距离小于第一距离，且其中第一与第三纳米片堆叠包括不同数量的纳米片。
以上概述数个实施例的部件，以便在本发明所属技术领域中技术人员可更易理解本发明实施例的观点。在本发明所属技术领域中技术人员应理解，他们能以本发明实施例为基础，设计或修改其他制程和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中技术人员也应理解到，此类等效的制程和结构并无悖离本发明的精神与范围，且他们能在不违背本发明的精神和范围之下，做各式各样的改变、取代和替换。

Claims (10)

1.一种半导体装置的制造方法，包括：
于一基板上形成一第一交替层堆叠，其中形成该第一交替层堆叠的步骤包括于该基板上交替沉积一第一半导体材料的多个第一层与一第二半导体材料的多个第二层，该第二半导体材料与该第一半导体材料不同；
于该基板上形成一第二交替层堆叠，距该第一交替层堆叠一第一距离，其中形成该第二交替层堆叠的步骤包括于该基板上交替沉积该第一半导体材料的多个第一层与该第二半导体材料的多个第二层，且其中相对于该第一交替层堆叠的所述多个第一层，该第二交替层堆叠的所述多个第一层具有较大的厚度；
从该第一交替层堆叠建构一第一纳米片堆叠且从该第二交替层堆叠建构一第二纳米片堆叠，其中建构该第一与该第二纳米片堆叠的步骤包括：
从该第一交替层堆叠图案化一第一鳍片，且从该第二交替层堆叠图案化一第二鳍片；以及
从该第一交替层堆叠移除所述多个第一层且从该第二交替层堆叠移除所述多个第一层，使得该第二交替层堆叠相邻的剩余层间的距离大于该第一交替层堆叠相邻的剩余层间的距离；以及
于该第一纳米片堆叠之上形成一第一栅极介电质，且于该第二纳米片堆叠之上形成一第二栅极介电质。
2.如权利要求1所述的半导体装置的制造方法，其中形成该第一栅极介电质使其包括一第一栅极介电质厚度，且形成该第二栅极介电质使其包括一第二栅极介电质厚度，该第二栅极介电质厚度大于该第一栅极介电质厚度。
3.如权利要求1所述的半导体装置的制造方法，其中通过控制用于形成该第一交替层堆叠的外延成长循环的数量，形成该第一交替层堆叠使其包括一第一数量的交替层；其中通过控制用于形成该第二交替层堆叠的外延成长循环的数量，形成该第二交替层堆叠使其包括一第二数量的交替层；且其中该第一数量与该第二数量不同。
4.如权利要求1所述的半导体装置的制造方法，其中形成该第二交替层堆叠的所述多个第二层使其相对于该第一交替层堆叠的所述多个第二层具有较大的厚度。
5.一种半导体装置的制造方法，包括：
于一基板上的一第一交替层堆叠中蚀刻一凹口，其中该第一交替层堆叠包括交替的多个第一层与多个第二层，所述多个第一层包括一第一半导体材料而所述多个第二层包括一第二半导体材料，该第一半导体材料与该第二半导体材料不同，其中该第一交替层堆叠的所述多个第一层具有一第一平均厚度，而该第一交替层堆叠的所述多个第二层具有一第二平均厚度，其中通过控制该第一交替层堆叠的所述多个第一层与所述多个第二层的外延成长，决定该第一平均厚度与该第二平均厚度；
于该第一交替层堆叠中形成一第二交替层堆叠，其中形成该第二交替层堆叠的步骤包括于该凹口中沉积交替的多个第一层与多个第二层，所述多个第一层包括该第一半导体材料，而所述多个第二层包括该第二半导体材料，其中该第二交替层堆叠的所述多个第一层具有一第三平均厚度，而该第二交替层堆叠的所述多个第二层具有一第四平均厚度，该第三平均厚度与该第一平均厚度不同，且该第四平均厚度与该第二平均厚度不同，其中通过控制该第二交替层堆叠的所述多个第一层与所述多个第二层的外延成长，决定该第三平均厚度与该第四平均厚度；
从该第一交替层堆叠建构一第一纳米片堆叠，且从该第二交替层堆叠建构一第二纳米片堆叠，其中建构该第一与该第二纳米片堆叠的步骤包括：
从该第一交替层堆叠图案化一第一鳍片，且从该第二交替层堆叠图案化一第二鳍片；以及
从该第一交替层堆叠与该第二交替层堆叠移除所述多个第一层与所述多个第二层的其中之一；以及
于该第一纳米片堆叠之上形成一第一栅极介电质，且于该第二纳米片堆叠之上形成一第二栅极介电质。
6.如权利要求5所述的半导体装置的制造方法，其中形成该第一纳米片堆叠使其具有一第一宽度，且形成该第二纳米片堆叠使其具有一第二宽度，该第一宽度与该第二宽度不同。
7.如权利要求5所述的半导体装置的制造方法，其中形成该第二交替层堆叠的步骤还包括：
于该凹口的多个侧壁上形成一间隔物；以及
于该间隔物的多个侧壁间的该凹口中交替沉积该第一半导体材料的多个第一层与该第二半导体材料的多个第二层。
8.一种半导体装置，包括
一第一纳米片堆叠，其中一第一栅极介电质围绕该第一纳米片堆叠的每个纳米片，其中该第一纳米片堆叠的相邻纳米片以一第一平均间距彼此隔离；以及
一第二纳米片堆叠，距该第一纳米片堆叠一第一距离，其中一第二栅极介电质围绕该第二纳米片堆叠的每个纳米片，其中该第二纳米片堆叠的相邻纳米片以一第二平均间距彼此隔离，其中该第二平均间距大于该第一平均间距。
9.如权利要求8所述的半导体装置，其中一第三纳米片堆叠距该第一纳米片堆叠一第二距离，该第二距离小于该第一距离，且其中该第一纳米片堆叠具有一第一宽度，而该第三纳米片堆叠具有一第二宽度，该第一宽度大于该第二宽度。
10.如权利要求8所述的半导体装置，其中一第三纳米片堆叠距该第一纳米片堆叠一第二距离，该第二距离小于该第一距离，其中一第三栅极介电质围绕该第三纳米片堆叠的每个纳米片，其中该第一栅极介电质具有一第一平均厚度，该第二栅极介电质具有一第二平均厚度，该第三栅极介电质具有一第三平均厚度，该第三平均厚度大于该第一平均厚度，该第三平均厚度小于该第二平均厚度。
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