CN110416081B - Nfet/pfet的源极/漏极区域的选择性凹进 - Google Patents

Nfet/pfet的源极/漏极区域的选择性凹进 Download PDF

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CN110416081B
CN110416081B CN201811098848.7A CN201811098848A CN110416081B CN 110416081 B CN110416081 B CN 110416081B CN 201811098848 A CN201811098848 A CN 201811098848A CN 110416081 B CN110416081 B CN 110416081B
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source
drain region
etch
polymer layer
drain
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CN110416081A (zh
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张云闵
陈建安
王冠人
王鹏
陈煌明
林焕哲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括在第一源极/漏极区域和第二源极/漏极区域上方形成层间电介质。第一源极/漏极区域和第二源极/漏极区域分别是n型和p型。蚀刻层间电介质以形成第一接触开口和第二接触开口，其中，第一源极/漏极区域和第二源极/漏极区域分别暴露于第一接触开口和第二接触开口。使用工艺气体来同时回蚀刻第一源极/漏极区域和第二源极/漏极区域，并且第一源极/漏极区域的第一蚀刻速率高于第二源极/漏极区域的第二蚀刻速率。在第一源极/漏极区域和第二源极/漏极区域上分别形成第一硅化物区域和第二硅化物区域。本发明的实施例还涉及NFET/PFET的源极/漏极区域的选择性凹进。

Description

NFET/PFET的源极/漏极区域的选择性凹进
技术领域
本发明的实施例涉及NFET/PFET的源极/漏极区域的选择性凹进。
背景技术
随着集成电路的尺寸变得越来越小，相应的形成工艺也变得越来越困难，并且可能在传统没有出现问题的地方出现问题。例如，在鳍式场效应晶体管(FinFET)的形成中，源极/漏极区域的尺寸变得越来越小，使得接触电阻越来越高。
发明内容
本发明的实施例提供了一种形成晶体管的方法，包括：在第一源极/漏极区域和第二源极/漏极区域上方形成层间电介质，其中，所述第一源极/ 漏极区域和所述第二源极/漏极区域分别是n型和p型；蚀刻所述层间电介质以形成第一接触开口和第二接触开口，其中，所述第一源极/漏极区域和所述第二源极/漏极区域分别暴露于所述第一接触开口和所述第二接触开口；引入工艺气体以同时回蚀刻所述第一源极/漏极区域和所述第二源极/漏极区域，其中，所述第一源极/漏极区域的第一蚀刻速率高于所述第二源极/漏极区域的第二蚀刻速率；以及在所述第一源极/漏极区域和所述第二源极/漏极区域上分别形成第一硅化物区域和第二硅化物区域。
本发明的另一实施例提供了一种形成晶体管的方法，包括：在第一源极/漏极区域上方形成介电层；蚀刻所述介电层以形成第一接触开口，其中，所述第一源极/漏极区域的顶面暴露于所述第一接触开口；使用包括含硫气体和聚合物生成气体的工艺气体回蚀刻所述第一源极/漏极区域，其中，所述含硫气体包括SF6或氧硫化碳；以及在凹进的第一源极/漏极区域上生成第一硅化物区域。
本发明的又一实施例提供了一种形成晶体管的方法，包括：实施第一外延以形成用于n型鳍式场效应晶体管(FinFET)的第一源极/漏极区域；使用工艺气体回蚀刻所述第一源极/漏极区域，其中，所述工艺气体包括氧硫化碳和含碳和氟的气体，其中，所述回蚀刻生成从所述第一源极/漏极区域的顶面延伸至所述第一源极/漏极区域内的凹槽；以及在所述第一源极/ 漏极区域上形成第一硅化物区域，其中，所述第一硅化物区域包括底部和位于所述底部的相对端上方并且连接至所述底部的相对端的侧壁部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图20是根据一些实施例的形成n型鳍式场效应晶体管(FinFET) 和p型FinFET的中间阶段的截面图和立体图。
图21示出了根据一些实施例的用于形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。在一些示出的实施例中，使用鳍式场效应晶体管(FinFET)的形成作为实例来解释本发明的构思。诸如平面晶体管的其它晶体管也可以采用本发明的构思。
图1至图20示出了根据本发明的一些实施例的形成晶体管(例如，可以是FinFET)的中间阶段的截面图和立体图。图1至图20中示出的步骤也在图21中示出的工艺流程300中示意性地示出。所形成的晶体管包括器件区域100中的第一晶体管和器件区域200中的第二晶体管。根据本发明的一些实施例，形成在器件区域100中的晶体管是n型FinFET，并且形成在器件区域200中的晶体管是p型FinFET。
图1示出了初始结构的立体图。初始结构包括晶圆10，晶圆10进一步包括衬底20。衬底20可以是半导体衬底，半导体衬底可以是硅衬底、硅锗衬底或由其它半导体材料形成的衬底。根据一些实施例，衬底20包括块状硅衬底和位于块状硅衬底上方的外延硅锗(SiGe)层或锗层(其中不含硅)。衬底20可以掺杂有p型杂质或n型杂质。诸如浅沟槽隔离(STI) 区域的隔离区域22可以形成为延伸至衬底20内。衬底20的位于相邻的 STI区域22之间的部分称为半导体带124和224，半导体带124和224分别位于器件区域100和200中。
STI区域22可以包括衬垫氧化物(未示出)。衬垫氧化物可以是通过衬底20的表面层的热氧化形成的热氧化物。衬垫氧化物也可以是使用例如原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)或化学汽相沉积(CVD)形成的沉积氧化硅层。STI区域22也可以包括位于衬垫氧化物上方的介电材料，其中，介电材料可以使用可流动化学汽相沉积(FCVD)、旋涂等形成。
参照图2，使STI区域22凹进，使得半导体带124和224的顶部突出高于相邻STI区域22的顶面122A和222A以形成突出鳍124’和224’。相应的工艺示出为图21中示出的工艺流程300中的工艺302。可以使用干蚀刻工艺来实施蚀刻，其中，使用HF3和NH3作为蚀刻气体。在蚀刻工艺期间，可以生成用于蚀刻的等离子体。也可以包括氩气。根据本发明的可选实施例，使用湿蚀刻工艺实施STI区域22的凹进。例如，蚀刻化学物质可以包括HF溶液。
参照图3，分别在突出鳍124’和224’的顶面和侧壁上形成伪栅极堆叠件130和230。相应的工艺示出为图21中示出的工艺流程300中的工艺304。伪栅极堆叠件130可以包括伪栅极电介质132和位于伪栅极电介质132上方的伪栅电极134。伪栅极堆叠件230可以包括伪栅极电介质232和位于伪栅极电介质232上方的伪栅电极234。可以例如使用非晶硅或多晶硅形成伪栅电极134和234，但是也可以使用其它材料。伪栅极堆叠件130和 230的每个也可以包括一个(或多个)硬掩模层136和236。硬掩模层136 和236可以由氮化硅、碳氮化硅等形成。伪栅极堆叠件130和230的每个均分别横跨在单个或多个突出鳍124’和224’上方。伪栅极堆叠件130和230 也可以具有分别垂直于相应的突出鳍124’和224’的纵向方向的纵向方向。
下一步，分别在伪栅极堆叠件130和230的侧壁上形成栅极间隔件138 和238。同时，鳍间隔件(未示出)也可以形成在突出鳍124’和224’的侧壁上。根据本发明的一些实施例，栅极间隔件138和238由诸如碳氮氧化硅(SiCON)、氮化硅等的介电材料形成，并且可以具有单层结构或包括多个介电层的多层结构。
根据一些实施例，每个栅极间隔件138均包括第一介电层138A和第二介电层138B(未在图3中示出，参照图6B)，其中，层138A和138B的每个均通过毯式沉积步骤以及随后的各向异性蚀刻步骤形成。根据一些实施例，介电层138A是低k介电层，并且介电层138B是非低k介电层。介电层138A可以由具有低于约3.0的介电常数(k值)的低k介电材料形成，介电层138A可以由SiON或SiOCN形成，其中形成有孔，以将其k值减小至期望的低k值。例如，介电层138B可以由氮化硅形成。栅极间隔件 238具有与栅极间隔件138相同的结构，并且可以包括分别由与层138A和 138B相同的材料形成的层238A和238B(图6B)。根据其它实施例，介电层138A是非低k介电层，并且介电层138B是低k介电层，并且对应的低k介电材料和非低k介电材料可以与以上描述的类似。采用低k电介质可以减小栅电极和源极/漏极区域之间的寄生电容。
然后实施蚀刻步骤以蚀刻未由伪栅极堆叠件130和230以及栅极间隔件138和238覆盖的突出鳍124’和224’的部分，从而产生图4所示的结构。凹进可以是各向异性的，并且因此位于相应的伪栅极堆叠件130/230和栅极间隔件138/238正下面的鳍124’和224’的部分受到保护，并且不被蚀刻。根据一些实施例，凹进的半导体带124和224的顶面可以低于邻近的STI 区域22的顶面。因此，在STI区域22之间形成凹槽140和240。可以在同一蚀刻工艺中或在单独的蚀刻工艺中实施器件区域100和200中的凹进，并且凹槽140的深度可以等于凹槽240的深度或与凹槽240的深度不同。
下一步，通过从凹槽140和240选择性地生长半导体材料来形成外延区域(源极/漏极区域)，从而产生图5中的结构。相应的工艺示出为图21 中示出的工艺流程300中的工艺306。根据一些实施例，外延区域142由硅磷(SiP)或硅碳磷(SiCP)形成，其是n型的。当器件区域200中的相应的晶体管是p型晶体管时，外延区域242可以由掺杂有硼的硅锗(SiGeB)形成。外延区域242可以包括具有较低锗浓度的下层和具有较高浓度的上层。根据一些实施例，在具有高锗浓度的上层上方可以存在或不存在硅帽 (不含锗)。例如，下层可以具有介于约20％和约40％之间的锗原子百分比，并且上层可以具有介于约40％和约75％之间的锗原子百分比。
在单独的工艺中并且使用不同的掩模(未示出)实施外延区域142和 242的形成。根据本发明的可选实施例，外延区域142和242由诸如GaAs、 InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层的III-V族化合物半导体形成。在用外延半导体材料填充凹槽140和240之后，外延区域142和242的进一步外延生长使得外延区域142和242水平地扩展，并且可以形成小平面。从相邻凹槽生长的外延区域可以合并以形成大的外延区域，或当它们不合并时可以保持为离散的外延区域。外延区域142和242形成相应的晶体管的源极/漏极区域。
图6A示出了用于沉积接触蚀刻停止层(CESL)46和层间电介质(ILD) 48的立体图。相应的工艺示出为图21中示出的工艺流程300中的工艺308。根据本发明的一些实施例，CESL 46由氮化硅、碳氮化硅等形成。例如， CESL 46可以使用诸如ALD或CVD的共形沉积方法来形成。ILD 48形成在CESL 46上方，并且可以使用例如FCVD、旋涂、CVD等形成。ILD 48可以由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等形成。可以实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使ILD 48、伪栅极堆叠件130和230以及栅极间隔件138和238的顶面彼此平齐。
图6B示出了图6A所示的结构的截面图，其中，截面图从包含图6A 中的线A-A的垂直平面和包含图6A中的线B-B的垂直平面获得。在形成图6A和图6B所示的结构之后，用金属栅极和替换栅极电介质替换包括硬掩模层136和236、伪栅电极134和234以及伪栅极电介质132和232的伪栅极堆叠件130和230。在图6B以及随后的截面图中，可以示出STI区域22的顶面122A和222A，并且突出鳍124’和224’分别突出高于顶面122A 和222A。
为了形成替换栅极，通过蚀刻去除图6A和图6B所示的硬掩模层136 和236、伪栅电极134和234以及伪栅极电介质132和232，在栅极间隔件 138之间和栅极间隔件238之间形成沟槽。因此，突出鳍124’和224’的顶面和侧壁暴露于产生的沟槽。图7A和图7B示出了在由去除的伪栅极堆叠件留下的沟槽中形成替换栅极堆叠件150和250和硬掩模160和260之后的晶圆10的部分的立体图和截面图。相应的工艺示出为图21中示出的工艺流程300中的工艺310。根据本发明的一些实施例，如图7B所示，栅极电介质152和252分别包括界面层(IL)154和254以及上面的高k电介质 156和256。分别在突出鳍124’和224’的暴露表面上形成IL154和254。IL 154和254的每个均可以包括通过突出鳍124’和224’的表面层的热氧化、化学氧化工艺或沉积工艺形成的诸如氧化硅层的氧化物层。
同样在图7B中示出的，栅极电介质152和252可以包括分别形成在 IL 154和254上方的高k介电层156和256。高k介电层156和256可以包括诸如氧化铪、氧化镧、氧化铝、氧化锆、氮化硅等的高k介电材料。高 k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0。高k介电层 156和256形成为共形层，并且在突出鳍124’和224’的侧壁以及栅极间隔件138和238的侧壁上延伸。根据本发明的一些实施例，使用ALD或CVD 形成高k介电层156和256。
栅电极158和258(图7B)可以包括多个堆叠的导电子层。可以使用诸如ALD或CVD的共形沉积方法来实施栅电极158和258的形成，使得栅电极158和258的下子层的垂直部分的厚度和水平部分的厚度基本彼此相等。
栅电极158和258可以分别包括金属层158A和258A，每个金属层均包括扩散阻挡层和位于扩散阻挡层上方的一个(或多个)功函层(未单独示出)。扩散阻挡层可以由氮化钛(TiN)形成，其可以(或可以不)掺杂有硅。功函层决定栅极的功函数，并且包括至少一层或由不同材料形成的多个层。根据相应的FinFET是n型FinFET还是p型FinFET来选择功函层的材料。例如，(n型FinFET的)金属层158A中的功函层可以包括TaN 层和位于TaN层上方的钛铝(TiAl)层。(p型FinFET的)金属层258A 中的功函层可以包括TaN层、位于TaN层上方的TiN层和位于TiN层上方的TiAl层。在功函层的沉积之后，形成阻挡层，其可以是另一TiN层。
栅电极158和258也可以包括填充未由下面的子层填充的剩余沟槽的相应的填充金属158B和258B。例如，填充金属可以由钨或钴形成。在填充材料的形成之后，实施诸如CMP工艺或机械研磨工艺的平坦化工艺，以去除ILD 48上方的层152/252和158/258的部分。下文将栅极电介质152/252 和栅电极158/258的剩余部分的组合称为替换栅极150和250。
根据一些实施例，然后形成自对准硬掩模160和260。自对准硬掩模 160和260与下面的替换栅极150和250自对准，并且由诸如ZrO2、Al2O3、 SiON、SiCN、SiO2等的介电材料形成，并且可以不含SiN。形成工艺可以包括蚀刻替换栅极150和250以形成凹槽，将介电材料填充至凹槽内，并且实施平坦化工艺以去除介电材料的过量部分。此时，硬掩模160和260、栅极间隔件138和238、CESL 46和ILD 48的顶面可以基本共面。
参照图8A和图8B，蚀刻ILD 48和CESL 46以形成源极/漏极接触开口162和262。相应的工艺示出为图21中示出的工艺流程300中的工艺312。 CESL 46用作ILD 48的蚀刻中的蚀刻停止层，并且然后蚀刻CESL 46，暴露下面的源极/漏极区域142和242。接触开口162和262可以同时形成，或可以单独形成。图8B示出了从包含图8A中的线A-A和B-B的垂直平面获得的截面图。如图8B所示，由于过蚀刻，开口162和262可以略微延伸至源极/漏极区域142和242内例如小于约5nm的深度D1。
同样参照图8B，在接触开口162和262的形成之后，在源极/漏极区域 142和242、CESL 46和ILD 48的侧壁上形成接触间隔件164和264。相应的工艺示出为图21中示出的工艺流程300中的工艺314。接触间隔件164 和264的形成可以包括形成介电层，并且然后实施各向异性蚀刻以去除介电层的水平部分，留下垂直部分作为接触间隔件。根据本发明的一些实施例，使用诸如CVD或ALD的共形沉积方法来形成介电层。介电层可以是 k值大于3.9的高k介电层，因此具有良好的隔离能力。备选材料包括AlxOy、 HfO2和SiOCN(内部没有孔或基本没有孔)，并且当在随后的源极/漏极区域的回蚀刻中使用CF4或类似的气体时可以不含SiN。例如，介电层的厚度可以介于约2nm和约6nm之间的范围内。当从晶圆10的顶部观察时，接触间隔件164和264的每个均可以形成环。根据可选实施例，跳过接触间隔件164和264的形成。
图8C示出了器件区域100和200中的任一结构的截面图，其中，截面图从图8A中的平面交叉线C1-C1或线C2-C2获得。图8C所示的截面图也从包含图8B中的线8C1-8C1或线8C2-8C2的平面获得。
图9至图11示出了源极/漏极区域142的回蚀刻。相应的工艺示出为图21中示出的工艺流程300中的工艺316。根据本发明的一些实施例，在回蚀刻中，源极/漏极区域142和242都暴露于相同的工艺气体以节省制造成本，并且因此源极/漏极区域142和242都经受蚀刻。产生的n型FinFET 的n型源极/漏极区域142的回蚀刻可以增加接触面积，这将在随后的段落中讨论。因此，减小了接触插塞与源极/漏极区域142的接触电阻，并且改进了器件性能。另一方面，旨在最小化产生的p型FinFET的p型源极/漏极区域242的回蚀刻。这是因为难以用诸如硼的p型掺杂剂重掺杂整个源极/漏极区域242。因此，源极/漏极区域242的顶面层被重掺杂，而下层的掺杂比顶面层轻。例如，源极/漏极区域242的顶面层可以具有高于约1× 1020/cm3或在约1×1020/cm3和约1×1022/cm3之间的范围内的p型或n型掺杂剂浓度。下层的掺杂剂浓度可以比顶面层的掺杂剂浓度低一个或两个数量级。例如，下层的掺杂剂浓度可以在约1×1018/cm3和约1×1020/cm3之间的范围内。因此，不期望在回蚀刻中蚀刻顶面层以保留由p型源极/漏极区域242的重掺杂顶面层产生的高电导率。
根据一些实施例，如由箭头66代表的蚀刻气体包括含硫气体、聚合物生成气体和用于蚀刻源极/漏极区域142的蚀刻气体。根据一些实施例，聚合物生成气体和蚀刻气体可以是相同的气体。含硫气体可以包括SF6、羰基硫化物(COS，也称为氧硫化碳)等。聚合物生成气体可以包括CxHyFz，其中，x，y和z是整数。例如，聚合物生成气体可以包括CF4(其中，x＝1， y＝0以及z＝4)、CH3F、CH2F2等。蚀刻气体可以包括CxHyFz、HBr、Cl2等。因此，CxHyFz可以用作聚合物生成气体和蚀刻气体，并且可以或可以不添加另一种蚀刻气体。氢气(H2)也可以添加至工艺气体66中。
图9示出了蚀刻中的中间结构。在开始蚀刻之后，源极/漏极区域242 中的锗与含硫气体形成硫化锗，诸如GeS或GeS2。聚合物生成气体进一步生成可以包含氟和碳的聚合物。硫化锗与聚合物的混合物使得在源极/漏极区域242的表面处形成聚合物层268。同时，聚合物生成气体使得在源极/ 漏极区域142上生成聚合物层168。由于硫化锗，聚合物层268的厚度T2 大于聚合物层168的厚度T1。聚合物层168和268具有减小源极/漏极区域 142和242的蚀刻速率的作用，并且较厚的聚合物层268使得源极/漏极区域242具有比源极/漏极区域142更低的蚀刻速率。根据本发明的一些实施例，可以将比率T2/T1调整为大于约1.5，大于约2.0或更高。在形成聚合物层168和268的同时，工艺气体66中的蚀刻气体(其可以是或可以不是聚合物生成气体)蚀刻源极/漏极区域142，并且可以略微地蚀刻源极/漏极区域242。在随后的讨论中，源极/漏极区域142的蚀刻速率表示为ER142，并且源极/漏极区域242的蚀刻速率表示为ER242。根据本发明的一些实施例，ER142大于ER242。
为了增加ER142和ER242之间的差值，降低蚀刻工艺中晶圆10的温度。降低温度可以使得聚合物层168和268在接触开口162和162的底部处的厚度减小，因此提高了区域142的蚀刻速率。由于聚合物层268比聚合物层168厚，因此当温度降低时比率T2/T1增加，因此蚀刻速率比率 ER142/ER242增加。实验结果表明，当晶圆10的温度(以及源极/漏极区域142和242的温度)为约50℃时，SiGe的蚀刻速率为约3.0nm/分钟，并且SiP的蚀刻速率为约9.2nm/分钟。当晶圆10的温度(以及源极/漏极区域142和242的温度)减小至低于20℃时，SiGe的蚀刻速率为约3.5nm/ 分钟，并且SiP的蚀刻速率为约18.7nm/分钟。这表明，随着晶圆温度的降低，SiP和SiGe之间的蚀刻速率差值显著增加。因此，根据一些实施例，使用低温来回蚀刻源极/漏极区域142，同时可以使源极/漏极区域242的回蚀刻最小化。根据本发明的一些实施例，调整(诸如降低)晶圆10的温度，使得比率ER142/ER242大于约1.5，并且可以大于2.0，大于约3.0或更高。例如，比率ER142/ER242可以在约2.0和约3.5之间的范围内。根据一些实施例，蚀刻期间采用的晶圆温度可以低于室温，并且低于约20℃。例如，根据一些实施例，晶圆10的温度可以在约0℃和约20℃之间的范围内或在约0℃和约15℃之间的范围内。根据本发明的一些实施例，通过冷却机构冷却晶圆10，例如，将冷却剂导入用于将晶圆10固定在其上的E卡盘中的导管中。
此外，在回蚀刻中，(工艺气体的等离子体的)低离子能量用于减小轰击效应，使得速率比率ER142/ER242增加。例如，离子能量可以小于约 0.5keV。在蚀刻中，可能生成SiF4和CO2气体，并且排空SiF4和CO2气体。
应该理解，源极/漏极区域142和源极/漏极区域242的蚀刻速率以及蚀刻速率比率ER142/ER242受多个结果影响参数影响，结果影响参数包括但不限于含硫气体、聚合物生成气体和蚀刻气体的每个的类型和流率、晶圆温度、源极/漏极区域142和242的组成(诸如锗浓度)和离子能量。因此，可以实施实验以调整结果影响参数以实现高比率ER142/ER242。在实验中，多个样品晶圆形成为具有与图8A相同的结构(或具有与区域142和242 具有相同组成的毯式半导体区域)。采用上述结果影响参数的不同组合来蚀刻样品晶圆并且找出对应的蚀刻速率和比率ER142/ER242。选择结果影响参数的组合，使得蚀刻速率和蚀刻速率比率可以具有期望的值。选择的结果影响参数的组合可以用于对生产的晶圆10实施回蚀刻。
图10A示出了完成回蚀刻时的晶圆10。根据一些实施例，凹槽170和 270形成为分别延伸至源极/漏极区域142和242内，其中，凹槽170和270 分别具有深度D2和D3。深度D2和D3可以具有大于约4nm的差值 (D2-D3)，该差值可以介于约4nm和约10nm之间。而且，深度D3尽可能小，并且可以小于约1.5nm。深度D3可以在约0.5nm和约1.5nm之间的范围内。深度D2可以大于约5nm，并且可以在约5nm和约12nm之间的范围内。
图10B示出了图10A所示的结构的截面图，其中，截面图从包含图10A 中的线10B1-10B1或线10B2-10B2的平面获得。因此，图10B中示出的结构可以是图10A中的器件区域100中所示的结构或器件区域200中所示的结构。产生的聚合物层168和268也在图10B中使用虚线示出。可以看出，聚合物层168和268在示出的区域48、164/264和142/242的顶面上较厚，并且在接触开口162/262中的侧壁上和深处较薄。
然后去除聚合物层168和268，产生图11所示的结构。聚合物层168 和268的去除可以使用干或湿工艺来实现。当使用干工艺时，可以使用N2和H2的混合气体。当使用湿工艺时，可以使用稀释的O3(在水中)溶液。可以去除硫化锗。根据本发明的一些实施例，由于扩散，在源极/漏极区域 242的顶面层中留下一些残留的硫，该顶面层面向凹槽270，并且在图11所示的截面中具有U形形状。
图12和图13示出了源极/漏极硅化物区域的形成。参照图12，例如使用物理汽相沉积(PVD)沉积金属层72(诸如钛层或钴层)。然后在金属层72上方形成阻挡层74，该阻挡层74可以是金属氮化物层，诸如氮化钛层或氮化钽层。相应的工艺示出为图21中示出的工艺流程300中的工艺 318。阻挡层74可以通过氮化金属层72的顶层，留下未氮化的金属层72 的底层来形成，或可以使用诸如CVD的沉积方法来形成。层72和74都是共形的，并且延伸至沟槽162/170和262/270内。
然后如图13所示，实施退火以形成源极/漏极硅化物区域176和276。相应的工艺示出为图21中示出的工艺流程300中的工艺320。可以通过快速热退火(RTA)、炉退火等实施退火。因此，金属层72的底部分别与源极/漏极区域142和242反应以形成硅化物区域176和276。在硅化工艺之后，金属层72的一些侧壁部分保留。根据本发明的一些实施例，硅化物区域176和276的顶面与相应的阻挡层74的底面接触。当某些残留的硫留在源极/漏极区域242的顶面层中时，产生的源极/漏极硅化物区域276中可以包括残留的硫。根据一些实施例，与源极/漏极硅化物区域276接触的下面的源极/漏极区域242的部分可以包括或可以不包括残留的硫。
图14和图15示出了阻挡层74的回拉。相应的工艺示出为图21中示出的工艺流程300中的工艺322。参照图14，形成牺牲层78。根据一些实施例，通过在晶圆10上用底部抗反射涂层(BARC)和光刻胶(未示出) 覆盖晶圆10的一些部分并且对光刻胶实施曝光和显影，从而去除光刻胶的位于示出的区域上方的部分来实施回拉。BARC用作牺牲层78。
下一步，如图15所示，回蚀刻牺牲层78，其中，剩余如图14所示的牺牲层78的底部。然后实施各向同性蚀刻工艺(可以是湿蚀刻工艺)，以去除阻挡层74和金属层72的顶部，留下由牺牲层78保护的底部未被蚀刻。剩余的阻挡层74的顶端高于硅化物区域176和276的顶端。阻挡层74的回拉有利于扩大开口162和262的顶端的尺寸，并且因此随后的金属填充更容易，并且减小了产生的源极/漏极接触插塞中形成空隙的可能性。在回拉之后，去除牺牲层78的剩余部分，产生图16所示的结构。
图17示出了额外的阻挡层80的形成。根据一些实施例，阻挡层80由氮化钛、氮化钽等形成。在图17中，未单独示出剩余的阻挡层74，而阻挡层74和80之间可以存在或可以不存在可区分的界面。
下一步，如图18所示，金属材料82沉积在阻挡层80上方并且与阻挡层80接触。金属材料82可以选自用于形成填充金属的备选材料的相同的组，并且可以包括钨或钴。然后实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除位于ILD 48上方的层72、80和82的部分。图19中示出了产生的结构，该结构包括源极/漏极接触插塞184和284。相应的工艺示出为图21中示出的工艺流程300中的工艺324。因此形成N型FinFET 186 和p型FinFET 286。
图20示出了蚀刻停止层88、ILD 90和接触插塞92的形成。根据一些实施例，接触插塞92包括穿过硬掩模160和260以接触栅电极158和258 的栅极接触插塞。
如图20所示，源极/漏极区域142的凹进使得n型FinFET 186的硅化物区域176除了底部之外还具有添加的侧壁部分。接触插塞184和硅化物区域176之间的接触电阻由于增加的接触面积而减小。另一方面，虽然回蚀刻源极/漏极区域242也可能使得面积增加，但是由于源极/漏极区域242 的重掺杂区域被不利地蚀刻，所以如果源极/漏极区域242也被回蚀刻，则 p型FinFET的整体性能可能受损。因此，源极/漏极区域242的回蚀刻保持最小以保持源极/漏极区域242的源极/漏极区域和对应接触件的总电阻较低。
在以上示出的实施例中，可以通过任何合适的方法来图案化鳍。例如，可以使用一种或多种光刻工艺(包括双重图案化或多重图案化工艺)来图案化鳍。通常，双重图案化或多重图案化工艺结合光刻和自对准工艺，从而允许创建具有例如比使用单一直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后可以使用剩余的间隔件或芯轴来图案化鳍。
本发明的实施例具有一些有利特征。通过采用可以选择性地蚀刻n型 FinFET的源极/漏极区域的蚀刻气体，n型FinFET可以具有增加的硅化物区域面积，并且因此减小接触电阻。另一方面，p型FinFET的源极/漏极区域的重掺杂部分的蚀刻保持最小，并且p型FinFET的源极/漏极区域的整体电阻没有受损。将n型和p型FinFET的源极/漏极区域暴露于相同的蚀刻气体而不掩蔽p型FinFET可以节省用于掩蔽p型FinFET的光刻工艺并且因此节省制造成本。
根据本发明的一些实施例，方法包括在第一源极/漏极区域和第二源极 /漏极区域上方形成层间电介质，其中，第一源极/漏极区域和第二源极/漏极区域分别是n型和p型；蚀刻层间电介质以形成第一接触开口和第二接触开口，其中，第一源极/漏极区域和第二源极/漏极区域分别暴露于第一接触开口和第二接触开口；引入工艺气体以同时回蚀刻第一源极/漏极区域和第二源极/漏极区域，其中，第一源极/漏极区域的第一蚀刻速率高于第二源极/漏极区域的第二蚀刻速率；以及在第一源极/漏极区域和第二源极/漏极区域上分别形成第一硅化物区域和第二硅化物区域。在实施例中，工艺气体包括：含硫气体；以及含碳和氟的气体。在实施例中，工艺气体还包括 HBr或Cl2。在实施例中，该方法还包括在引入工艺气体之前，将包括第一源极/漏极区域和第二源极/漏极区域的晶圆的温度调整为低于约20℃。在实施例中，第一源极/漏极区域包括硅并且不含锗，并且第二源极/漏极区域包括硅锗。在实施例中，第一蚀刻速率与第二蚀刻速率的比率高于约1.5。在实施例中，在蚀刻中，在第一源极/漏极区域上形成包含碳和氟的第一聚合物层，并且在第二源极/漏极区域上形成包含碳、氟、锗和硫的第二聚合物层。在实施例中，在蚀刻中，第一聚合物层的第一厚度与第二聚合物层的第二厚度的比率大于约2.0。在实施例中，该方法还包括在形成第一硅化物区域和第二硅化物区域之前去除第一聚合物层和第二聚合物层。
根据本发明的一些实施例，方法包括：在第一源极/漏极区域上方形成介电层；蚀刻介电层以形成第一接触开口，其中，第一源极/漏极区域的顶面暴露于第一接触开口；使用包括含硫气体和聚合物生成气体的工艺气体回蚀刻第一源极/漏极区域；以及在凹进的第一源极/漏极区域上生成第一硅化物区域。在实施例中，含硫气体包括SF6或氧硫化碳。在实施例中，含硫气体包括SF6。在实施例中，含硫气体包括氧硫化碳。在实施例中，第一源极/漏极区域是n型，并且该方法还包括：蚀刻介电层以形成第二接触开口，其中，第二源极/漏极区域的顶面暴露于第二接触开口并且第二源极/ 漏极区域是p型的并且当回蚀刻第一源极/漏极区域时暴露于工艺气体；以及在第二源极/漏极区域上生成第二硅化物区域。在实施例中，在回蚀刻第一源极/漏极区域时，第一源极/漏极区域的第一蚀刻速率与第二源极/漏极区域的第二蚀刻速率的比率大于约1.5。在实施例中，在回蚀刻第一源极/ 漏极区域时，调整第一源极/漏极区域的温度以实现该比率。
根据本发明的一些实施例，方法包括实施第一外延以形成用于n型 FinFET的第一源极/漏极区域；使用工艺气体回蚀刻第一源极/漏极区域，其中，工艺气体包括氧硫化碳和含碳和氟的气体，其中，回蚀刻生成从第一源极/漏极区域的顶面延伸至第一源极/漏极区域内的凹槽；以及在第一源极/漏极区域上形成第一硅化物区域，其中，第一硅化物区域包括底部和位于底部的相对端上方并且连接至底部的相对端的侧壁部分。在实施例中，工艺气体还包括被配置为回蚀刻第一源极/漏极区域的蚀刻气体。在实施例中，该方法还包括实施第二外延以形成用于p型FinFET的第二源极/漏极区域，其中，在回蚀刻中，第二源极/漏极区域暴露于工艺气体。在实施例中，该方法还包括在回蚀刻之前，将包括第一源/漏区域的晶圆的温度调整为低于约20℃，其中，在回蚀刻中，晶圆处于该温度。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成晶体管的方法，包括：
在第一源极/漏极区域和第二源极/漏极区域上方形成层间电介质，其中，所述第一源极/漏极区域和所述第二源极/漏极区域分别是n型和p型；
蚀刻所述层间电介质以形成第一接触开口和第二接触开口，其中，所述第一源极/漏极区域和所述第二源极/漏极区域分别暴露于所述第一接触开口和所述第二接触开口；
引入工艺气体以同时回蚀刻所述第一源极/漏极区域和所述第二源极/漏极区域，其中，所述第一源极/漏极区域的第一蚀刻速率高于所述第二源极/漏极区域的第二蚀刻速率，所述工艺气体用以在所述回蚀刻中在所述第一源极/漏极区域上产生第一聚合物层，所述第一聚合物层在所述第一源极/漏极区域的顶表面上比在所述第一源极/漏极区域的侧壁上厚；以及
在所述第一源极/漏极区域和所述第二源极/漏极区域上分别形成第一硅化物区域和第二硅化物区域。
2.根据权利要求1所述的方法，其中，所述工艺气体包括：
含硫气体；以及
含碳和氟的气体。
3.根据权利要求2所述的方法，其中，所述工艺气体还包括HBr或Cl2。
4.根据权利要求1所述的方法，还包括，在引入所述工艺气体之前，将包括所述第一源极/漏极区域和所述第二源极/漏极区域的晶圆的温度调整为低于20℃。
5.根据权利要求1所述的方法，其中，所述第一源极/漏极区域包括硅并且不含锗，并且所述第二源极/漏极区域包括硅锗。
6.根据权利要求1所述的方法，其中，所述第一蚀刻速率与所述第二蚀刻速率的比率高于1.5。
7.根据权利要求1所述的方法，其中，在所述蚀刻中，在所述第一源极/漏极区域上形成包含碳和氟的第一聚合物层，并且在所述第二源极/漏极区域上形成包含碳、氟、锗和硫的第二聚合物层。
8.根据权利要求7所述的方法，其中，在所述蚀刻中，所述第一聚合物层的第一厚度与所述第二聚合物层的第二厚度的比率大于2.0。
9.根据权利要求7所述的方法，还包括，在形成所述第一硅化物区域和所述第二硅化物区域之前去除所述第一聚合物层和所述第二聚合物层。
10.一种形成晶体管的方法，包括：
在第一源极/漏极区域上方形成介电层；
蚀刻所述介电层以形成第一接触开口，其中，所述第一源极/漏极区域的顶面暴露于所述第一接触开口；
使用包括含硫气体和聚合物生成气体的工艺气体回蚀刻所述第一源极/漏极区域，其中，所述含硫气体包括SF6或氧硫化碳，其中，所述聚合物生成气体用于在所述回蚀刻中在所述第一源极/漏极区域上产生第一聚合物层，所述第一聚合物层在所述第一源极/漏极区域的顶表面上比在所述第一源极/漏极区域的侧壁上厚；以及
在凹进的第一源极/漏极区域上生成第一硅化物区域。
11.根据权利要求10所述的方法，其中，所述第一源极/漏极区域是n型，并且在所述回蚀刻中，蚀刻p型源极/漏极的第二源极/漏极区域，其中，所述聚合物生成气体被配置为在所述第二源极/漏极区域上生成第二聚合物层，并且所述第二聚合物层比所述第一聚合物层厚。
12.根据权利要求10所述的方法，其中，所述含硫气体包括SF6。
13.根据权利要求10所述的方法，其中，所述含硫气体包括氧硫化碳。
14.根据权利要求10所述的方法，其中，所述第一源极/漏极区域是n型，并且所述方法还包括：
在第二源极/漏极区域上方形成所述介电层；
蚀刻所述介电层以形成第二接触开口，其中，所述第二源极/漏极区域的顶面暴露于所述第二接触开口，并且所述第二源极/漏极区域是p型并且当回蚀刻所述第一源极/漏极区域时暴露于所述工艺气体；以及
在所述第二源极/漏极区域上生成第二硅化物区域。
15.根据权利要求14所述的方法，其中，所述第一源极/漏极区域蚀刻在4nm和10nm之间的范围的第一深度，并且所述第二源极/漏极区域蚀刻在0.5nm和1.5nm之间的范围的第二深度。
16.根据权利要求14所述的方法，其中，在回蚀刻所述第一源极/漏极区域时，调整所述第一源极/漏极区域的温度以实现所述第一源极/漏极区域和所述第二源极/漏极区域的不同蚀刻速率。
17.一种形成晶体管的方法，包括：
实施第一外延以形成用于n型鳍式场效应晶体管的第一源极/漏极区域；
使用工艺气体回蚀刻所述第一源极/漏极区域，其中，所述工艺气体包括氧硫化碳和含碳和氟的气体，其中，所述回蚀刻生成从所述第一源极/漏极区域的顶面延伸至所述第一源极/漏极区域内的凹槽，其中，所述工艺气体用以在所述回蚀刻中在所述第一源极/漏极区域上产生第一聚合物层，所述第一聚合物层在所述第一源极/漏极区域的顶表面上比在所述第一源极/漏极区域的侧壁上厚；以及
在所述第一源极/漏极区域上形成第一硅化物区域，其中，所述第一硅化物区域包括底部和位于所述底部的相对端上方并且连接至所述底部的相对端的侧壁部分。
18.根据权利要求17所述的方法，其中，所述工艺气体还包括被配置为回蚀刻所述第一源极/漏极区域的蚀刻气体。
19.根据权利要求17所述的方法，还包括：
实施第二外延以形成用于p型鳍式场效应晶体管的第二源极/漏极区域，其中，在所述回蚀刻中，所述第二源极/漏极区域暴露于所述工艺气体。
20.根据权利要求17所述的方法，还包括，在所述回蚀刻之前，将包括所述第一源极/漏极区域的晶圆的温度调整为低于20℃，其中，在所述回蚀刻中，所述晶圆处于所述温度。
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