TWI736884B - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TWI736884B
TWI736884B TW108114842A TW108114842A TWI736884B TW I736884 B TWI736884 B TW I736884B TW 108114842 A TW108114842 A TW 108114842A TW 108114842 A TW108114842 A TW 108114842A TW I736884 B TWI736884 B TW I736884B
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source
drain region
forming
region
semiconductor device
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TW108114842A
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TW201946121A (zh
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張雲閔
陳建安
王冠人
鵬 王
陳煌明
林煥哲
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置的形成方法包括形成層間介電質於第一源極/汲極區域及第二源極/汲極區域之上，第一源極/汲極區域及第二源極/汲極區域分別為n型及p型。蝕刻層間介電質以形成第一接點開口及第二接點開口，第一接點開口及第二接點開口分別露出第一源極/汲極區域及第二源極/汲極區域。以製程氣體同時回蝕第一源極/汲極區域及第二源極/汲極區域，且第一源極/汲極區域的第一蝕刻速率高於第二源極/汲極區域的第二蝕刻速率。形成第一矽化物區以及第二矽化物區分別於第一源極/汲極區域及第二源極/汲極區域之上。

Description

半導體裝置的形成方法
本發明實施例係有關於一種半導體裝置，且特別有關於一種包括鰭狀場效電晶體(Fin Field-Effect Transistor，FinFet)的半導體裝置及其形成方法。
當積體電路的尺寸逐漸變小時，各自的形成製程也逐漸變得困難，傳統製程未發生問題的情況下也可能出現問題。例如，在鰭狀場效電晶體形成時，源極/汲極區域尺寸逐漸變小，使接點電阻逐漸變高。
本發明實施例包括一種半導體裝置的形成方法，包括：形成層間介電質於第一源極/汲極區域及第二源極/汲極區域之上，其中第一源極/汲極區域及第二源極/汲極區域分別為n型及p型；蝕刻層間介電質以形成第一接點開口及第二接點開口，第一接點開口及第二接點開口分別露出第一源極/汲極區域及第二源極/汲極區域；導入製程氣體以同時回蝕第一源極/汲極區域及第二源極/汲極區域，其中第一源極/汲極區域的第一蝕刻速率高於第二源極/汲極區域的第二蝕刻速率；以及形成第一矽化物區以及第二矽化物區分別於第一源極/汲極區域及第二源極/汲極區域之上。
本發明實施例亦包括一種半導體裝置的形成方法，包括：形成介電層於第一源極/汲極區域之上；蝕刻介電層以形成第一接點開口，第一接點開口露出第一源極/汲極區域的頂表面；使用包括含硫氣體及聚合物生成氣體的製程氣體回蝕第一源極/汲極區域，其中含硫氣體包括SF6 或氧硫化碳(carbon oxide sulfide)；以及產生第一矽化物區於凹蝕的第一源極/汲極區域之上。
本發明實施例又包括一種半導體裝置的形成方法，包括：進行第一磊晶以形成n型鰭狀場效電晶體(Fin Field-Effect transistor，FinFET)的第一源極/汲極區域；以製程氣體回蝕第一源極/汲極區域，其中製程氣體包括氧硫化碳(carbon oxide sulfide)及含碳及氟氣體，其中回蝕產生從第一源極/汲極區域的頂表面延伸入第一源極/汲極區域的凹蝕；以及形成第一矽化物區於第一源極/汲極區域之上，其中第一矽化物區包括底部及在底部相對端之上並連接至底部相對端的側壁部份。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本發明實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方，即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。
應理解的是，額外的操作步驟可實施於所述方法之前、之間或之後，且在所述方法的其他實施例中，部分的操作步驟可被取代或省略。
此外，其中可能用到與空間相對用詞，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相對用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係，這些空間相對用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
不同實施例提供了電晶體及其形成方法。根據一些實施例繪示出形成電晶體的中間階段，亦討論了一些實施例的一些變化。在各視圖及說明實施例中，使用相同的標號以表示相似的元件。在一些所示的實施例中，使用形成鰭狀場效電晶體為範例，解釋本發明實施例的概念。其他電晶體例如平面電晶體亦可採用本發明實施例的概念。
第1至20圖係根據一些實施例繪示出形成場效電晶體(例如可為鰭狀場效電晶體)中間階段的剖面圖及透視圖。第1至20圖所示的步驟亦示意性地反應於第21圖中的製程流程300之中。所形成的電晶體包括元件區域100中的第一電晶體及元件區域200中的第二電晶體。依據本發明實施例，元件區域100形成的元件為n型鰭狀場效電晶體，元件區域200形成的元件為p型鰭狀場效電晶體。
第1圖繪示出起始結構的透視圖。起始結構包括晶圓10，其更包括了基板20。基板20可為半導體基板，其可為矽基板、矽鍺基板、或其他半導體材料所形成的基板。根據一些實施例，基板20包括塊體矽基板及塊體矽基板上的磊晶矽鍺(silicon germanium，SiGe)層或鍺(germanium)層(其中無矽)。基板20可以p型或n型雜質摻雜。可形成隔離區域22例如淺溝槽隔離(Shallow Trench Isolation，STI)區域延伸入基板20。相鄰淺溝槽隔離區域22間的基板20部分稱為條狀半導體124及224，分別位於元件區域100及200中。
淺溝槽隔離區域22可包括氧化物襯層(未繪示)。氧化物襯層可由熱氧化基板20表面層所形成的熱氧化物形成。氧化物襯層亦可為例如以原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、或化學氣相沉積 (Chemical Vapor Deposition，CVD)沉積的氧化矽層。淺溝槽隔離區域22亦可包括氧化物襯層上的介電材料，其中介電材料可使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋轉塗佈、或類似製程形成。
參見第2圖，凹蝕淺溝槽隔離區域22，因此條狀半導體124及224的頂部突出高於相鄰淺溝槽隔離區域22的頂表面122A及222A，以形成突出鰭片124’及 224’。在第21圖所繪示的製程流程300中，相應製程繪示為製程302。蝕刻可以乾蝕刻進行，其中使用NH3 及NF3 為蝕刻氣體。在蝕刻過程中，可能產生用於蝕刻的電漿，亦可能包括氬氣(Argon)。在本發明其他實施例中，以濕蝕刻製程進行凹蝕淺溝槽隔離區域22。蝕刻化學品可例如包含稀釋的HF溶液。
參見第3圖，分別在突出的鰭片124’及224’的頂表面及側壁上形成虛置閘極堆疊130及230。在第21圖所繪示的製程流程300中，相應製程繪示為製程304。虛置閘極堆疊130可包括閘極介電質132及虛置閘極介電質132上的虛置閘極電極134。虛置閘極堆疊230可包括虛置閘極介電質232及虛置閘極介電質232上的虛置閘極電極234。虛置閘極電極134及234可以例如非晶矽或多晶矽形成，亦可能使用其他材料形成。每個虛置閘極堆疊130及230亦可能包含一(或多)層硬罩幕層136及236。硬罩幕層136及236可以氮化矽、碳氮化矽、或類似物形成。每個虛置閘極堆疊130及230中分別跨越單一或多個突出的鰭片124’及224’。虛置閘極堆疊130及230亦可能分別具有垂直於突出的鰭片124’及224’之長度方向的長度方向。
接著，分別形成閘極間隔物138及238於虛置閘極堆疊130及230的側壁上。同時，亦可能形成鰭片間隔物(未繪示)於突出的鰭片124’及224’的側壁上。根據本發明一些實施例，閘極間隔物138及238以介電材料例如矽碳氮氧化物(silicon carbon-oxynitride，SiCON)、氮化矽、或類似物形成，且可能為單層結構或包括多層介電層的多層結構。
根據一些實施例，每個閘極間隔物138包括第一介電層138A及第二介電層138B(未於第3圖繪示，參見第6B圖)。每一膜層138A及138B透過毯覆性沉積步驟形成，接著進行非等向性蝕刻步驟。根據一些實施例，介電層138A為低介電常數介電層，且介電層138B為非低介電常數介電層。介電層138A可以具有低於約3.0的介電常數(k值)的低介電常數介電材料形成，其可以由SiON或SiOCN形成，其中形成孔隙，以降低k值至想要的低介電常數值。介電層138B可例如由氮化矽形成。閘極間隔物238具有與閘極間隔物138相同的結構，並可包括分別與膜層138A及138B相同材料形成的膜層238A及238B(第6圖)。在一些其他的實施例中，介電層138A為非低介電常數介電層，且介電層138B為低介電常數介電層，且相應的低介電常數介電材料與非低介電常數介電材料與上述相似。採用低介電常數介電質可降低閘極電極與源極/汲極區域之間的寄生電容。
接著進行蝕刻步驟，以蝕刻突出的鰭片124’及224’未被虛置閘極堆疊130及230與閘極間隔物138及238覆蓋的突出的鰭片124’及224’的部分，產生如第4圖所繪示的結構。凹蝕可為非等向性的，而因此分別位於虛置閘極堆疊130/230及閘極間隔物138/238正下方的鰭片124’及224’受到保護，而不會被蝕刻。根據一些實施例，凹蝕的條狀半導體124及224的頂表面可低於相鄰的淺溝槽隔離區域22的頂表面。凹槽140及240相應形成於淺溝槽隔離區域22之間。凹蝕元件區域100及200可在共同的蝕刻製程中或在分開的蝕刻製程中進行，且凹槽140的深度可與凹槽240的深度相同或不同。
接著，從凹槽140及240選擇性地成長半導體材料，以形成磊晶區域(源極/汲極區域)，產生如第5圖所繪示的結構。在第21圖所繪示的製程流程300中，相應製程繪示為製程306。根據一些實施例，以矽磷(silicon phosphorous，SiP)或矽碳磷(silicon carbon phosphorous，SiCP)形成磊晶區域142，其為n型。當元件區域200中相應的電晶體為p型電晶體時，磊晶區域242可以摻雜硼的矽鍺(SiGeB)形成。磊晶區域242可包括具有較低鍺濃度的下層，以及具有較高濃度的上層。根據一些實施例，在具有較高鍺濃度的上層之上可能具有或可能沒有矽蓋層(不含鍺)。例如，下層可具有介於約百分之20至約百分之40的鍺原子百分比，且上層可具有介於約百分之40至約百分之75鍺原子百分比。
形成磊晶區域142及242在分開的製程中進行，並使用不同罩幕(未繪示)。在另外的實施例中，以III-V族化合物半導體例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、上述之組合、或上述之多層形成磊晶區域142及242。在凹槽140及240填入磊晶半導體材料之後，進一步磊晶成長磊晶區域142及242，造成磊晶區域142及242水平擴展，並形成晶面(facets)。從相鄰凹槽成長的磊晶區域可能合併以形成大的磊晶區域，或可能在未合併時保持為分開的磊晶區域。磊晶區域142及242分別形成電晶體的源極/汲極區域。
第6A圖繪示出沉積接點蝕刻停止層(Contact Etch Stop Layer，CESL)46及層間介電質(Inter-Layer Dielectric，ILD)48的透視圖。在第21圖所繪示的製程流程300中，相應製程繪示為製程308。在一些實施例中，以氮化矽、碳氮化矽、或類似物形成接點蝕刻停止層46。可以順應性的沉積方法例如原子層沉積或化學氣相沉積形成接點蝕刻停止層46。形成層間介電層48於接點蝕刻停止層46之上，並可使用例如可流動化學氣相沉積、旋轉塗佈、化學氣相沉積、或類似製程形成。層間介電層48可以磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、硼摻雜的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG) 、四乙氧基矽烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、或類似物形成。可進行平坦化製程例如化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械研磨(mechanical grinding)製程以使層間介電層48、虛置閘極堆疊130及230、及閘極間隔物138及238的頂表面彼此齊平。
第6B圖繪示出第6A圖中結構的剖面圖，剖面圖是從第6A圖中包括線段A-A的垂直面及包括線段B-B的垂直面所獲得的。在第6A及6B圖中所示的結構形成之後，虛置閘極堆疊130及230包括硬罩幕層136及236、虛置閘極電極134及234、及虛置閘極介電質132及232被金屬閘極及替換閘極介電質取代。在第6B圖及後續的剖面圖中，繪示出淺溝槽隔離區域22的頂表面122A及222A，及分別突出高於頂表面122A及222A的突出的鰭片124’及224’。
為形成替換閘極，透過蝕刻移除第6A及6B圖所繪示的硬罩幕層136及236、虛置閘極電極134及234、及虛置閘極介電質132及232，在閘極間隔物138之間及閘極間隔物238之間形成溝槽。突出的鰭片124’及224’的頂表面及側壁因此露出於所得的溝槽。第7A及7B圖繪示出在移除虛置閘極堆疊所留下的溝槽中形成替換閘極堆疊150及250及硬罩幕160及260後的晶圓10部分的透視圖及剖面圖。在第21圖所繪示的製程流程300中，相應製程繪示為製程310。在一些實施例中，如第7B圖所示，閘極介電質152及252分別包括界面層(Interfacial Layers，ILs)154及254以及位於其上的高介電常數介電質156及256。界面層154及254分別形成於突出的鰭片124’及224’露出的表面。每個界面層154及254可包括氧化層例如氧化矽層，透過熱氧化突出的鰭片124’及224’的表面層、化學氧化製程、或沉積製程形成。
第7B圖亦繪示出閘極介電質152及252可包括分別形成於界面層154及254之上的高介電常數介電層156及256。高介電常數介電層156及256可包括高介電常數介電材料例如氧化鉿(hafnium oxide)、氧化鑭(lanthanum oxide)、氧化鋁(aluminum oxide)、氧化鋯(zirconium oxide)、氮化矽、或其類似物。高介電常數介電材料的介電常數(k值)高於3.9，且可能高於約7.0。高介電常數介電層156及256以順應性的膜層形成，且延伸於突出的鰭片124’及224’的側壁之上及閘極間隔物138及238的側壁之上。在一些實施例中，以原子層沉積或化學氣相沉積形成高介電常數介電層156及256。
閘極電極158及258(第7B圖)可包括複數層堆疊的導電子層。形成閘極電極158及258可以順應性的沉積方法例如原子層沉積或化學氣相沉積進行，因此閘極電極158及258的下部子層垂直部分的厚度及水平部分的厚度大抵上彼此相等。
閘極電極158及258可分別包括金屬層158A及258A，各自包括擴散阻障層及擴散阻障層之上的一層(或多層)功函數層(未分別繪示)。擴散阻障層可以氮化鈦(titanium nitride，TiN)形成，其可(或可不)摻雜矽。功函數層決定閘極的功函數，並包括至少一層，或由不同材料形成的多層。根據相對應的鰭狀場效電晶體為n型鰭狀場效電晶體或p型鰭狀場效電晶體來選擇功函數層的材料。例如，(n型鰭狀場效電晶體的)金屬層158A中可包括TaN層及TaN層之上的鈦鋁(titanium aluminum，TiAl)層。(p型鰭狀場效電晶體的)金屬層258A中可包括TaN層、TaN層之上的TiN層、及TiN層上的TiAl層。在沉積功函數層之後，形成阻障層，其可能為另一TiN層。
閘極電極158及258亦可包括相應的填充金屬158B及258B填充於未被下方子層所填充的剩餘溝槽。填充金屬可例如以鎢或鈷形成。在形成填充金屬之後，進行平坦化製程例如化學機械研磨製程或機械研磨製程，因此移除了層間介電層48之上膜層152/252及158/258部分。以下將閘極介電質152/252及閘極電極158/258的剩餘部分統稱為替換閘極150及250。
在一些實施例中，接著形成自對準硬罩幕160及260。自對準硬罩幕160及260與下方的替換閘極150及250自對準，並以例如ZrO2 、Al2 O3 、SiON、SiCN、SiO2 、或類似物之介電材料形成，且可能不含SiN。形成製程可包括蝕刻替換閘極150及250以形成凹槽，填充介電材料於凹槽之中，並進行平坦化製程以移除介電材料的多餘部分。硬罩幕160及260、閘極間隔物138及238、接點蝕刻停止層46、及層間介電層48的頂表面此時可大抵共平面。
參見第8A及8B圖，蝕刻層間介電層48及接點蝕刻停止層46以形成源極/汲極接點開口162及262。在第21圖所繪示的製程流程300中，相應製程繪示為製程312。接點蝕刻停止層46做為蝕刻層間介電層48的蝕刻停止層，然後接著蝕刻接點蝕刻停止層46，露出下方的源極/汲極區域142及242。可同時形成或可分別形成接點開口162及262。第8B圖繪示出第8A圖中包括線段A-A及B-B的垂直面的剖面圖。由於過度蝕刻，如第8B圖所繪示，開口162及262可略微延伸入源極/汲極區域142及242，例如深度D1小於約5nm。
亦參見第8B圖，在形成接點開口162及262之後，形成接點間隔物164及264於源極/汲極區域142及242、接點蝕刻停止層46、及層間介電層48的側壁上。在第21圖所繪示的製程流程300中，相應製程繪示為製程314。形成接點間隔物164及264可包括形成介電層，並接著進行非等向性蝕刻以移除介電層的水平部分，留下垂直部分做為接點間隔物。在一些實施例中，以順應性的沉積方法例如原子層沉積或化學氣相沉積形成介電層。介電層可為高介電常數介電層，其k值大於3.9，因此其具有良好的隔離能力。候選材料包括Alx Oy 、HfO2 、及SiOCN(內部無孔洞或大抵無孔洞)，且在後續回蝕源極/汲極區域使用CF4 或類似氣體時，可不含SiN。介電層的厚度可介於例如約2nm至約6nm的範圍。從晶圓10的上方看時，每個接點間隔物164及264可形成環狀物。在一些其他實施例中，省略形成接點間隔物164及264。
第8C圖繪示出元件區域100及200中任一結構的剖面圖，其中剖面圖係由第8A圖中跨過線段C1-C1或線段C2-C2所得到的。第8C圖所繪示的剖面圖亦由第8B圖中包括線段8C1-8C1或8C2-8C2的平面所獲得的。
第9至11圖繪示出回蝕源極/汲極區域142。在第21圖所繪示的製程流程300中，相應製程繪示為製程316。在一些實施例中，在回蝕中，源極/汲極區域142及242兩者暴露於相同的製程氣體，以節省製程成本，而因此源極/汲極區域142及242兩者均經受蝕刻。所得的n型FinFET的n型源極/汲極區域142回蝕可增加接點面積，將於後續段落討論。因此，接點插塞至源極/汲極區域142的接點電阻降低，改善了元件性能。另一方面，意圖最小化回蝕所得的p型FinFET的p型源極/汲極區域242。這是因為難以使用p型摻質例如硼重摻雜整個源極/汲極區域242。因此，源極/汲極區域242的頂表面層為重摻雜，而下方膜層相對於頂表面層較輕摻雜。例如，源極/汲極區域242的頂表面層可具有高於約1x1020 /cm3 ，或介於約1x1020 /cm3 至約1x1022 /cm3 的p型或n型摻質濃度。下方膜層的摻質濃度可能相較頂表面層的摻質濃度低了一至兩個數量級。例如，下方膜層的摻質濃度可介於1x1018 /cm3 至約1x1020 /cm3 。因此，不希望頂表面層在回蝕中被蝕刻，以保持p型源極/汲極區域242的重摻雜頂表面層導致的高導電性。
根據一些實施例，蝕刻氣體如箭頭66所示，包括含硫氣體、聚合物生成氣體、及蝕刻源極/汲極區域142的蝕刻氣體。根據一些實施例，聚合物生成氣體及蝕刻氣體可為相同氣體。含硫氣體可包括SF6 、羰基硫(carbonyl sulfide，COS, 亦稱為氧硫化碳)、或類似物。聚合物生成氣體可包括Cx Hy Fz ，其中x、y、及z為整數。例如，聚合物生成氣體可包括CF4 (其中x=1、y=0、及z=4)、CH3 F、CH2 F2 、或類似物。蝕刻氣體可包括Cx Hy Fz 、HBr、Cl2 、及/或相似物。因此，當添加或不添加另外的蝕刻氣體時，Cx Hy Fz 可以做為聚合物生成氣體及蝕刻氣體。亦可添加氫(Hydrogen，H2 )於製程氣體 66中。
第9圖繪示出蝕刻中的中間結構。在蝕刻開始之後，源極/汲極區域242中的鍺與含硫氣體形成硫化鍺例如GeS或GeS2 。聚合物生成氣體進一步導致產生聚合物，其可包含氟和碳。硫化鍺及聚合物的混合物導致在源極/汲極區域242的表面形成聚合物層268。同時，聚合物生成氣體導致在源極/汲極區域142上產生聚合物層168。由於硫化鍺的緣故，聚合物層268的厚度T2大於聚合物層168的厚度T1。聚合物層168及268具有降低源極/汲極區域142及242蝕刻速率的效果，較厚的聚合物層 268導致源極/汲極區域242比源極/汲極區域 142具有較低的蝕刻速率。根據一些實施例，可調整比值T2/T1大於約1.5、大於約2.0，或更高。在聚合物層168及268形成的同時，製程氣體 66中的蝕刻氣體(可能是或可能不是聚合物生成氣體)蝕刻源極/汲極區域142，並可能略微蝕刻源極/汲極區域242。在後續的討論中，源極/汲極區域 142的蝕刻速率表示為ER142，且源極/汲極區域 242的蝕刻速率表示為ER242。根據一些實施例，ER142大於ER242。
為增加ER142與ER242的差異，降低蝕刻中晶圓10的溫度。降低溫度可導致接點開口162及262底部聚合物層168及268的厚度減少，因此改善區域142的蝕刻速率。由於聚合物層 268比聚合物層 168厚，當溫度下降時，比值T2/T1增加，因此蝕刻速率比值ER142/ER242增加。實驗數據顯示當晶圓10(以及源極/汲極區域142及242的溫度)約為50°C時，SiGe的蝕刻速率約為3.0nm/分鐘，且SiP的蝕刻速率約為9.2nm/分鐘。當晶圓10(以及源極/汲極區域142及242的溫度)降為低於20°C時，SiGe的蝕刻速率約為3.5nm/分鐘，且SiP的蝕刻速率約為18.7nm/分鐘。這顯示當晶圓溫度降低時，SiP和SiGe的蝕刻速率的差異顯著增加。因此，在一些實施例中，使用低溫以回蝕源極/汲極區域 142，同時可最小化源極/汲極區域242的回蝕。根據一些實施例，可調整(例如降低)晶圓10的溫度以致比值ER142/ER242大於約1.5，且可大於2.0，大於約3.0，或更高。例如，比值ER142/ER242可在約2.0至約3.5的範圍之內。根據一些實施例，蝕刻時採用的晶圓溫度可低於室溫，且低於約20°C。例如，根據一些實施例，晶圓10的溫度可介於約0°C至約20°C的範圍中，或介於約0°C至約15°C。根據一些實施例，經由冷卻機制冷卻晶圓10，例如，將冷卻劑導入固定晶圓10於其上的靜電夾盤中的導管中。
此外，在回蝕中，使用低離子能量(的製程氣體電漿)以減少轟擊效應，因此增加了速率比值ER142/ER242。例如，離子能量可小於約0.5keV。在蝕刻中，可能產生SiF4 及CO2 ，且將其抽空。
可理解的是，源極/汲極區域 142及源極/汲極區域 242的蝕刻速率，以及蝕刻速率比值ER142/ER242受多個影響結果的參數影響，包括但不限於每一含硫氣體、聚合物生成氣體、蝕刻氣體的種類及流速、晶圓溫度、源極/汲極區域142及242的成分(例如鍺濃度)、以及離子能量。因此，可進行實驗以調整影響結果的參數以達到高比值ER142/ER242。在實驗中，形成多個具有與第8A圖相同結構(或具有與區域142及242相同組成的毯覆半導體區域)的樣品晶圓。採用上述影響結果的參數的不同組合來蝕刻樣品晶圓並找到相對應的蝕刻速率以及比值ER142/ER242。選擇影響結果的參數的組合，使得蝕刻速率及蝕刻速率比值可具有期望的值。可使用選定的影響結果的參數的組合進行量產晶圓10的回蝕。
第10A圖繪示出回蝕完成時的晶圓10。根據一些實施例，形成凹槽170及270個別延伸入源極/汲極區域142及242，凹槽170及270分別具有深度D2及D3。深度D2及D3可具有大於約4nm的差異(D2-D3)，其可在約為4nm至約10nm之間。此外，深度D3越小越好，且可小於約1.5nm。深度D3在約為0.5nm至約1.5nm之間的範圍。深度D2可大於約5nm，且可在約為5nm至約12nm之間的範圍。
第10B圖繪示出如第10A圖所繪示結構的剖面圖，係由第10A圖中包含線段10B1-10B1或線段10B2-10B2所獲得的剖面圖。因此，第10B圖中繪示的結構可為第10A圖中元件區域100中所繪示的結構或元件區域200中所繪示的結構。所得的聚合物層168及268亦以虛線繪示於第10B圖中。可觀察到聚合物層168及268在所繪示區域48、164/264、及142/242的頂表面上較厚，且在接點開口162/262的側壁及深處較薄。
接著移除聚合物層168及268，得到如第11圖所繪示的結構。移除聚合物層168及268可以乾或濕製程達成。當使用乾製程時，可使用N2 和H2 的混合氣體。當使用濕製程時，可使用(在水中)稀釋的O3 溶液。可移除硫化鍺。在一些實施例中，由於擴散，一些殘留的硫餘留於源極/汲極區域242的頂表面，其頂表面面向凹槽270，且如第11圖所繪示，具有U型剖面。
第12及13圖繪示出形成源極/汲極矽化物區。參見第12圖，以例如物理氣相沉積(Physical Vapor Deposition，PVD)沉積金屬層72(例如鈦層或鈷層)。阻障層74，其可為氮化金屬層例如氮化鈦或氮化鉭層，接著形成於金屬層72之上。在第21圖所繪示的製程流程300中，相應製程繪示為製程318。可氮化金屬層72的頂層而形成阻障層74，留下未氮化的金屬層72的底層，或是以沉積方式例如化學氣相沉積形成阻障層74。膜層72和74均為順應性的，且延伸入溝槽162/170及262/270。
如第13圖所繪示，接著進行退火以形成源極/汲極矽化物區176及276。在第21圖所繪示的製程流程300中，相應製程繪示為製程320。退火可透過快速熱退火(Rapid Thermal Anneal，RTA)、爐管退火、或相似製程進行。因此，金屬層72的底部與源極/汲極區域 142及242反應以分別形成矽化物區176及276。在矽化製程之後，金屬層72的一些側壁部分殘留。在一些實施例中，矽化物區176及276的頂表面接觸相應阻障層74的底表面。當一些殘留的硫留在源極/汲極區域242的頂表面中時，所得的源極/汲極矽化物區276可包括其中的殘餘硫。根據一些實施例，與源極/汲極矽化物區276接觸的源極/汲極區域242之底部可包括或可不包括殘餘硫。
第14及15圖繪示出內縮阻障層74。在第21圖所繪示的製程流程300中，相應製程繪示為製程322。參見第14圖，形成犧牲層78。根據一些實施例，透過在晶圓10上以底部抗反射層(Bottom Anti-Reflective Coating，BARC)及光阻(未繪示)覆蓋晶圓10進行內縮，並在光阻上進行曝光及顯影，因此在所繪示區域上的光阻部分被移除。底部抗反射層做為犧牲層78。
接著，如第15圖所示，蝕刻犧牲層78，餘留如第14圖所示的犧牲層78底部。接著進行等向性蝕刻製程，其可為濕蝕刻製程，以移除阻障層74及金屬層72的頂部，留下受犧牲層78保護而未蝕刻的底部。餘留的阻障層74頂端高於矽化物區176及276的頂端。內縮阻障層74有利於擴大開口162及262的尺寸，而因此後續填充金屬較容易，且減少了所得的源極/汲極接點插塞中形成孔洞的可能性。在內縮之後，移除犧牲層78的剩餘部分，得到如第16圖所繪示的結構。
第17圖繪示出形成額外的阻障層80。根據一些實施例，阻障層80以氮化鈦、氮化鉭、或類似物形成。在第17圖中，未單獨繪示餘留的阻障層74，雖然阻障層74及80可能存在或可能不存在可區分的界面。
接著，如第18圖所繪示，沉積金屬材料82於阻障層80上，並接觸阻障層80。金屬材料82可選自與形成含金屬材料60相同的候選材料組合，且可包括鎢或鈷。接著進行平坦化製程例如化學機械研磨製程或機械研磨製程以移除層間介電層48上的部分膜層72、80、及82。所得的結構繪示於第19圖中，其包括源極/汲極接點插塞184及284。在第21圖所繪示的製程流程300中，相應製程繪示為製程324。因而形成n型鰭狀場效電晶體186及p型鰭狀場效電晶體286。
第20圖繪示出形成蝕刻停止層88、層間介電層90、及接點插塞92。根據一些實施例，接點插塞92包括穿透硬罩幕160及260至接點閘極電極158及258的閘極接點插塞。
如第20圖所示，凹蝕源極/汲極區域 142導致n型鰭狀場效電晶體186的矽化物區176中除了底部之外還具有額外的側壁部。由於接點面積增加，接點插塞184和矽化物區176之間的接點電阻降低。另一方面，雖然回蝕源極/汲極區域 242亦可導致增加面積，由於源極/汲極區域 242的重摻雜區受到不利蝕刻，若源極/汲極區域242亦被回蝕，可能損害p型鰭狀場效電晶體的整體效能。因此，保持最小化源極/汲極區域 242的回蝕，以維持源極/汲極區域 242的源極/汲極區域及相對應接點的整體電阻是低的。
在上述實施例中，可以任何適合的方式圖案化鰭片。例如，可以一或多道微影製程圖案化鰭片，包括雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合了微影及自對準製程，允許所創造出的圖案具有例如比單一直接微影製程所得的更小的節距。例如，在一實施例中，形成犧牲層於基板上，且以微影製程圖案化。使用自對準製程在圖案化的犧牲層旁形成間隔物。接著移除犧牲層，且可接著用餘留的間隔物或心軸以圖案化鰭片。
本發明實施例具有一些優點。採用可選擇性的蝕刻n型鰭狀場效電晶體的源極/汲極區域，n型鰭狀場效電晶體可增加矽化物區的面積，且因此降低接點電阻。另一方面，最小化p型鰭狀場效電晶體的源極/汲極區域的重摻雜區域，p型鰭狀場效電晶體的整體電阻不受損害。將n型和p型鰭狀場效電晶體的源極/汲極區域露出於相同蝕刻氣體，而不遮蔽p型鰭狀場效電晶體可節省遮蔽p型鰭狀場效電晶體的微影製程，而因此節省製造成本。
根據一些實施例，一種半導體裝置的形成方法包括：形成層間介電質於第一源極/汲極區域及第二源極/汲極區域之上，其中第一源極/汲極區域及第二源極/汲極區域分別為n型及p型；蝕刻層間介電質以形成第一接點開口及第二接點開口，第一接點開口及第二接點開口分別露出第一源極/汲極區域及第二源極/汲極區域；導入製程氣體以同時回蝕第一源極/汲極區域及第二源極/汲極區域，其中第一源極/汲極區域的第一蝕刻速率高於第二源極/汲極區域的第二蝕刻速率；以及形成第一矽化物區以及第二矽化物區分別於第一源極/汲極區域及第二源極/汲極區域之上。在一實施例中，製程氣體包括：含硫氣體；以及含碳及氟氣體。在一實施例中，製程氣體更包括HBr或Cl2 。在一實施例中，半導體裝置的形成方法更包括：導入製程氣體前，調整包括第一源極/汲極區域及第二源極/汲極區域之晶圓的溫度至低於約20°C。在一實施例中，第一源極/汲極區域包括矽且不含鍺(germanium)，且第二源極/汲極區域包括矽鍺(silicon germanium)。在一實施例中，第一蝕刻速率與第二蝕刻速率的比例高於約1.5。在一實施例中，在蝕刻中，第一聚合物層包括碳與氟形成於第一源極/汲極區域之上，且第二聚合物層包括碳、氟、鍺、及硫形成於第二源極/汲極區域之上。在一實施例中，在蝕刻中，第一聚合物層的第一厚度與第二聚合物層的第二厚度的比例高於約2.0。在一實施例中，半導體裝置的形成方法更包括：在第一矽化物區及第二矽化物區形成之前，移除第一聚合物層及第二聚合物層。
根據一些實施例，一種半導體裝置的形成方法包括：形成介電層於第一源極/汲極區域之上；蝕刻介電層以形成第一接點開口，第一接點開口露出第一源極/汲極區域的頂表面；使用包括含硫氣體及聚合物生成氣體的製程氣體回蝕第一源極/汲極區域，其中含硫氣體包括SF6 或氧硫化碳(carbon oxide sulfide)；以及產生第一矽化物區於凹蝕的第一源極/汲極區域之上。在一實施例中，第一源極/汲極區域為n型，且聚合物生成氣體用以在回蝕中產生第一聚合物層於第一源極/汲極區域之上，且在回蝕中，蝕刻p型源極/汲極的第二源極/汲極區域，聚合物生成氣體用以產生第二聚合物層於第二源極/汲極區域之上，且第二聚合物層比第一聚合物層厚。在一實施例中，含硫氣體包括SF6 或氧硫化碳(carbon oxide sulfide)。在一實施例中，含硫氣體包括SF6 。在一實施例中，含硫氣體包括氧硫化碳(carbon oxide sulfide)。在一實施例中，第一源極/汲極區域為n型，且半導體裝置的形成方法更包括：形成介電層於第二源極/汲極區域之上；蝕刻介電層以形成第二接點開口，第二接點開口露出第二源極/汲極區域的頂表面，且第二源極/汲極區域為p型，且在回蝕第一源極/汲極區域時第二源極/汲極區域暴露於製程氣體；以及產生第二矽化物區於第二源極/汲極區域之上。在一實施例中，在回蝕第一源極/汲極區域中，第一源極/汲極區域的第一蝕刻速率與第二源極/汲極區域的第二蝕刻速率的比例高於約1.5。在一實施例中，以介於約4nm至約10nm範圍的第一深度蝕刻第一源極/汲極區域，且以介於約0.5nm至約1.5nm範圍的第二深度蝕刻第二源極/汲極區域。在一實施例中，在回蝕第一源極/汲極區域中，調整第一源極/汲極區域的溫度以達到此比例。
根據一些實施例，一種半導體裝置的形成方法包括：進行第一磊晶以形成n型鰭狀場效電晶體(Fin Field-Effect transistor，FinFE T)的第一源極/汲極區域；以製程氣體回蝕第一源極/汲極區域，其中製程氣體包括氧硫化碳(carbon oxide sulfide)及含碳及氟氣體，其中回蝕產生從第一源極/汲極區域的頂表面延伸入第一源極/汲極區域的凹蝕；以及形成第一矽化物區於第一源極/汲極區域之上，其中第一矽化物區包括底部及在底部相對端之上並連接至底部相對端的側壁部份。在一實施例中，製程氣體更包括用以回蝕第一源極/汲極區域的蝕刻氣體。在一實施例中，半導體裝置的形成方法更包括：進行第二磊晶以形成p型鰭狀場效電晶體的第二源極/汲極區域，其中於回蝕中，第二源極/汲極區域暴露於製程氣體。在一實施例中，半導體裝置的形成方法更包括：在回蝕之前，調整包括第一源極/汲極區域之晶圓的溫度至低於約20°C，其中在回蝕中，晶圓為此溫度。
前述內文概述了許多實施例的特徵部件，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。另外，雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，且並非所有優點都已於此詳加說明。
10‧‧‧晶圓20‧‧‧基板22‧‧‧隔離區域46‧‧‧接點蝕刻停止層48‧‧‧層間介電質66‧‧‧箭頭(蝕刻氣體)72‧‧‧金屬層74‧‧‧阻障層78‧‧‧犧牲層80‧‧‧阻障層82‧‧‧金屬材料88‧‧‧蝕刻停止層90‧‧‧層間介電層92‧‧‧接點插塞100、200‧‧‧元件區域124、224‧‧‧條狀半導體122A、222A‧‧‧頂表面124’、224’‧‧‧突出鰭片130、230‧‧‧虛置閘極堆疊132、232‧‧‧虛置閘極介電質134、234‧‧‧虛置閘極電極136、236‧‧‧硬罩幕層138、238‧‧‧閘極間隔物138A、238A‧‧‧第一介電層138B、238B‧‧‧第二介電層140、240‧‧‧凹槽142、242‧‧‧磊晶源極/汲極區域150、250‧‧‧替換閘極堆疊152、252‧‧‧閘極介電質154、254‧‧‧界面層156、256‧‧‧高介電常數介電質158、258‧‧‧閘極電極158A、258A‧‧‧金屬層158B、258B‧‧‧填充金屬160、260‧‧‧硬罩幕162、262‧‧‧接點開口164、264‧‧‧接點間隔物168、268‧‧‧聚合物層170、270‧‧‧凹槽176、276‧‧‧矽化物區186‧‧‧n型鰭狀場效電晶體286‧‧‧p型鰭狀場效電晶體300‧‧‧製程流程302、304、306、308、310、312、314、316、318、320、322、324‧‧‧製程A-A、B-B、C1-C1、C2-C2、8C1-8C1、8C2-8C2、10B1-10B1、10B2-10B2‧‧‧線段D1、D2、D3‧‧‧深度T1、T2‧‧‧厚度
以下將配合所附圖式詳述本發明實施例。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地表現出本發明實施例的技術特徵。 第1-5、6A-6B、7A-7B、8A-8C、9、10A-10B、11-20圖係根據一些實施例繪示出形成n型鰭狀場效電晶體及p型鰭狀場效電晶體中間階段的剖面圖及透視圖。 第21圖係根據一些實施例繪示出形成鰭狀場效電晶體的製程流程圖。
10‧‧‧晶圓
20‧‧‧基板
46‧‧‧接點蝕刻停止層
48‧‧‧層間介電質
66‧‧‧箭頭(蝕刻氣體)
100、200‧‧‧元件區域
122A、222A‧‧‧頂表面
124’、224’‧‧‧突出鰭片
138、238‧‧‧閘極間隔物
142、242‧‧‧磊晶源極/汲極區域
150、250‧‧‧替換閘極堆疊
152、252‧‧‧閘極介電質
154、254‧‧‧界面層
156、256‧‧‧高介電常數介電質
158、258‧‧‧閘極電極
158A、258A‧‧‧金屬層
158B、258B‧‧‧填充金屬
160‧‧‧硬罩幕
162、262‧‧‧接點開口
164、264‧‧‧接點間隔物
168、268‧‧‧聚合物層
T1、T2‧‧‧厚度

Claims (15)

  1. 一種半導體裝置的形成方法，包括：形成一層間介電質於一第一源極/汲極區域及一第二源極/汲極區域之上，其中該第一源極/汲極區域及該第二源極/汲極區域分別為n型及p型；蝕刻該層間介電質以形成一第一接點開口及一第二接點開口，該第一接點開口及該第二接點開口分別露出該第一源極/汲極區域及該第二源極/汲極區域；導入一製程氣體以同時回蝕該第一源極/汲極區域及該第二源極/汲極區域以在該第一源極/汲極區域及該第二源極/汲極區域分別形成一第一凹槽及一第二凹槽，其中該第一源極/汲極區域的一第一蝕刻速率高於該第二源極/汲極區域的一第二蝕刻速率，其中該製程氣體用以在該回蝕中產生一第一聚合物層於該第一源極/汲極區域之上，該第一聚合物層在該第一源極/汲極區域的一頂表面上比在該第一源極/汲極區域的一側壁上厚；以及形成一第一矽化物區以及一第二矽化物區分別於該第一源極/汲極區域及該第二源極/汲極區域之上。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該製程氣體包括：一含硫氣體；以及一含碳及氟氣體。
  3. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該第一源極/汲極區域包括矽且不含鍺(germanium)，且該第二源極/汲極區域包括矽鍺(silicon germanium)。
  4. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該第一蝕刻速率與該第二蝕刻速率的一比例高於約1.5。
  5. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中在 該蝕刻中，一第一聚合物層包括碳與氟，形成於該第一源極/汲極區域之上，且一第二聚合物層包括碳、氟、鍺、及硫，形成於該第二源極/汲極區域之上。
  6. 如申請專利範圍第5項所述之半導體裝置的形成方法，更包括：在形成該第一矽化物區及該第二矽化物區之前，移除該第一聚合物層及該第二聚合物層。
  7. 一種半導體裝置的形成方法，包括：形成一介電層於一第一源極/汲極區域及一第二源極/汲極區域之上，其中該第一源極/汲極區域為n型，該第二源極/汲極區域為p型；蝕刻該介電層以形成一第一接點開口及一第二接點開口，該第一接點開口露出該第一源極/汲極區域的一頂表面，該第二接點開口露出該第二源極/汲極區域的一頂表面；使用包括一含硫氣體及一聚合物生成氣體的一製程氣體同時回蝕該第一源極/汲極區域與該第二源極/汲極區域以產生一第一凹槽與一第二凹槽，其中該含硫氣體包括SF6或氧硫化碳(carbon oxide sulfide)，其中該聚合物生成氣體用以在該回蝕中產生一第一聚合物層於該第一源極/汲極區域之上，該第一聚合物層在該第一源極/汲極區域的一頂表面上比在該第一源極/汲極區域的一側壁上厚；以及產生一第一矽化物區於凹蝕的該第一源極/汲極區域之上。
  8. 如申請專利範圍第7項所述之半導體裝置的形成方法，其中在該回蝕中，該聚合物生成氣體用以產生一第二聚合物層於該第二源極/汲極區域之上，且該第二聚合物層比該第一聚合物層厚。
  9. 如申請專利範圍第7項所述之半導體裝置的形成方法，其中該第一源極/汲極區域為n型，且該方法更包括：在回蝕該第一源極/汲極區域時，該第二源極/汲極區域暴露於該製程氣體； 以及產生一第二矽化物區於該第二源極/汲極區域之上。
  10. 如申請專利範圍第9項所述之半導體裝置的形成方法，其中以介於約4nm至約10nm範圍的一第一深度蝕刻該第一源極/汲極區域，且以介於約0.5nm至約1.5nm範圍的一第二深度蝕刻該第二源極/汲極區域。
  11. 如申請專利範圍第9項所述之半導體裝置的形成方法，其中該回蝕該第一源極/汲極區域時，調整該第一源極/汲極區域的一溫度以達成該第一源極/汲極區域與該第二源極/汲極區域不同的蝕刻速率。
  12. 一種半導體裝置的形成方法，包括：進行一第一磊晶以形成一n型鰭狀場效電晶體(Fin Field-Effect transistor，FinFET)的一第一源極/汲極區域；進行一第二磊晶以形成一p型鰭狀場效電晶體的一第二源極/汲極區域；使用一製程氣體同時回蝕該第一源極/汲極區域與該第二源極/汲極區域，其中該製程氣體包括氧硫化碳(carbon oxide sulfide)及含碳和氟氣體，其中該回蝕產生從該第一源極/汲極區域的一頂表面延伸入該第一源極/汲極區域的一第一凹槽，該回蝕產生從該第二源極/汲極區域的一頂表面延伸入該第二源極/汲極區域的一第二凹槽，其中該製程氣體用以在該回蝕中產生一第一聚合物層於該第一源極/汲極區域之上，該第一聚合物層在該第一源極/汲極區域的一頂表面上比在該第一源極/汲極區域的一側壁上厚；以及形成一第一矽化物區於該第一源極/汲極區域之上，其中該第一矽化物區包括一底部及在該底部的兩端之上並連接至該底部的兩端的側壁部份。
  13. 如申請專利範圍第12項所述之半導體裝置的形成方法，其中該製程氣體更包括用以回蝕該第一源極/汲極區域的一蝕刻氣體。
  14. 如申請專利範圍第12項所述之半導體裝置的形成方法， 其中於該回蝕中，該第二源極/汲極區域暴露於該製程氣體。
  15. 如申請專利範圍第12至14項中任一項所述之半導體裝置的形成方法，更包括：在該回蝕之前，調整包括該第一源極/汲極區域之一晶圓的一溫度至低於約20℃，其中在該回蝕中，該晶圓為該溫度。
TW108114842A 2018-04-30 2019-04-29 半導體裝置的形成方法 TWI736884B (zh)

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