CN102034708B - 沟槽型dmos晶体管的制作方法 - Google Patents
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Abstract
一种沟槽型DMOS晶体管的制作方法，包括：在半导体基底上依次形成氧化层和图案化阻挡层；以阻挡层为掩膜，刻蚀氧化层和半导体基底，形成沟槽；在沟槽内壁形成栅氧化层；在阻挡层上形成多晶硅层，且将多晶硅层填充满沟槽内；以阻挡层为掩膜，对多晶硅层进行反刻蚀去除阻挡层上的多晶硅层，形成沟槽栅极；去除阻挡层和氧化层；向沟槽栅极两侧的半导体基底内注入离子，形成扩散层；在扩散层上形成光刻胶层，并定义出源/漏极图形；以光刻胶层为掩膜，沿源/漏极图形向扩散层内注入离子，形成源/漏极；去除光刻胶层后，在沟槽栅极两侧形成侧墙；在扩散层和沟槽栅极上形成金属硅化物层。本发明制作成本降低，效率提高。
Description
技术领域
本发明涉及半导体器件的制造领域，尤其涉及一种沟槽型DMOS晶体管的制作方法。
背景技术
DMOS(双扩散MOS)晶体管是使用扩散形成晶体管区域的MOSFET(半导体上的金属场效应晶体管)的一种类型。DMDS晶体管一般用作功率晶体管，以提供用于功率集成电路应用的高压电路。当需要低的正向压降时，DMOS晶体管每一单位面积提供更高的电流。
DMOS晶体管的一个具体类型是沟槽DMOS晶体管，其中沟道出现在从源极向漏极延伸的沟槽的内壁上，且栅极形成在沟槽内。沟槽型DMOS因为其高压大电流驱动(器件结构决定漏端能承受高压，高集成度可在小面积内做超大W/L(器件沟道的宽/长比)的特点而被广泛应用于模拟电路和驱动，尤其是高压功率部分。
现有形成DMOS晶体管的方法如中国专利申请96108636中公开的，参考图1，在高浓度的n+硅基底10上由低浓度的n-半导体物质形成了覆盖层12，从而形成了半导体基底。即，构成半导体基底的高浓度的基底10和低浓度的覆盖层12扩散了同一导电型的杂质离子。在上述半导体基底的覆盖层12上，注入与具有上述硅基底10的导电型不同的导电型的杂质离子，而形成P型的扩散层14。该扩散层14用于后续工序制造沟槽型DMOS晶体管的主体层。
如图2所示，在扩散层14上形成作为所定图案的电介质膜的氧化硅膜(图中未示出)，以该氧化硅膜的图案作为形成源极用的掩模而进行离子注入工序而形成高浓度的源极杂质注入层16。
然后，如图3所示，除去上述氧化硅的晶格后，再在扩散层14上形成所定图案的氧化硅膜(图中未示出)，从而产生对称的两个沟槽区，利用反应性离子束刻蚀法或其它刻蚀法形成具有垂直侧壁的两个沟槽15a、15b。上述两个沟槽15a、15b分别具有除去了上述半导体基底的覆盖层12部分的深度，在上述两个沟槽15a、15b之间形成的上述杂质注入层16直接连接源极。通过氧化工序分别在上述两个沟槽15a、15b的侧壁和底部表面上形成栅极氧化膜18。
如图4所示，在栅极氧化膜18上形成多晶硅的同时，向上述沟槽15a、15b内填充多晶硅，从而形成栅极多晶硅膜20。形成在各沟槽15a、15b内的该多晶硅膜20a、20b，通过后续的金属布线工序，连接栅极，上述源极杂质注入层16连接源极，上述半导体基底连接集电极。
现有形成DMOS晶体管的工艺比较复杂，需要经过5次左右的光刻或刻蚀工艺，制作成本高，效率低，耗时。并且很少有自对准工艺而造成器件套刻会有大的误差。
发明内容
本发明解决的问题是提供一种沟槽型DMOS晶体管的制作方法，防止制作成本高，效率低。
为解决上述问题，本发明提供一种沟槽型DMOS晶体管的制作方法，包括：在半导体基底上依次形成氧化层和图案化阻挡层；以阻挡层为掩膜，刻蚀氧化层和半导体基底，形成沟槽；在沟槽内壁形成栅氧化层；在阻挡层上形成多晶硅层，且将多晶硅层填充满沟槽内；以阻挡层为掩膜，对多晶硅层进行反刻蚀去除阻挡层上的多晶硅层，形成沟槽栅极；去除阻挡层和氧化层；向沟槽栅极两侧的半导体基底内注入离子，形成扩散层；在扩散层上形成光刻胶层，并定义出源/漏极图形；以光刻胶层为掩膜，沿源/漏极图形向扩散层内注入离子，形成源/漏极；去除光刻胶层后，在沟槽栅极两侧形成侧墙；在扩散层和沟槽栅极上形成金属硅化物层。
可选的，所述半导体基底包括N型硅基底和位于其上的N型外延层。所述沟槽位于N型外延层内。
可选的，形成所述氧化层的方法为热氧化法或化学气相沉积方法或物理气相沉积方法。所述氧化层的材料为二氧化硅，厚度为250埃～350埃。
可选的，形成所述阻挡层的方法为化学气相沉积法或物理气相沉积方法。所述阻挡层的材料为氮化硅，厚度为2500埃～3500埃。
可选的，形成所述栅氧化层的方法为热氧化法或快速退火氧化方法。所述栅氧化层的材料为二氧化硅或含氮二氧化硅，厚度为300埃～1000埃。
可选的，形成扩散层，在半导体基底内注入的离子类型为P型。所述P型离子为硼离子，注入的剂量为1E13/cm2～3E13/cm2，能量为70Kev～100Kev。
可选的，形成源/漏极，向扩散层内注入离子的类型为N型。所述N型离子为砷离子，注入的剂量为1E16/cm2～5E16/cm2，能量为70Kev～130Kev。
与现有技术相比，本发明具有以下优点：只使用了两次光刻工艺，减少了器件制作的工艺步骤，使制作成本降低，效率提高。
附图说明
图1至图4是现有工艺制作DMOS晶体管的示意图；
图5是本发明制作DMOS晶体管的具体实施方式流程图；
图6至图14是采用本发明的方法制作DMOS晶体管的示意图。
具体实施方式
本发明制作DMOS晶体管的具体实施方式流程如图5所示，执行步骤S11，在半导体基底上依次形成氧化层和图案化阻挡层；执行步骤S12，以阻挡层为掩膜，刻蚀氧化层和半导体基底，形成沟槽；执行步骤S13，在沟槽内壁形成栅氧化层；执行步骤S14，在阻挡层上形成多晶硅层，且将多晶硅层填充满沟槽内；执行步骤S15，以阻挡层为掩膜，对多晶硅层进行反刻蚀去除阻挡层上的多晶硅层，形成沟槽栅极；执行步骤S16，去除阻挡层和氧化层；执行步骤S17，向沟槽栅极两侧的半导体基底内注入离子，形成扩散层；执行步骤S18，在扩散层上形成光刻胶层，并定义出源/漏极图形；执行步骤S19，以光刻胶层为掩膜，沿源/漏极图形向扩散层内注入离子，形成源/漏极；执行步骤S20，去除光刻胶层后，在沟槽栅极两侧形成侧墙；执行步骤S21，在扩散层和沟槽栅极上形成金属硅化物层。
由于本发明只使用了两次光刻工艺，减少了器件制作的工艺步骤，使制作成本降低，效率提高。
下面结合附图对本发明的具体实施方式做详细的说明。
图6至图14是采用本发明的方法制作DMOS晶体管的示意图。如图6所示，提供高浓度n+硅基底101；在高浓度的n+硅基底101上形成外延层102，所述外延层102的导电类型与硅基底101一致，即在外延层102中掺杂了低浓度的n-离子。所述n+硅基底101和n-外延层102扩散了同一导电型的杂质离子，构成了半导体基底100。
继续参考图6，用热氧化法或化学气相沉积方法或物理气相沉积方法在n-外延层102上形成厚度为250埃～350埃的氧化层104，所述氧化层104的材料为二氧化硅；用化学气相沉积法或物理气相沉积法在氧化层104上形成厚度为2500埃～3500埃的阻挡层106，所述阻挡层106的材料为氮化硅，阻挡层106的作用为在后续刻蚀工艺中，用于保护其下方的膜层不被破坏。用旋涂法在阻挡层106上形成第一光刻胶层108，经过曝光显影工艺后，在第一光刻胶层108上定义出沟槽图形。接着以第一光刻胶层108为掩膜，沿沟槽图形，刻蚀阻挡层106至露出氧化层104，形成沟槽开口，其中刻蚀阻挡层106所采用的刻蚀方法为干法刻蚀法，采用的气体为C4F8与CO，C4F8与CO的流量比为1∶15。
如图7所示，灰化法或湿法刻蚀法去除第一光刻胶层；以阻挡层106为掩膜，沿沟槽开口，刻蚀氧化层104和n-外延层102，形成沟槽110；其中，刻蚀氧化层104和n-外延层102所采用的刻蚀方法为干法刻蚀法，采用的气体为Cl2、HBr和CF4，流量比为1∶10∶1.5。
参考图8，用热氧化法或快速退火氧化法在沟槽100内壁生长栅氧化层112，所述栅氧化层112的材料为二氧化硅或含氮二氧化硅，厚度为300埃～1000埃。
如图9所示，在沟槽内填充满多晶硅层，形成沟槽栅极114。具体工艺如下：先用化学气相沉积法在阻挡层106上形成多晶硅层，且将多晶硅层填充满沟槽；然后以阻挡层106为掩膜，采用反刻蚀工艺刻蚀多晶硅层至露出阻挡层106，只在沟槽内保留多晶硅层。
本实施例中，所述反刻蚀工艺为干法刻蚀，采用的气体为Cl2。
参考图10，去除阻挡层106和氧化层104，使部分沟槽栅极114露出，即沟槽栅极114表面高出n-外延层102表面。其中去除阻挡层106和氧化层104的方法为湿法刻蚀法。
如图11所示，以沟槽栅极114为掩膜，向n-外延层102内注入P型离子，形成扩散层115，所述扩散层115的作用为形成沟道区。
本实施例中，所述P型离子可以是硼离子或氟化硼离子；形成扩散层115，如果注入的是硼离子，则剂量为1E13/cm2～3E13/cm2，能量为70Kev～100Kev。使形成的扩散层115的厚度为1μm～2μm。
参考图12，用旋涂法在扩散层115上形成第二光刻胶层116，经过曝光显影工艺后，在第二光刻胶层116上定义出源/漏极图形；接着，以第二光刻胶层116为掩膜，沿源/漏极图形，向沟槽栅极114两侧的扩散层115内注入N型离子117，形成源/漏极118。
本实施例中，所述N型离子可以是砷离子或磷离子；形成源/漏极118，注入的如果是砷离子，则剂量为1E16/cm2～5E16/cm2，能量为70Kev～130Kev。使形成的源/漏极118的深度为0.3μm。
接着，进行退火工艺，使离子扩散均匀。
如图13所示，灰化法或湿法刻蚀法去除第二光刻胶层。
继续参考图13，在沟槽栅极114的高出扩散层115表面部分的两侧形成侧墙120。具体形成工艺如下：用低压化学气相沉积法在扩散层115上以及沟槽栅114高出扩散层115表面部分的周围形成氧化层，所述氧化层可以是二氧化硅或氧化硅和氮化硅组合或者氧化硅-氮化硅-氧化硅(ONO)；用反应离子各向异性刻蚀法刻蚀氧化层。
如图14所示，在扩散层115和沟槽栅极114上形成金属硅化物层，所述金属硅化物层的厚度为80埃～350埃，具体材料为硅化钛。具体形成工艺如下：用化学气相沉积法在扩散层115、侧墙120和沟槽栅极114上形成金属层，所述金属层材料为钛；然后进行热处理，使金属层与扩散层115、侧墙120和沟槽栅极114中的硅结合，形成金属硅化物层，即硅化钛层；用湿法刻蚀法去除侧墙120上的金属硅化物层，自动断开栅极与源/漏极之间的连接，以形成欧姆接触工艺。
虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (13)
1.一种沟槽型DMOS晶体管的制作方法，其特征在于，包括：
在半导体基底上依次形成氧化层和图案化阻挡层；
以阻挡层为掩膜，刻蚀氧化层和半导体基底，形成沟槽；
在沟槽内壁形成栅氧化层；
在阻挡层上形成多晶硅层，且将多晶硅层填充满沟槽内；
以阻挡层为掩膜，对多晶硅层进行反刻蚀去除阻挡层上的多晶硅层，形成沟槽栅极；
去除阻挡层和氧化层；
向沟槽栅极两侧的半导体基底内注入离子，形成扩散层；
在扩散层上形成光刻胶层，并定义出源/漏极图形；
以光刻胶层为掩膜，沿源/漏极图形向扩散层内注入离子，形成源/漏极；
去除光刻胶层后，在沟槽栅极两侧形成侧墙；
在扩散层及沟槽栅极上形成金属硅化物层。
2.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，所述半导体基底包括N型硅基底和位于其上的N型外延层。
3.根据权利要求2所述沟槽型DMOS晶体管的制作方法，其特征在于，所述沟槽位于N型外延层内。
4.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，形成所述氧化层的方法为热氧化法或化学气相沉积方法或物理气相沉积方法。
5.根据权利要求4所述沟槽型DMOS晶体管的制作方法，其特征在于，所述氧化层的材料为二氧化硅，厚度为250埃～350埃。
6.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，形成所述阻挡层的方法为化学气相沉积法或物理气相沉积方法。
7.根据权利要求6所述沟槽型DMOS晶体管的制作方法，其特征在于，所述阻挡层的材料为氮化硅，厚度为2500埃～3500埃。
8.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，形成所述栅氧化层的方法为热氧化法或快速退火氧化方法。
9.根据权利要求8所述沟槽型DMOS晶体管的制作方法，其特征在于，所述栅氧化层的材料为二氧化硅或含氮二氧化硅，厚度为300埃～1000埃。
10.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，形成扩散层，在半导体基底内注入的离子类型为P型。
11.根据权利要求10所述沟槽型DMOS晶体管的制作方法，其特征在于，所述P型离子为硼离子，注入的剂量为1E13/cm2～3E13/cm2，能量为70Kev～100Kev。
12.根据权利要求1所述沟槽型DMOS晶体管的制作方法，其特征在于，形成源/漏极，向扩散层内注入离子的类型为N型。
13.根据权利要求12所述沟槽型DMOS晶体管的制作方法，其特征在于，所述N型离子为砷离子，注入的剂量为1E16/cm2～5E16/cm2，能量为70Kev～130Kev。
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| US13/394,679 US20120178230A1 (en) | 2009-09-27 | 2010-09-26 | Method for fabricating trench dmos transistor |
| JP2012530119A JP2013505589A (ja) | 2009-09-27 | 2010-09-26 | トレンチｄｍｏｓトランジスタの製造方法 |
| KR1020127007293A KR20120053511A (ko) | 2009-09-27 | 2010-09-26 | 트렌치형 디모스 트랜지스터 제조 방법 |
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| CN104425351A (zh) * | 2013-09-11 | 2015-03-18 | 中国科学院微电子研究所 | 沟槽形成方法和半导体器件制造方法 |
| KR102335328B1 (ko) * | 2016-12-08 | 2021-12-03 | 현대자동차 주식회사 | 반도체 소자의 제조 방법 |
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| CN1148274A (zh) * | 1995-10-16 | 1997-04-23 | 三星电子株式会社 | 沟槽型dmos晶体管及其制造方法 |
| CN1353863A (zh) * | 1999-04-22 | 2002-06-12 | 理查德·K·威廉斯 | 具有降低接通电阻的超级自对准的沟－栅双扩散金属氧化物半导体器件 |
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| US5567634A (en) * | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
| US6049108A (en) * | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
| JP2000021970A (ja) * | 1998-07-02 | 2000-01-21 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| JP2000223705A (ja) * | 1999-01-29 | 2000-08-11 | Nissan Motor Co Ltd | 半導体装置 |
| JP3337012B2 (ja) * | 1999-09-08 | 2002-10-21 | 日本電気株式会社 | 半導体装置およびその製造方法 |
| DE10239861A1 (de) * | 2002-08-29 | 2004-03-18 | Infineon Technologies Ag | Transistoreinrichtung |
| JP4567969B2 (ja) * | 2003-10-28 | 2010-10-27 | 東部エレクトロニクス株式会社 | 半導体素子のトランジスタ製造方法 |
| US20060113588A1 (en) * | 2004-11-29 | 2006-06-01 | Sillicon-Based Technology Corp. | Self-aligned trench-type DMOS transistor structure and its manufacturing methods |
| US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
| US8338887B2 (en) * | 2005-07-06 | 2012-12-25 | Infineon Technologies Ag | Buried gate transistor |
| US20070075362A1 (en) * | 2005-09-30 | 2007-04-05 | Ching-Yuan Wu | Self-aligned schottky-barrier clamped trench DMOS transistor structure and its manufacturing methods |
| JP5065589B2 (ja) * | 2005-11-29 | 2012-11-07 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| US20080206944A1 (en) * | 2007-02-23 | 2008-08-28 | Pan-Jit International Inc. | Method for fabricating trench DMOS transistors and schottky elements |
| JP5410055B2 (ja) * | 2007-09-27 | 2014-02-05 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| US8878292B2 (en) * | 2008-03-02 | 2014-11-04 | Alpha And Omega Semiconductor Incorporated | Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method |
| US7867852B2 (en) * | 2008-08-08 | 2011-01-11 | Alpha And Omega Semiconductor Incorporated | Super-self-aligned trench-dmos structure and method |
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| CN1148274A (zh) * | 1995-10-16 | 1997-04-23 | 三星电子株式会社 | 沟槽型dmos晶体管及其制造方法 |
| CN1353863A (zh) * | 1999-04-22 | 2002-06-12 | 理查德·K·威廉斯 | 具有降低接通电阻的超级自对准的沟－栅双扩散金属氧化物半导体器件 |
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