CN110707040B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN110707040B
CN110707040B CN201810750109.5A CN201810750109A CN110707040B CN 110707040 B CN110707040 B CN 110707040B CN 201810750109 A CN201810750109 A CN 201810750109A CN 110707040 B CN110707040 B CN 110707040B
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forming
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CN110707040A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

一种半导体器件及其形成方法，包括：提供包括逻辑区和外围区的半导体衬底；在半导体衬底上形成初始鳍部和隔离结构，初始鳍部包括若干沿半导体衬底表面法线方向重叠的第一鳍部层和位于相邻第一鳍部层之间的第二鳍部层，隔离结构覆盖部分初始鳍部侧壁；在外围区初始鳍部侧壁形成保护层；去除外围区初始鳍部形成凹槽，凹槽底部表面低于隔离结构顶部表面；在凹槽内形成单一材料的修正鳍部；去除保护层；形成横跨初始鳍部的第一栅极结构，第一栅极结构包括第一栅介质层，第一栅极结构环绕逻辑区的第一鳍部层；形成横跨修正鳍部的第二栅极结构，第二栅极结构包括第二栅介质层，第二栅介质层厚度大于第一栅介质层厚度。所述方法提高了半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。在目前的半导体产业中，集成电路产品主要可分为三大类型：逻辑、存储器和模拟电路，为实现高级程度和更为广泛的应用，需要将不同功能的器件同时形成在一个芯片上，以形成嵌入式半导体装置。例如将核心器件和输入输出器件集成在同一芯片内。
核心器件承担了半导体器件的主要功能，对核心器件的性能要求越来越高，为适应对器件性能不断提出的更高要求，催生了四面控制的全包围栅结构(Gate-all-around)。具有全包围栅极(Gate-all-around)结构的半导体器件拥有有效地限制短沟道效应(Shortchannel effect)的特殊性能，正是业界在遵循摩尔定律不断缩小器件尺寸的革新中所极其渴望的。全包围栅极结构中的薄硅膜构成的器件沟道被器件的栅极包围环绕，而且仅被栅极控制，从而减小短沟道效应。
然而，性能较优的全包围栅极结构不一定适用于所有器件，现有技术中集成了多种功能器件的集成半导体器件性能较差。
发明内容
本发明解决的技术问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述技术问题，本发明实施例提供一种半导体器件的形成方法，包括：提供半导体衬底，所述半导体衬底包括逻辑区和外围区；在逻辑区和外围区半导体衬底上分别形成初始鳍部和隔离结构，所述初始鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层和第二鳍部层，所述第二鳍部层位于相邻两层第一鳍部层之间，所述隔离结构覆盖部分初始鳍部侧壁；在外围区初始鳍部侧壁形成保护层，所述保护层暴露出外围区初始鳍部顶部表面；去除外围区初始鳍部，在外围区的保护层内形成凹槽，所述凹槽底部表面低于隔离结构顶部表面；在所述凹槽内形成修正鳍部，所述修正鳍部的材料为单一材料；去除所述保护层，暴露出修正鳍部顶部和侧壁表面；形成横跨逻辑区初始鳍部的第一栅极结构，所述第一栅极结构包括第一栅介质层，且部分第一栅极结构替代逻辑区的第二鳍部层，所述第一栅极结构环绕逻辑区的第一鳍部层；形成横跨修正鳍部的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层厚度大于所述第一栅介质层厚度。
可选的，所述修正鳍部的材料包括：单晶硅、单晶锗或者硅锗。
可选的，在所述凹槽内形成修正鳍部的工艺包括：外延生长工艺。
可选的，所述保护层还覆盖逻辑区初始鳍部顶部和侧壁。
可选的，所述保护层的材料包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
可选的，所述保护层的形成方法包括：在半导体衬底表面形成初始保护层，所述初始保护层覆盖初始鳍部顶部和侧壁表面；在逻辑区的初始保护层表面形成掩膜层；以所述掩膜层为掩膜，回刻蚀所述初始保护层，直至暴露出外围区初始鳍部顶部表面形成所述保护层。
可选的，还包括：在形成第一栅极结构和第二栅极结构之前，在半导体衬底上形成介质层，介质层内具有第一栅开口和第二栅开口；在所述第一栅开口内形成第一栅极结构，在所述第二栅开口内形成第二栅极结构。
可选的，还包括：形成介质层前，形成横跨逻辑区初始鳍部的第一伪栅极结构，所述第一伪栅极结构覆盖部分逻辑区初始鳍部的侧壁和顶部表面；所述介质层覆盖第一伪栅极结构侧壁；所述第一栅开口的形成方法包括：去除第一伪栅极结构，在介质层中形成初始第一栅开口，所述初始第一栅开口位于逻辑区内；去除初始第一栅开口暴露出的逻辑区的第二鳍部层，在逻辑区介质层内形成第一栅开口。
可选的，还包括：形成介质层前，形成横跨修正鳍部的第二伪栅极结构，所述第二伪栅极结构覆盖部分修正鳍部的侧壁和顶部表面；所述介质层覆盖第二伪栅极结构侧壁；所述第二栅开口的形成方法包括：去除第二伪栅极结构，在外围区介质层内形成第二栅开口；在所述第二栅开口内形成第二栅极结构。
可选的，所述第一栅介质层包括第一界面层和第一栅介质本体层，所述第一界面层位于所述第一栅开口底部，所述第一栅介质本体层位于第一栅开口底部和侧壁，且所述第一栅介质本体层覆盖第一界面层表面。
可选的，所述第二栅介质层包括第二界面层和第二栅介质本体层，所述第二界面层位于所述第二栅开口底部，所述第二栅介质本体层位于第二栅开口底部和侧壁，且所述第二栅介质本体层覆盖第二界面层表面。所述第二界面层厚度大于第一界面层厚度。
可选的，所述第一栅介质本体层和第二栅介质本体层同时形成。
可选的，形成介质层前，在所述修正鳍部表面形成所述第二界面层，所述第二栅开口暴露出第二界面层。
可选的，所述第一伪栅极结构包括第一伪栅介质层和第一伪栅极层；所述第一栅开口的形成方法包括：去除第一伪栅极层，暴露出第一伪栅介质层，在介质层中形成初始第一栅开口，所述初始第一栅开口位于逻辑区内；去除第一伪栅介质层；去除第一伪栅介质层后，去除初始第一栅开口暴露出的逻辑区的第二鳍部层，在逻辑区介质层内形成第一栅开口。
可选的，形成保护层前，在所述逻辑区初始鳍部顶部和侧壁以及外围区初始鳍部顶部和侧壁形成所述第一伪栅介质层，所述保护层暴露出外围区初始鳍部侧壁的第一伪栅介质层顶部表面和外围区初始鳍部顶部表面。
可选的，形成凹槽后，形成修正鳍部前，去除外围区保护层侧壁的第一伪栅介质层。
可选的，形成第一栅极结构或第二栅极结构前，去除保护层后，去除外围区保护层侧壁的第一伪栅介质层。
可选的，形成所述初始鳍部的方法包括：在所述半导体衬底上形成鳍部材料膜，鳍部材料膜若干层沿半导体衬底表面法线方向重叠的第一鳍部膜、以及位于相邻两层第一鳍部层中的第二鳍部膜；在所述鳍部材料膜上形成图形化层；以所述图形化层为掩膜，刻蚀所述鳍部材料膜以形成初始鳍部，且使所述第一鳍部膜形成第一鳍部层，使所述第二鳍部膜形成第二鳍部层。
可选的，所述第一鳍部层的材料和第二鳍部层的材料不同；所述第一鳍部层的材料为单晶硅或单晶锗硅；所述第二鳍部层的材料为单晶硅锗或单晶硅。
本发明还提供一种半导体器件，包括：半导体衬底，所述半导体衬底包括逻辑区和外围区；位于逻辑区半导体衬底上的初始鳍部，所述初始鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层；位于外围区半导体衬底上的修正鳍部，所述修正鳍部的材料为单一材料；位于半导体衬底表面的隔离结构，所述隔离结构覆盖部分初始鳍部和修正鳍部侧壁；横跨初始鳍部的第一栅极结构，第一栅极结构包括第一栅介质层，所述第一栅极结构环绕初始鳍部的第一鳍部层；横跨修正鳍部的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层厚度大于所述第一栅介质层厚度。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明技术方案提供的半导体器件的形成方法中，逻辑区用于形成逻辑器件，外围区用于形成外围器件，外围区的修正鳍部为单一材料，覆盖修正鳍部的第二栅介质层厚度较厚，能满足外围器件在较高电压下的性能要求。同时逻辑区的第一栅极结构环绕逻辑区的第一鳍部层，第一栅极结构对沟道的控制能力增强，逻辑区所形成的半导体器件性能得到提升，从而实现逻辑区半导体器件和外围区半导体器件的工艺整合的同时，提高半导体器件的性能。
附图说明
图1是一种半导体器件的结构示意图；
图2至图10是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术的半导体器件的性能较差。
图1是一种半导体器件的结构示意图。
参考图1，一种半导体器件，包括：半导体衬底100，所述半导体衬底100包括逻辑区I和外围区II；位于逻辑区I半导体衬底上的逻辑鳍部，所述逻辑鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层111；位于外围区II半导体衬底上的外围鳍部，所述外围鳍部包括若干层沿半导体衬底法线方向重叠的第二鳍部层121，所述第一鳍部层111和第二鳍部层121材料相同；位于半导体衬底100上，覆盖部分逻辑鳍部侧壁和部分外围鳍部侧壁的隔离层101；位于逻辑区I隔离层101上横跨逻辑鳍部的第一栅极结构，所述第一栅极结构环绕逻辑鳍部的第一鳍部层；位于外围区II隔离层101外围区II上横跨外围鳍部的第二栅极结构，所述第二栅极结构环绕外围鳍部的第二鳍部层。
随着半导体技术的发展，为提高栅极结构对沟道的控制能力，采用全包围栅结构提高半导体器件的性能。然而半导体器件的外围区器件电压较大，外围区器件的栅介质层需要较厚的厚度才能满足需求。全包围栅结构的第二栅极结构包围第二鳍部层121，而相邻第二鳍部层121间的空间较小，在形成较厚的第二栅介质层后，相邻第二鳍部层121间的空间过小，在该过小的空间内形成功函数层或第二栅极层时难度较高，且形成的质量不高；若形成较薄的第二栅介质层，在高压条件下，较薄的第二栅介质层容易被击穿，综上所述，逻辑区和外围区均采用全包围栅结构的半导体器件的性能较差。
本发明技术方案中逻辑区形成全包围栅结构的半导体器件，外围区的鳍部采用单一材料的多栅器件，所述方法提高了半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图10是本发明一实施例中半导体器件形成过程的结构示意图。
请参考图2，提供半导体衬底200，所述半导体衬底200包括逻辑区A和外围区B。
在所述半导体衬底200上形成鳍部材料膜，所述鳍部材料膜包括若干层沿半导体衬底200表面法线方向重叠的第一鳍部膜201、以及位于相邻两层第一鳍部膜中的第二鳍部膜202；在所述鳍部材料膜表面形成鳍部保护膜203。
所述鳍部材料膜为后续形成初始鳍部提供材料层。
所述鳍部保护膜203在后续形成鳍部时保护鳍部顶部表面。
所述半导体衬底200可以是单晶硅，多晶硅或非晶硅；所述半导体衬底200也可以是硅、锗、锗化硅、砷化镓等半导体材料。
本实施例中，所述半导体衬底200的材料为单晶硅。
第一鳍部膜201和第二鳍部膜202的材料不同。所述第一鳍部膜201的材料为单晶硅或单晶锗硅；所述第二鳍部膜202的材料为单晶硅或单晶锗硅。
所述第一鳍部膜201的材料为单晶硅时，所述第二鳍部膜202的材料为单晶硅锗；所述第一鳍部膜201的材料为单晶硅锗时，所述第二鳍部膜202的材料为单晶硅。
本实施例中，所述第一鳍部膜201的材料为单晶硅，所述第二鳍部膜202的材料为单晶硅锗。
在一实施例中，所述第一鳍部膜201的材料为单晶硅锗，所述第二鳍部膜202的材料为单晶硅。
请参考图3，刻蚀所述鳍部材料膜，在逻辑区A和外围区B半导体衬底200上形成初始鳍部210，所述初始鳍部210包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层211、以及位于相邻两层第一鳍部层211之间的第二鳍部层212。
所述初始鳍部210的形成方法包括：在所述鳍部材料膜上形成图形化层(未图示)，所述图形化层覆盖部分所述鳍部材料膜；以所述图形化层为掩膜，刻蚀所述鳍部材料膜以形成初始鳍部，且使所述第一鳍部膜形成第一鳍部层211，使所述第二鳍部膜形成第二鳍部层212。
本实施例中，所述第一鳍部层211的材料为单晶硅，所述第二鳍部层212的材料为单晶硅锗。
所述交错叠层结构的初始鳍部为后续形成全包围栅提供初始结构。
继续参考图3，在所述半导体衬底200上形成隔离结构201，所述隔离结构201覆盖底部区初始鳍部210的部分侧壁。
所述隔离结构201顶部表面低于初始鳍部210最底部的第二鳍部层212的底部表面或者与初始鳍部210最底部的第二鳍部层212的底部表面齐平。
所述隔离结构201顶部表面与初始鳍部210最底部的第二鳍部层212的底部表面之间的距离为0至200埃。
本实施例中，所述隔离结构201顶部表面与初始鳍部210最底部的第二鳍部层212的底部表面齐平。
所述隔离结构201的材料包括氧化硅。
形成所述隔离结构201的方法包括：在所述半导体衬底200上形成覆盖初始鳍部210的隔离结构膜(未图示)；平坦化所述隔离结构膜，直至露出初始鳍部210顶部表面，回刻蚀隔离结构膜，形成所述隔离结构201。
形成所述隔离结构膜的工艺为沉积工艺，如流体化学气相沉积工艺。采用流体化学气相沉积工艺形成隔离结构膜，使隔离结构膜的填充性能较好。
形成隔离结构膜所采用的流体化学气相沉积工艺的步骤包括：在半导体衬底200上形成隔离流体层；进行水汽退火，使所述隔离流体层形成隔离结构膜。
所述水汽退火的参数包括：采用的气体包括氧气、臭氧和气态水，退火温度为350摄氏度～750摄氏度。
请参考图4，在所述初始鳍部210顶部和侧壁表面形成第一伪栅介质层205。
所述第一伪栅介质层205为后续形成第一伪栅极结构提供材料层，且在后续去除保护层时保护逻辑区A内的初始鳍部210。
其他实施中，去除逻辑区保护层后，在逻辑区初始鳍部顶部和侧壁表面形成第一伪栅介质层。
在一实施例中，形成第二界面层时，在逻辑区初始鳍部顶部和侧壁表面形成所述第一伪栅介质层。
本实施例中，所述第一伪栅介质层205位于逻辑区A的初始鳍部210侧壁和顶部表面以及外围区B的初始鳍部210侧壁和顶部表面。
在一实施例中，所述第一伪栅介质层205不位于外围区初始鳍部210侧壁和顶部表面。
所述第一伪栅介质层的材料包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
本实施例中，所述第一伪栅介质层205的材料为氧化硅。
所述第一伪栅介质层205的形成工艺包括：化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
本实施例中，所述第一伪栅介质层205的形成工艺为原子层沉积工艺。
所述第一伪栅介质层205的厚度为20埃～50埃。
请参考图5，在所述第一伪栅介质层205表面形成初始保护层206。
所述初始保护层206为后续形成保护层提供材料层。
所述初始保护层206位于第一伪栅介质层205表面，且覆盖逻辑区A的初始鳍部210侧壁和顶部表面，所述初始保护层206还覆盖外围区B的初始鳍部210侧壁和顶部表面。
所述初始保护层206的材料包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
形成所述初始保护层206的工艺包括：化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
本实施例中，所述初始保护层206的形成工艺为化学气相沉积工艺。
所述初始保护层206的厚度为10埃～35埃。
请参考图6，回刻蚀外围区B的初始保护层206，在外围区B的初始鳍部210侧壁形成保护层207，所述保护层207暴露出外围区B的初始鳍部210顶部表面。
所述保护层207还覆盖逻辑区A的初始鳍部210顶部和侧壁表面。
所述保护层207为后续形成规则形状的修正鳍部提供阻挡结构，限制修正鳍部形成时的生长方向。
所述保护层207的形成方法包括：在初始保护层206表面形成掩膜层(未图示)，所述掩膜层覆盖逻辑区初始鳍部210顶部和侧壁；以所述掩膜层为掩膜，回刻蚀所述初始保护层206，直至暴露出外围区B初始鳍部210顶部表面形成所述保护层207。
本实施例中，回刻蚀所述初始保护层206后，还包括去除外围区B初始鳍部210顶部表面的第一伪栅介质层205，暴露出外围区B初始鳍部210顶部表面形成所述保护层207。
所述掩膜层的材料为光刻胶。
形成保护层207后，去除所述掩膜层。去除所述掩膜层的工艺为灰化工艺。
本实施例中，所述保护层207的材料为氮化硅。
在一实施例中，所述保护层207的材料为氮氧化硅。
继续参考图6，去除外围区B的初始鳍部210，在外围区B的保护层207之间形成凹槽208，所述凹槽208底部表面低于逻辑区A初始鳍部210最底部的第二鳍部层212底部表面。
本实施例中，还包括去除外围区B的初始鳍部210侧壁的第一伪栅介质层205。
在一实施例中，不去除外围区B的初始鳍部210侧壁的第一伪栅介质层205，后续去除保护层时一起去除。
所述凹槽208为后续形成修正鳍部提供空间。
去除外围区B的初始鳍部210的工艺包括干法刻蚀工艺。
本实施例中，去除外围区B的初始鳍部210的工艺为干法刻蚀工艺，所述干法刻蚀的参数包括：第一阶段采用CF4气体和H2气体，CF4气体流量为5sccm～300sccm，H2气体流量为20sccm～500sccm，时间为5s～50s，温度为70摄氏度；第二阶段采用包括CH3F气体、O2和He的混合气体，CH3F流量为60sccm～800sccm，O2流量为5sccm～200sccm，He流量为60sccm～200sccm，时间为5秒～100s，温度为35摄氏度～85摄氏度。
请参考图7，在所述凹槽208内形成修正鳍部223，所述修正鳍部223材料为单一材料。
所述修正鳍部223为外围区B的鳍部，后续在修正鳍部223上形成半导体器件的其他结构。
所述修正鳍部210材料为单一材料，后续不会形成全包围栅结构的第二栅极结构，在单一材料的修正鳍部表面形成第二栅极结构时，第二栅介质层较厚也不会影响第二栅极层的沉积，所形成的第二栅极层质量较高，外围区器件的性能得到提高，从而提高了半导体器件的性能。
所述修正鳍部210的材料包括：单晶硅、单晶锗或者硅锗。
本实施例中，所述修正鳍部223的材料为单晶硅。
在一实施例中，所述修正鳍部223的材料为单晶硅锗，单晶硅锗作为鳍部材料，能够提高载流子的迁移速率，从而提高所形成的半导体器件的性能。
在所述凹槽208内形成修正鳍部223的工艺包括：外延生长工艺。
本实施例中，所述外延生长工艺的参数包括：采用的气体包括氢气、HCl气体、SiH2Cl2，氢气的流量为2000sccm～20000sccm，HCl气体的流量为30sccm～150sccm，SiH2Cl2的流量为50sccm～1000sccm，腔室压强为10torr～600torr，温度为650摄氏度～850摄氏度。
请参考图8，去除修正鳍部223侧壁的保护层207，暴露出修正鳍部223顶部和侧壁表面。
去除修正鳍部223侧壁的保护层207，以便后续在修正鳍部223表面形成第二界面层。
本实施例中，还包括去除逻辑区A初始鳍部210上的保护层207，暴露出覆盖逻辑区A初始鳍部210顶部和侧壁表面的第一伪栅介质层205。
在一实施例中，还包括去除外围区B的初始鳍部210侧壁的第一伪栅介质层205。
去除修正鳍部223侧壁以及逻辑区A初始鳍部210上的保护层207的工艺包括：干法刻蚀工艺或者湿法刻蚀工艺。
本实施例中，去除修正鳍部223侧壁的保护层207为干法刻蚀工艺，实施干法刻蚀工艺参数包括：采用的气体包括氢气、CH3F气体、N2和O2，CH3F气体的流量为8sccm～50sccm，N2气体的流量为200sccm，O2的流量为5sccm～60sccm，源射频功率为80W～300W，偏置电压为30V～100V，腔室压强为10mtorr～200mtorr，时间为4秒～50秒。
形成横跨逻辑区初始鳍部的第一栅极结构，所述第一栅极结构包括第一栅介质层，所述第一栅极结构环绕逻辑区的第一鳍部层；形成横跨修正鳍部的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层厚度大于第一栅介质层厚度。
本实施例中，采用后栅工艺形成所述第一栅极结构和第二栅极结构。
在形成第一栅极结构和第二栅极结构之前，还包括：在半导体衬底上形成介质层，介质层内具有第一栅开口和第二栅开口；在所述第一栅开口内形成第一栅极结构，在所述第二栅开口内形成第二栅极结构。
形成介质层之前，还包括：形成横跨逻辑区初始鳍部的第一伪栅极结构，所述第一伪栅极结构覆盖部分逻辑区初始鳍部的侧壁和顶部表面；所述介质层覆盖第一伪栅极结构侧壁。
所述第一栅开口的形成方法包括：去除第一伪栅极结构，在介质层中形成初始第一栅开口，所述初始第一栅开口位于逻辑区内；去除初始第一栅开口暴露出的逻辑区的第二鳍部层，使初始第一栅开口形成所述第一栅开口，在逻辑区介质层内形成第一栅开口。
形成介质层前，还包括：形成横跨修正鳍部的第二伪栅极结构，所述第二伪栅极结构覆盖部分修正鳍部的侧壁和顶部表面；所述介质层覆盖第二伪栅极结构侧壁；所述第二栅开口的形成方法包括：去除第二伪栅极结构，在外围区介质层内形成第二栅开口；在所述第二栅开口内形成第二栅极结构
具体的，所述第一栅极结构的形成方法包括：形成横跨逻辑区初始鳍部的第一伪栅极结构，所述第一伪栅极结构覆盖部分逻辑区初始鳍部的侧壁和顶部表面；去除第一伪栅极结构和第一伪栅极结构覆盖的逻辑区的第二鳍部层，在逻辑区介质层内形成第一栅开口；在所述第一栅开口内形成第一栅极结构，所述第一栅极结构环绕逻辑区的第一鳍部层。
具体的，所述第二栅极结构的形成方法包括：形成横跨修正鳍部的第二伪栅极结构；去除第二伪栅极结构，在外围区介质层内形成第二栅开口；在所述第二栅开口内形成第二栅极结构。
所述第一伪栅极结构包括第一伪栅介质层和第一伪栅极层。
所述第二伪栅极结构包括第二伪栅介质层和第二伪栅极层。
所述第一栅极结构包括第一栅介质层和第一栅极层。
所述第二栅极结构包括第二栅介质层和第二栅极层。
本实施例中，所述第一栅介质层包括第一界面层和第一栅介质本体层，所述第一界面层位于所述第一栅开口底部，所述第一栅介质本体层位于第一栅开口底部和侧壁，覆盖第一界面层表面。
本实施例中，所述第二栅介质层包括第二界面层和第二栅介质本体层，所述第二界面层位于所述第二栅开口底部，所述第二栅介质本体层位于第二栅开口底部和侧壁，覆盖第二界面层表面。
为满足外围区半导体器件的需求，第二栅极结构的第二界面层厚度较厚，且对第二界面层的质量要求不高，可以用第二伪栅介质层作为第二界面层，即去除第二伪栅极结构时，去除第二伪栅极层即可，保留第二伪栅介质层作为后续形成的第二栅极结构的第二界面层或者第二栅介质层。
本实施例中，用第二伪栅极介质层作为后续形成的第二栅极结构的第二界面层。
本实施例中，形成介质层前，在所述修正鳍部表面形成所述第二界面层，所述第二栅开口暴露出第二界面层。
其他实施例中，形成第二栅开口后，在第二栅开口底部形成第二界面层。
请参考图9，在外围区B的修正鳍部223表面形成第二界面层241。
所述第二界面层241为改善后续形成的第二栅介质层与修正鳍部223的表面状态，同时作为第二栅极结构第二栅极层和修正栅极223之间隔离的隔离层。
第一栅介质层包括第一界面层和第一栅介质本体层；第二栅介质层包括第二界面层和第二栅介质本体层。第二界面层厚度大于第一界面层，则第二栅介质层厚度大于第一栅介质层。逻辑区用于形成逻辑器件，外围区用于形成外围器件，外围区的修正鳍部材料为单一材料，覆盖修正鳍部的第二栅介质层厚度较厚，能满足外围器件在较高电压下的性能要求，同时逻辑区的第一栅极结构环绕逻辑区的第一鳍部层，第一栅极结构对沟道的控制能力增强，逻辑区所形成的半导体器件性能得到提升，从而实现逻辑区半导体器件和外围区半导体器件的整合，提高半导体器件的性能。
所述第二界面层的厚度为25埃～45埃。
所述第二界面层的形成工艺包括：化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。
本实施例中，所述第二界面层241的形成工艺为原子层沉积工艺，所述原子层沉积工艺的参数包括：采用含Si和O的有机前驱体气体，温度为80摄氏度～300摄氏度，压强为5mtorr～20torr，工艺次数为5次～100次。
请参考图10，形成横跨逻辑区初始鳍部210的第一栅极结构，所述第一栅极结构环绕逻辑区的第一初始鳍部210层；形成横跨修正初始鳍部210的第二栅极结构。
所述第一栅极结构和第二栅极结构的形成方法包括：形成横跨逻辑区A初始鳍部210的第一伪栅极层(未图示)，所述第一伪栅极层位于逻辑区A的第一栅介质层205表面；形成第一伪栅极层后，在半导体衬底200上形成介质层(未图示)，所述介质层覆盖第一伪栅极层侧壁表面和第二伪栅极层侧壁表面，暴露出第一伪栅极层和第二伪栅极层顶部表面；去除第一伪栅极层、逻辑区A的第一伪栅介质层205和第一伪栅极层覆盖的逻辑区A的第二鳍部层212，在逻辑区A介质层内形成第一栅开口；在第一栅开口内形成第一栅介质层本体232和第一栅极层234，所述第一栅介质层本体232位于第一栅开口底部和侧壁，且覆盖第一界面层231表面，所述第一栅极层234位于第一栅介质层本体232表面，所述第一栅极层234顶部表面与介质层表面齐平。
所述第二栅极结构的形成方法包括：形成横跨外围区B修正鳍部223的第二伪栅极层(未图示)，所述第二伪栅极层位于第二界面层241表面，覆盖外围区B隔离结构204部分顶部表面；形成第二伪栅极层后，去除第二伪栅极层，在外围区B介质层内形成第二栅开口；在第二栅开口内形成第二栅介质层本体232和第二栅极层244，所述第二栅介质层本体232位于第二栅开口底部和侧壁，且覆盖第二界面层241表面，所述第二栅极层244位于第二栅介质层本体232表面，所述第二栅极层244顶部表面与介质层表面齐平。
本实施例中，所述第一伪栅极层和第二伪栅极层同时形成。
其他实施中，所述第一伪栅极层和第二伪栅极层不同时形成。
本实施例中，所述第一栅介质层本体232和第二栅介质层本体232同时形成。
其他实施中，所述第一栅介质层本体232和第二栅介质层本体232不同时形成。
本实施例中，所述第一栅极层234和第二栅极层244同时形成。
其他实施中，所述第一栅极层234和第二栅极层244不同时形成。
所述第一栅极结构还包括：位于第一栅介质层本体232和第一栅极层234之间的第一功函数层233。
所述第二栅极结构还包括：位于第二栅介质层本体232和第二栅极层244之间的第二功函数层243。
所述第一功函数层233或第二功函数层243用于调节所形成半导体器件的阈值电压。
如果所述第一栅极结构或第二栅极结构用于形成P型器件，所述第一功函数层233或第二功函数层243的材料为氧化钛或氮化钛；如果所述第一栅极结构或第二栅极结构用于形成N型器件，所述第一功函数层233或第二功函数层243的材料为钛或钽。
所述第一界面层或第二界面层的材料为氧化硅。
所述第一栅介质层或第二栅介质层的材料为高k介质材料(介电系数大于3.9)；所述高k介质材料包括氧化铪、氧化锆、氧化铪硅、氧化镧、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛或氧化铝。
所述第一栅极层或第二栅极层的材料为金属，所述金属材料包括铜、钨、镍、铬、钛、钽和铝中的一种或多种组合。
逻辑区用于形成逻辑器件，外围区用于形成外围器件，外围区的修正鳍部材料为单一材料，覆盖修正鳍部的第二栅介质层由第二界面层和第二栅介质本体层组成，第二界面层厚度较厚，第二栅介质层能满足外围器件在较高电压下的性能要求，同时逻辑区的第一栅极结构环绕逻辑区的第一鳍部层，第一栅极结构对沟道的控制能力增强，逻辑区所形成的半导体器件性能得到提升，从而实现逻辑区半导体器件和外围区半导体器件的整合，提高半导体器件的性能。
相应的，本实施例还提供一种采用上述方法形成的半导体器件，参考图图10，包括：半导体衬底200，所述半导体衬底200包括逻辑区A和外围区B；位于逻辑区A半导体衬底200上的初始鳍部，所述初始鳍部包括若干层沿半导体衬底200表面法线方向重叠的第一鳍部层211；位于外围区B半导体衬底200表面的修正鳍部223，所述修正鳍部223的材料为单一材料；横跨初始鳍部的第一栅极结构，第一栅极结构包括第一栅介质层，所述第一栅极结构环绕初始鳍部的第一鳍部层；横跨修正鳍部223的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层厚度大于所述第一栅介质层厚度。
所述修正鳍部223的材料包括：单晶硅、单晶锗或者硅锗。
所述半导体衬底200参照前述实施例的内容，不再详述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底包括逻辑区和外围区；
在逻辑区和外围区半导体衬底上分别形成初始鳍部和隔离结构，所述初始鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层和第二鳍部层，所述第二鳍部层位于相邻两层第一鳍部层之间，所述隔离结构覆盖部分初始鳍部侧壁；
在初始鳍部顶部和侧壁表面形成第一伪栅介质层；
在外围区初始鳍部侧壁形成保护层，所述保护层覆盖初始鳍部上的第一伪栅介质层，所述保护层暴露出外围区初始鳍部顶部表面；
去除外围区初始鳍部，在外围区的保护层内形成凹槽，所述凹槽底部表面低于隔离结构顶部表面；
在所述凹槽内形成修正鳍部，所述修正鳍部的材料为单一材料；
去除所述保护层，暴露出修正鳍部顶部和侧壁表面；
形成横跨逻辑区初始鳍部的第一栅极结构，所述第一栅极结构包括第一栅介质层，且部分第一栅极结构替代逻辑区的第二鳍部层，所述第一栅极结构环绕逻辑区的第一鳍部层；
形成横跨修正鳍部的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层包括第二界面层，所述第二栅介质层厚度大于所述第一栅介质层厚度；
所述第一伪栅介质层在所述第二界面层形成之后去除。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述修正鳍部的材料包括：单晶硅、单晶锗或者硅锗。
3.根据权利要求1所述的半导体器件的形成方法，其特征在于，在所述凹槽内形成修正鳍部的工艺包括：外延生长工艺。
4.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述保护层还覆盖逻辑区初始鳍部顶部和侧壁。
5.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述保护层的材料包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
6.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述保护层的形成方法包括：在半导体衬底上形成初始保护层，所述初始保护层覆盖初始鳍部顶部和侧壁表面；在逻辑区的初始保护层上形成掩膜层；以所述掩膜层为掩膜，回刻蚀所述初始保护层，直至暴露出外围区初始鳍部顶部表面形成所述保护层。
7.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在形成第一栅极结构和第二栅极结构之前，在半导体衬底上形成介质层，介质层内具有第一栅开口和第二栅开口；在所述第一栅开口内形成第一栅极结构，在所述第二栅开口内形成第二栅极结构。
8.根据权利要求7所述的半导体器件的形成方法，其特征在于，还包括：形成介质层前，形成横跨逻辑区初始鳍部的第一伪栅极结构，所述第一伪栅极结构覆盖部分逻辑区初始鳍部的侧壁和顶部表面；所述介质层覆盖第一伪栅极结构侧壁；所述第一栅开口的形成方法包括：去除第一伪栅极结构，在介质层中形成初始第一栅开口，所述初始第一栅开口位于逻辑区内；去除初始第一栅开口暴露出的逻辑区的第二鳍部层，在逻辑区介质层内形成第一栅开口。
9.根据权利要求7所述的半导体器件的形成方法，其特征在于，还包括：形成介质层前，形成横跨修正鳍部的第二伪栅极结构，所述第二伪栅极结构覆盖部分修正鳍部的侧壁和顶部表面；所述介质层覆盖第二伪栅极结构侧壁；所述第二栅开口的形成方法包括：去除第二伪栅极结构，在外围区介质层内形成第二栅开口；在所述第二栅开口内形成第二栅极结构。
10.根据权利要求8所述的半导体器件的形成方法，其特征在于，所述第一栅介质层包括第一界面层和第一栅介质本体层，所述第一界面层位于所述第一栅开口底部，所述第一栅介质本体层位于第一栅开口底部和侧壁，且所述第一栅介质本体层覆盖第一界面层表面。
11.根据权利要求10所述的半导体器件的形成方法，其特征在于，所述第二栅介质层包括第二界面层和第二栅介质本体层，所述第二界面层位于所述第二栅开口底部，所述第二栅介质本体层位于第二栅开口底部和侧壁，且所述第二栅介质本体层覆盖第二界面层表面，所述第二界面层厚度大于第一界面层厚度。
12.根据权利要求11所述的半导体器件的形成方法，其特征在于，所述第一栅介质本体层和第二栅介质本体层同时形成。
13.根据权利要求11所述的半导体器件的形成方法，其特征在于，形成介质层前，在所述修正鳍部表面形成所述第二界面层，所述第二栅开口暴露出第二界面层。
14.根据权利要求13所述的半导体器件的形成方法，其特征在于，所述第一伪栅极结构包括第一伪栅介质层和第一伪栅极层；所述第一栅开口的形成方法包括：去除第一伪栅极层，暴露出第一伪栅介质层，在介质层中形成初始第一栅开口，所述初始第一栅开口位于逻辑区内；去除第一伪栅介质层；去除第一伪栅介质层后，去除初始第一栅开口暴露出的逻辑区的第二鳍部层，在逻辑区介质层内形成第一栅开口。
15.根据权利要求14所述的半导体器件的形成方法，其特征在于，形成保护层前，在所述逻辑区初始鳍部顶部和侧壁以及外围区初始鳍部顶部和侧壁形成所述第一伪栅介质层，所述保护层暴露出外围区初始鳍部侧壁的第一伪栅介质层顶部表面和外围区初始鳍部顶部表面。
16.根据权利要求15所述的半导体器件的形成方法，其特征在于，形成凹槽后，形成修正鳍部前，去除外围区保护层侧壁的第一伪栅介质层。
17.根据权利要求15所述的半导体器件的形成方法，其特征在于，形成第一栅极结构或第二栅极结构前，去除保护层后，去除外围区保护层侧壁的第一伪栅介质层。
18.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述初始鳍部的方法包括：在所述半导体衬底上形成鳍部材料膜，鳍部材料膜若干层沿半导体衬底表面法线方向重叠的第一鳍部膜、以及位于相邻两层第一鳍部层中的第二鳍部膜；在所述鳍部材料膜上形成图形化层；以所述图形化层为掩膜，刻蚀所述鳍部材料膜以形成初始鳍部，且使所述第一鳍部膜形成第一鳍部层，使所述第二鳍部膜形成第二鳍部层。
19.根据权利要求18所述的半导体器件的形成方法，其特征在于，所述第一鳍部层的材料和第二鳍部层的材料不同；所述第一鳍部层的材料为单晶硅或单晶锗硅；所述第二鳍部层的材料为单晶硅锗或单晶硅。
20.一种半导体器件，其特征在于，所述半导体器件由权利要求1～19中任一项所述的形成方法形成，包括：
半导体衬底，所述半导体衬底包括逻辑区和外围区；
位于逻辑区半导体衬底上的初始鳍部，所述初始鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层；
位于外围区半导体衬底上的修正鳍部，所述修正鳍部的材料为单一材料；
位于半导体衬底表面的隔离结构，所述隔离结构覆盖部分初始鳍部和修正鳍部侧壁；
横跨初始鳍部的第一栅极结构，第一栅极结构包括第一栅介质层，所述第一栅极结构环绕初始鳍部的第一鳍部层；
横跨修正鳍部的第二栅极结构，所述第二栅极结构包括第二栅介质层，所述第二栅介质层厚度大于所述第一栅介质层厚度。
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