TW201724351A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201724351A
TW201724351A TW105128818A TW105128818A TW201724351A TW 201724351 A TW201724351 A TW 201724351A TW 105128818 A TW105128818 A TW 105128818A TW 105128818 A TW105128818 A TW 105128818A TW 201724351 A TW201724351 A TW 201724351A
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substrate
epitaxial
semiconductor
trenches
isolation
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TW105128818A
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李彥儒
李啟弘
丁姮彣
徐梓翔
金志昀
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台灣積體電路製造股份有限公司
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

一種半導體裝置包含基板、至少一第一隔離結構、至少二第二隔離結構以及複數個磊晶結構。基板具有複數個半導體鰭片於其中。第一隔離結構置於半導體鰭片之間。半導體鰭片置於第二隔離結構之間，且相較於第一隔離結構，第二隔離結構更往基板的內部延伸。磊晶結構分別置於半導體鰭片上。磊晶結構彼此分離，且至少一磊晶結構具有實質為圓形的輪廓。

Description

半導體裝置及其製造方法
本揭露是有關於一種半導體裝置。
半導體裝置被使用於大量的電子設備中，例如電腦、手機與其他電子設備。半導體裝置具有形成於半導體晶圓上的整合電路(integrated circuits)，且所述整合電路係透過將多種類型的材料薄膜沉積於半導體晶圓與圖案化材料薄膜而形成。整合電路具有場效電晶體(field-effect transistor,FET)，如金屬氧化物半導體(metal oxide semiconductor,MOS)電晶體。
在改善半導體效能與減少半導體尺寸的競賽中，半導體被發展成其通道與源極/汲極區位於形成於塊基板(bulk substrate)上的一鰭片。此類非平面的器件為多閘極鰭式場效電晶體(FinFET)。多閘極鰭式場效電晶體可以有閘極電極，且閘極電極跨越於鰭形矽主體，以形成通道區。
本揭露實施方式提供一種半導體裝置，半導體裝置包含基板、至少一第一隔離結構、至少二第二隔離結構以及複數個磊晶結 構。基板具有複數個半導體鰭片於其中。至少一第一隔離結構置於半導體鰭片之間。半導體鰭片置於第二隔離結構之間，且第二隔離結構相較於第一隔離結構更往基板的內部延伸。磊晶結構分別置於半導體鰭片上。磊晶結構彼此分隔，且至少一磊晶結構具有實質為圓形的輪廓。
102‧‧‧冠狀結構
110‧‧‧基板
112、112’、114‧‧‧溝槽
116‧‧‧半導體鰭片
117、125‧‧‧第一部分
118、126‧‧‧第二部分
118t、126t‧‧‧頂表面
122、124‧‧‧隔離結構
130‧‧‧閘極堆疊
132‧‧‧閘極介電層
134‧‧‧閘極電極
140‧‧‧間隔
160、165‧‧‧磊晶結構
162、167‧‧‧頂部
164、169‧‧‧主體部
170‧‧‧磊晶層
175‧‧‧保護層
7-7、9-9‧‧‧線段
d1‧‧‧深度
d2‧‧‧第二深度
d3‧‧‧第三深度
d4‧‧‧第四深度
G‧‧‧間隙
W1、W2、W3、W4、W5‧‧‧寬度
R‧‧‧凹槽
為使能更進一步瞭解本揭露之特徵及技術內容，請參閱以下有關本揭露之詳細說明與附圖。值得一提的是，相應此產業的一般性作法，多種特徵並未受限於尺度。事實上，多種特徵的尺寸可以任意增加或減少，以使說明更明確。
第1~6與8圖係為根據本揭露一些實施方式之方法製造的半導體裝置在不同階段的透視圖。
第7圖是第6圖沿著線段7-7的剖面圖。
第9圖是第8圖沿著線段9-9的剖面圖。
第10圖與第11圖是根據本揭露實施方式之方法製造的第9圖之半導體裝置於後續階段的透視圖。
下面的揭露內容提供不同的實施方式或例子來實現提供之標的物的不同特徵。元件與配置方式的特定例子被描述於後續內容中，以簡化本揭露內容。當然，該些內容僅是例子，而非打算用來限制本揭露內容。舉例來說，通過或基於第二特徵之第一特徵的形成於後續說明內容中將可能包含第一特徵與第二特徵直接關聯形成的實 施方式，且也可能包含形成於第一與第二特徵間之額外特徵的實施方式，如此，第一與第二特徵可能不會直接關聯。另外，本揭露內容於複數個例子中可能使用重複的元件符號。重複使用的原因係為了使本揭露內容精簡與明確，且其本身並沒有指定複數個實施方式與/或討論的組態之間的關係。
更進一步地，空間上的相對用語，例如「在...之下」、「在下面」、「低於」、「在上面」、「高於」與其類似用語，於此係用來簡化說明圖式中一個元件或特徵與另外一個或複數個元件或特徵之關係。空間上的相對用語打算用來涵蓋圖式以外之器件於使用或操作的不同定向。除此之外，裝置可能轉向(旋轉90度或位於其他定向)，且使用之空間上相關描述符於此處可以對應地被解釋。
第1~6與8圖係為根據本揭露一些實施方式之方法製造的半導體裝置在不同階段的透視圖。參照第1圖，基板110被提供。在一些實施方式中，基板110可以是半導體材料且可包含已知的結構例如包含漸變層(graded layer)或內埋氧化物(buried oxide)。在一些實施方式中，基板110包含未摻雜或摻雜(例如，P型、N型或其組合)的塊矽。適合於半導體裝置之形成的其他材料也可以被使用。其他材料，例如鍺、石英、藍寶石與玻璃可以擇一地用於基板110。或者，基板110可以是絕緣體基板上的半導體(SOI)之主動層或多層結構，例如，形成於塊矽層上的矽鍺層。
至少二溝槽(trenches)112’形成於基板110中。溝槽112’可以使用遮罩(masking)層配合適當的蝕刻製程來形成。舉例來說，遮罩層可以是透過製程而包含氮化矽的硬光罩(hardmask)，所述製程例如是化學氣相沉積(chemical vapor deposition,CVD)。儘管如此，其他材 料，例如氧化物、氮氧化物、碳矽化物或其組合等，以及其他製程，例如電漿增強(plasma enhanced)化學氣相沉積(PECVD)、低壓(low pressure)化學氣相沉積(LPCVD)或甚至是緊接於氮化後的氧化矽形成，也都可以被擇一使用。一但成形，遮罩層可以透過合適的微影製程(photography)對基板110進行圖案化以曝光基板110的那些部分，且接著移除部分來形成溝槽112’。
然而，本領域技術人員理當了解，當曝光基板110的其他部分以形成溝槽112’時，上述用來形成遮罩層的製程與材料並不是可以用來保護基板110之部分的唯一方式。其他適合的製程，例如圖案化與顯影的光阻劑可以擇一被使用來曝光基板110要被移除以形成溝槽112’的部分。全部的所述複數個方法最後將完整地被包含於本揭露的範圍。
一旦遮罩層被形成與圖案化，溝槽112’被形成於基板110中。曝光的基板110可以透過合適的製程被移除，例如，透過反應離子蝕刻(RIE)形成溝槽112’於基板110，儘管其他合適的製程也可以擇一地被使用。於其他實施方式中，溝槽112’可以形成而具有小於500奈米的深度d1，深度d1是由基板110之表面算起，例如為250奈米。如下面第2圖之說明，介於溝槽112’間之基板110的面積可以依序被圖案化以形成獨立的複數個鰭片。
參照第2圖，為了說明的方便，第2圖第1圖被放大以表示第1圖之溝槽112’的內部。至少一溝槽114被形成於第1圖的溝槽112’之間，且溝槽112’形成為溝槽112。舉例來說，於第2圖中，溝槽114被形成於溝槽112之間。溝槽114是介於共用相同閘極或者相同源極(汲 極)之兩分離之半導體鰭片116間的隔離區。溝槽112可以是位於不共用相同閘極、源極或汲極之鰭片間的隔離區。
溝槽114可以使用相同於形成溝槽112’之製程(其說明於第1圖)來形成，例如，合適的遮罩或微影製程與接著的蝕刻製程。額外地，溝槽114的形成也可以用來深化第1圖的溝槽112’，如此一來，相較於溝槽114，溝槽112延伸進入基板110更多一段距離。換言之，溝槽112比溝槽114還要深，且溝槽112的底表面低於溝槽114的底表面。這可利用一合適的遮罩以同樣曝光溝槽112與會被移除以形成溝槽114的基板110的區域。如此一來，溝槽112可以具有介於約20奈米到約700奈米的第二深度d2，例如，320奈米，且溝槽114可以形成而有具有介於約10奈米到約150奈米的第三深度d3，例如，1000奈米。值得注意的是，儘管第2圖的溝槽112與114具有尖角，但於其他實施方式中，溝槽112與114依據蝕刻條件可以具有圓角。
然而，如同本領域技術人員所能理解，上述用來形成溝槽112與114的製程僅為一種可行的製程，且並非用來限制其概念。儘管如此，用來形成溝槽112與114以使溝槽112比溝槽114更往基板110內延伸的其他合適的製程也可以被使用。舉例來說，溝槽112可在單一蝕刻步驟中形成，且接著在溝槽114形成的期間被保護。其他合適的製程，包含任何數量的遮罩與移除製程，皆可以擇一地被使用。
除了形成溝槽114，遮罩與蝕刻製程額外地從基板110未被移除的複數個部分形成複數個半導體鰭片116。半導體鰭片116如下所述可以用來形成半導體裝置的通道區。儘管第2圖說明了兩個半導體鰭片116自半導體基板110形成，但大於一之任何數量的半導體鰭片116也可被使用，如此會有溝槽112與114。於其他實施方式中，半導體 鰭片116可形成分離的通道區但仍靠得夠近以共享一共同閘極(其形成如下面相關於第4圖之說明)。
參照第3圖，溝槽112與114被介電質材料(圖未繪示)所填充。介電質材料可以陷於溝槽112與114中以分別形成隔離結構122(稱為第二隔離結構)與124(稱為第一隔離結構)。於其他實施方式中，隔離結構122相較於隔離結構124更延伸進入基板110。換言之，隔離結構122比隔離結構124還要深。隔離結構122定義出冠狀結構102於基板110中，且隔離結構124定義出複數個半導體鰭片116於冠狀結構102中。介電質材料可以是氧化物材料或高密度電漿(HDP)氧化物等。可以在選擇性的溝槽112與114之清洗與襯墊(lining)過程後，使用化學氣相沉積方法(例如，高深寬比填溝製程(High Aspect Ratio Process,HARP))、高密度電漿化學氣相沉積方法或其他本領域已知的合適形成方法來形成介電質材料。
藉由將溝槽112、114與基板110填滿介電質材料，並接著透過合適的製程移除溝槽112、114與基板110外部多出來的材料，溝槽112與114可以被填充，其中合適的製程例如為化學機械研磨(CMP)、蝕刻或其組合等。於其他實施方式中，移除製程也移除任何超出基板110的介電質材料，如此一來，介電質材料的移除可為下一步的製程操作而曝露基板110的表面。
一旦溝槽112與114已經被介電質材料所填充，介電質材料可以自基板110的表面被移除。所述移除可以被執行以暴露半導體鰭片116鄰近於基板110頂表面之側壁的至少一部分。介電質材料可以透過浸泡基板110的頂表面於蝕刻劑(例如，氟化氫(HF))的濕蝕刻方式被移除，儘管如此，其他蝕刻劑，例如氫(H2)，其他方法，例如反應離 子蝕刻、使用蝕刻劑(例如為氨(NH3)/氟化氮(NF3))的乾蝕刻、化學氧化物移除、或乾化學清洗都可以擇一地被使用。介電質材料可以被移除到從基板110的表面起算的第四深度d4，且介於約5奈米到約50奈米，例如為40奈米。另外，所述移除也可以移除位於基板110上任何殘留的介電質材料，以確保基板110於下一步的製程被曝露。
然而，如本領域技術人員所理解的，上述步驟僅是用以填充與移除介電質材料之全部製程流程的一部分。舉例來說，襯墊步驟、清洗步驟、退火步驟、間隙填充步驟或其組合等都能被用來形成介電質材料於溝槽112與114與對溝槽112與114填充介電質材料。全部可能的製程步驟可完整地被包含於本揭露實施方式的範圍內。
參照第4圖，形成閘極堆疊130於半導體鰭片116的部分與隔離結構122與124的部分。閘極堆疊130包含閘極介電層132與閘極電極134。閘極介電層132的形成可以透過熱氧化、化學氣相沉積、濺射(sputtering)或其他任何被本領域技術人員已知或用來沉積閘極介電層的方法來完成。根據閘極介電層的形成技術，閘極介電層132在半導體鰭片116上的厚度可以不同於閘極介電層132在半導體鰭片116之側壁上的厚度。
閘極介電層132可以包含例如二氧化矽或氮氧化矽的材料，且所述材料具有約3埃到10埃左右的厚度，例如10埃。閘極介電層132可以擇一地由高介電常數(高k)材料(例如，具有約比5大的相對介電常數)形成，例如鑭氧化物(La2O3)、鋁氧化物(Al2O3)、鉿氧化物(HfO2)、鉿氮氧化物(HfON)或鋯氧化物(ZrO2)或上述的組合，且具有大約0.5埃到100埃之等效氧化物厚度，例如10埃或更少。另外，二氧 化矽、矽氮氧化物與/或高介電常數(高k)材料的組合也可以用於閘極介電層132。
閘極電極134可以形成於閘極介電層132之上。閘極電極134可以包含導電材料，且可以選自具有多晶矽(poly-Si)、多晶矽-鍺(聚矽鍺(poly Si-Ge))、金屬氮化物、金屬矽化物、金屬氧化物、金屬與上述組合等。金屬氮化物的實施例包含氮化鎢、氮化鉬、氮化鈦、氮化鉭或者它們的組合。金屬矽化物的實施例包含矽化鎢、矽化鈦、矽化鈷、矽化鎳、矽化鉑、鉺矽化物或它們的組合。金屬氧化物的實施例包含氧化釕、氧化銦錫或它們的組合。金屬的實施例包含鎢、鈦、鋁、銅、鉬、鎳或鉑等。
閘極電極134可以透過化學氣相沉積、濺射沉積或其他本領域人員知悉與使用的用以沉積導電材料的其他技術，而被沉積。閘極電極134的厚度可以介於大約200埃到大約4000埃之間的範圍。於此製程，離子可被或可不被引入於閘極電極134。舉例來說，離子可以透過離子佈植技術被引入。
閘極堆疊130定義出位於閘極介電層132下方的半導體鰭片116中的複數個通道區(亦即，第一部分117)。閘極堆疊130可以透過沉積與圖案化閘極電極層上的閘極遮罩(圖未繪示)來形成，例如使用本領域人員所知悉的沉積與微影技術。閘極遮罩可以包含常用的遮罩材料，例如(但不限制於此)光阻劑材料、氧化矽、氧氮化矽與/或氮化矽。乾蝕刻製程可以用來形成圖案化的閘極堆疊130。
一旦閘極堆疊130被圖案化，一組間隔140可以被形成。間隔140形成於閘極堆疊130的兩相反側。間隔140典型地透過毯覆沉積(blanket depositing)間隔層(圖未繪示)於先前形成的結構來形成。間隔 層可包含氮化矽、氮氧化物、碳化矽、氮氧化與氧化物等，且可以透過用於形成所述層的方法來形成，例如化學氣相沉積、電漿增強化學氣相沉積、濺射或本領域人員已知的其他方法。間隔層所包含材料的蝕刻特性可以不同或相同於隔離結構122與124的介電質材料。間隔140可以接著被圖案化，例如透過一次或多次蝕刻從結構的水平面來移除間隔層。
於第4圖中，至少一半導體鰭片116具有至少一第一部分117與至少一第二部分118。閘極堆疊130和間隔140覆蓋第一部分117，且未覆蓋第二部分118。也就是說，第二部分118被閘極堆疊130和間隔140所暴露。此外，隔離結構124具有至少一第一部分125和至少一第二部分126。閘極堆疊130和間隔140覆蓋第一部分125，且未覆蓋第二部分126。也就是說，第二部分126被閘極堆疊130和間隔140所暴露。
參考第5圖，半導體鰭片116的第二部分118的部分從未被閘極堆疊130與間隔140保護的區域被移除，使得半導體鰭片116的第一部分117的側壁從間隔140露出。半導體鰭片116之殘留第二部分118的頂表面118t位於隔離結構124的第二部分126的頂表面126t下。因此，隔離結構122的一者、隔離結構124與半導體鰭片116的一者共同形成凹槽R。所述移除可透過反應離子蝕刻使用閘極堆疊130與間隔140作為硬遮罩來完成，或者透過其他合適的移除製程。在一些實施方式中，蝕刻製程在約1毫托到1000毫托的壓力、約50瓦至1000瓦的功率、約20伏特到500伏特的偏壓電壓與約40℃到60℃的溫度的情況下，使用溴化氫(HBr)和/或氯氣(Cl2)作為蝕刻氣體來實現。在其他的實施方式中，在蝕刻製程中使用的偏壓電壓可以被調整，以允許蝕刻方向的良好控 制，從而達到半導體鰭片116之剩餘(或凹陷)之第二部分118的需求輪廓。在此請注意，儘管在第5圖中，剩餘的第二部分118具有尖角，但在其他實施方式中，剩餘的第二部分118基於蝕刻條件可能具有圓角。
參照第6圖與第7圖，第7圖是第6圖沿著線段7-7的剖面圖。複數個磊晶結構160形成於凹槽R中且位於半導體鰭片116之剩餘的第二部分118上。隔離結構124的第二部分126置於複數個磊晶結構160之間。由於磊晶結構160的晶格常數(lattice constant)不同於基板110，半導體鰭片116的通道區被緊縮或壓縮以致能裝置的載子遷移率與增強裝置效能。在一些實施方式中，磊晶結構160，例如碳化矽，可透過低壓化學氣相沉積製程來磊晶成長從而形成N型鰭式場效電晶體的源極與汲極。低壓化學氣相沉積製程可以在約400℃到800℃的溫度與約1到200托的壓力下，使用Si3H8與SiH3CH作為反應氣體來實現。在一些實施方式中，磊晶結構160，例如矽鍺，可透過低壓化學氣相沉積製程來磊晶成長從而形成P型鰭式場效電晶體的源極與汲極。低壓化學氣相沉積製程可以在約400℃到800℃的溫度與約1到200托的壓力下，使用SiH4與GeiH4作為反應氣體來實現。
在第7圖中，至少一磊晶結構160具有頂部162與主體部164。主體部164置於頂部162與半導體鰭片116之凹陷的第二部分118的一者之間。主體部164更進一步地置於凹槽R之中。頂部162具有寬度W1，且主體部164具有小於寬度W1的寬度W2。至少一之半導體鰭片116具有實質相同於寬度W2的寬度W3。隔離結構122與124置於磊晶結構160之主體部164的相對側，且磊晶結構160的頂部162置於隔離結構122與124上。
在一些實施方式中，頂部162高於或實質等於半導體鰭片116的第一部分117。也就是說，半導體鰭片116的第一部分117之側壁暴露出間隔140(如第5圖)，且被磊晶結構160的頂部162所覆蓋。頂部162具琢面(facet)表面。於磊晶製程中，磊晶結構160的磊晶成長可以垂直與水平延伸，如此，磊晶結構160在一些實施方式中可以結合在一起(或物理性連接)。
參考第8圖與第9圖，第9圖是第8圖沿著線段9-9的剖面圖。第6圖中的磊晶結構160的部分被移除。舉例來說，回蝕製程可以在磊晶結構160上被執行以形成不具琢面的磊晶結構165。也就是說，磊晶結構165實質具有圓形輪廓(或非琢面表面)。更進一步地，磊晶結構165彼此分隔，亦即，間隙G形成於磊晶結構165之間，且位於隔離結構124的第二部分126上。在一些實施方式中，在形成第6圖之磊晶結構160時，蝕刻氣體(例如，氯化氫)可以被引入相同腔室。在一些實施方式中，磊晶結構160的磊晶成長與蝕刻可以是在原位執行，也就是，在其間沒有真空中斷之相同的製程腔室中執行。在蝕刻過程中，磊晶結構160的角可以比其平面被移除地更多，因此磊晶結構160的表面輪廓因此可以是圓形。在一些實施方式中，在蝕刻步驟後，磊晶結構165具有橢圓形狀。蝕刻步驟可以包含，例如將氯化氫或氯化氫與氫化鍺(GeH4)的組合引入製程腔室。在將氯化氫與氫化鍺引入製程腔室時，晶圓溫度於蝕刻步驟中可以大於約500℃，或者在將氯化氫引入製程腔室(氫化鍺並未引入)時，晶圓溫度可以大於約700℃。在蝕刻步驟中，電漿可以被激活，也可以不被激活。
在第9圖中，至少一磊晶結構160具有頂部167與主體部169。頂部167具有實質為圓形的輪廓(或非琢面表面)與寬度W4。主體 部169置於頂部167與半導體鰭片116的其中一者，且具有小於寬度W4的寬度W5。在一些實施方式中，寬度W4小於寬度W1(見第7圖)並大於寬度W5。寬度W5實質等於寬度W2(見第7圖)與W3。也就是說，儘管蝕刻製程縮減了磊晶結構160的頂部162之寬度W1，縮減後的寬度W4仍然大於主體部164或169的寬度W5。
由於磊晶結構165的頂部167的寬度W4被縮減，於兩磊晶結構165可靠得更近但仍彼此分離。換言之，半導體鰭片116之間的距離可以被縮減。如此，半導體裝置的整合密度可以被增加，且相同的面積下可以容置更多的元件。
另外，磊晶結構165的至少一頂部167更具有高度H。頂部167的高度H對頂部167的寬度W4的比值大約從0.5到大約4。如果比值不等於1，頂部167為如第8圖所示的橢圓柱狀，如果比值實質等於1，頂部167為圓柱狀。
第10圖與第11圖是根據本揭露實施方式之方法製造的第9圖之半導體裝置於後續階段的透視圖。在一些實施方式中，磊晶層170被形成以覆蓋磊晶結構165。磊晶層170可以使用如形成磊晶結構160之合適的磊晶成長製程來形成(如同上述第6圖的相關內容)。在一些實施方式中，磊晶層170與磊晶結構165可以實質使用相同材料來製成。然而，磊晶層170與磊晶結構165可以使用不同的材料來製成。在一些實施方式中，磊晶層170可以由碳化矽、矽鍺或其他合適的半導體材料來製成。在一些實施方式中，磊晶層170之鍺濃度可以小於約40%。
在第10圖中，磊晶層170可具有琢面，如此一來，另一蝕刻製程可以被執行以使磊晶層170的表面更平滑。參照第11圖，磊晶層170的部分可以被移除(或蝕刻)以形成保護層175。如此，保護層175 具有實質為圓形或非琢面的表面。磊晶層170可以使用如蝕刻磊晶結構160之相同的製程來蝕刻(如同上述第8圖的相關內容)。保護層170可以防止磊晶結構165於後續蝕刻製程所造成的損害。
從第10圖到第11圖的製程又稱作沉積-蝕刻製程循環(cycle)。在一些實施方式中，至少一個以上的循環可以被執行於磊晶結構165上。也就是說，保護層170可以是多層結構，且本揭露所保護的範圍不限制於此。
根據上述實施方式，由於磊晶結構的頂部之寬度可以透過移除頂部的部分來縮減，相鄰的磊晶結構(或相鄰的半導體鰭片)可以配置地更近，且相同面積下可以容置更多元件以增加半導體裝置的整合密度。
根據一些實施方式，半導體裝置包含基板、至少一第一隔離結構、至少二第二隔離結構以及複數個磊晶結構。基板具有複數個半導體鰭片於其中。至少一第一隔離結構置於半導體鰭片之間。半導體鰭片置於第二隔離結構之間，且第二隔離結構相較於第一隔離結構更往基板的內部延伸。磊晶結構分別置於半導體鰭片上。磊晶結構彼此分隔，且至少一磊晶結構具有實質為圓形的輪廓。
根據一些實施方式，半導體裝置包含基板、至少一第一隔離結構、複數個第二隔離結構、第一磊晶結構與第二磊晶結構。基板具有第一半導體鰭片與第二半導體鰭片於其中。第一隔離結構置於第一半導體鰭片與第二半導體鰭片之間。第二隔離結構定義出冠狀結構於基板中。第一半導體鰭片置於冠狀結構中且置於第二隔離結構的其中一者與第一隔離結構之間，第二半導體鰭片置於冠狀結構中且置於第二隔離結構的另一者與第一隔離結構之間。第一磊晶結構置於第 一半導體鰭片上且具有非琢面表面。第二磊晶結構置於第二半導體鰭片上且具有另一非琢面表面。間隙形成於第一磊晶結構與第二磊晶結構之間。
根據一些實施方式，一種用以製造半導體裝置的方法被提供。形成至少一第一隔離結構與複數個第二隔離結構於基板。第二隔離結構定義出冠狀結構於基板中，且第一隔離結構定義出複數個半導體鰭片於冠狀結構中。形成閘極堆疊(gate stack)覆蓋半導體鰭片的第一部分與第一隔離結構的第一部分，且未覆蓋半導體鰭片的第二部分與第一隔離結構的第二部分。移除半導體鰭片之第二部分的部分。形成複數個磊晶結構於半導體鰭片之剩餘的第二部分上。移除磊晶結構的部分。
上述內容概述複數個實施方式的複數個特徵，使得本領域技術人員可以更加地明白本揭露的概念。本領域技術人員能夠應當理解，基於本揭露的基礎去設計或修改其他製程與結構以實現本揭露實施方式中所述之類似的目的與/或優點係為可行的。在不脫離本揭露範圍之精神的情況下，本領域技術人員也能夠實現所述等效架構，並完成任何類型的修改、替代或置換。
110‧‧‧基板
116‧‧‧半導體鰭片
117‧‧‧第一部分
118‧‧‧第二部分
122、124‧‧‧隔離結構
126‧‧‧第二部分
160‧‧‧磊晶結構
162‧‧‧頂部
164‧‧‧主體部
R‧‧‧凹槽
W1、W2、W3‧‧‧寬度

Claims (1)

  1. 一種半導體裝置，包含：一基板，具有複數個半導體鰭片於其中；至少一第一隔離結構，置於該些半導體鰭片之間；至少二第二隔離結構，其中該些半導體鰭片置於該些第二隔離結構之間，且該些第二隔離結構相較於該第一隔離結構更往該基板的內部延伸；以及複數個磊晶結構，分別置於該些半導體鰭片上，其中該些磊晶結構彼此分隔，且該至少一磊晶結構具有實質為圓形的一輪廓。
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