CN105097807A - FinFET器件的结构和形成方法 - Google Patents

FinFET器件的结构和形成方法 Download PDF

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CN105097807A
CN105097807A CN201510230956.5A CN201510230956A CN105097807A CN 105097807 A CN105097807 A CN 105097807A CN 201510230956 A CN201510230956 A CN 201510230956A CN 105097807 A CN105097807 A CN 105097807A
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fin
extension
extension fin
isolation structure
groove
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CN105097807B (zh
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赖盈桦
张家铭
江宗育
陈光鑫
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了半导体器件，该半导体器件包括半导体衬底和位于半导体衬底上方的隔离结构。半导体器件还包括位于半导体衬底上方的第一外延鳍和第二外延鳍，并且第一外延鳍和第二外延鳍从隔离结构中突出。半导体器件还包括位于第一外延鳍和第二外延鳍上方且横跨第一外延鳍和第二外延鳍的栅极堆叠件。此外，半导体器件包括从隔离结构的顶面开始延伸的凹槽。凹槽介于第一外延鳍和第二外延鳍之间。本发明的实施例还提供了一种形成半导体器件的方法。

Description

FinFET器件的结构和形成方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及FinFET器件的结构和方法。
背景技术
半导体器件用于诸如个人计算机、手机、数码照相机和其他电子设备的各种电子应用中。通过下列步骤制造半导体器件：在半导体衬底上方顺序地沉积绝缘或介电层、导电层、和半导体层，以及使用光刻和蚀刻工艺来图案化各种不同材料层以在半导体衬底上形成电路组件和元件。
在追求更高器件密度、更高性能和更低成本的过程中，半导体工业已发展进入到纳米技术工艺节点，来自制造和设计问题的挑战已导致诸如鳍状场效应晶体管(FinFET)的三维设计的发展。FinFET制造有从衬底处延伸的薄而垂直“鳍”(或鳍结构)。FinFET的沟道形成在该垂直鳍中。在鳍上方提供有栅极。FinFET的优势可包括降低短沟道效应和较高的电流。
然而，因为特征尺寸持续减小，制造工艺继续变得更难以实施。因此，在形成包括FinFET的可靠半导体器件方面存在挑战。
发明内容
根据本发明的一个方面，提供了一种半导体器件，包括：半导体衬底；隔离结构，位于半导体衬底上方；第一外延鳍和第二外延鳍，位于半导体衬底上方，其中，第一外延鳍和第二外延鳍从隔离结构中突出；栅极堆叠件，位于第一外延鳍和第二外延鳍上方且横跨第一外延鳍和第二外延鳍；以及凹槽，从隔离结构的顶面处开始延伸，其中，凹槽介于第一外延鳍和第二外延鳍之间。
优选地，栅极堆叠件包括金属材料。
优选地，第一外延鳍和第二外延鳍的材料彼此不同。
优选地，第二外延鳍包括磷化硅、碳化硅或它们的组合。
优选地，第一外延鳍包括硅锗。
优选地，凹槽的延伸方向与第一外延鳍和第二外延鳍的延伸方向基本平行。
优选地，该半导体器件还包括：第一接触件，位于半导体衬底上方且电连接至第一外延鳍；第二接触件，位于半导体衬底上方且电连接至第二外延鳍；以及介电层，位于半导体衬底上方且围绕第一接触件和第二接触件。
优选地，第一接触件填充凹槽，并且第一外延鳍包括p型外延鳍。
优选地，第二接触件填充凹槽，并且第二外延鳍包括n型外延鳍。
优选地，介电层填充凹槽。
根据本发明的另一方面，提供了一种半导体衬底，包括：半导体衬底；隔离结构，位于半导体衬底上方；n型外延鳍和p型外延鳍，位于半导体衬底上方，其中，n型外延鳍和p型外延鳍从隔离结构中突出；栅极堆叠件，位于n型外延鳍和p型外延鳍上方且横跨n型外延鳍和p型外延鳍；以及凹槽，从隔离结构的顶面处开始延伸，其中，凹槽介于n型外延鳍和p型外延鳍之间。
优选地，栅极堆叠件包括金属材料。
优选地，凹槽的延伸方向与n型外延鳍和p型外延鳍的延伸方向基本平行。
优选地，该半导体器件还包括：第一接触件，位于半导体衬底上方且电连接至p型外延鳍；第二接触件，位于半导体衬底上方且电连接至n型外延鳍；以及介电层，位于半导体衬底上方且围绕第一接触件和第二接触件。
优选地，第一接触件和第二接触件中的一个填充凹槽。
根据本发明的又一方面，提供了一种形成半导体器件的方法，包括：在半导体衬底上方形成第一鳍和第二鳍；在半导体衬底上方形成隔离结构以围绕第一鳍的下部和第二鳍的下部；在第一鳍上方和第二鳍上方形成栅极堆叠件，其中，栅极堆叠件横跨第一鳍和第二鳍；以及分别在第一鳍和第二鳍上方顺序地形成第一外延鳍和第二外延鳍，其中，在形成第一外延鳍之后和在形成第二外延鳍之前在隔离结构中形成凹槽，并且凹槽介于第一外延鳍和第二外延鳍之间。
优选地，顺序地形成第一外延鳍和第二外延鳍的步骤包括：在第二鳍上方形成第一掩模层；在形成第一掩模层之后在第一鳍上方形成第一外延鳍；去除第一掩模层；在第一外延鳍上方形成第二掩模层；在形成第二掩模层之后在第二鳍上方形成第二外延鳍；以及去除第二掩模层。
优选地，该方法还包括：在形成第一外延鳍之前使第一鳍凹进；以及在形成第二外延鳍之前使所述第二鳍凹进。
优选地，在使所述第二鳍凹进之后且形成所述第二外延鳍之前形成所述凹槽。
优选地，该方法还包括：在所述栅极堆叠件上方形成硬掩模层，其中，在形成所述凹槽的同时在所述硬掩模层中形成第二凹槽，并且所述第二凹槽与所述凹槽基本对准。
附图说明
当结合附图进行阅读时，通过下列详细的描述，可以理解本发明的各方面。应该强调的是，根据工业中的标准实践，没有按比例绘制各种部件。实际上，为了清楚地讨论，各种部件的尺寸可以被任意增加或减少。
图1A至图1L是根据一些实施例的形成半导体器件的工艺的不同阶段的截面图。
图2A是根据一些实施例的半导体器件的立体图。
图2B是根据一些实施例的半导体器件的顶视图。
图3A是根据一些实施例的半导体器件的顶视图。
图3B是根据一些实施例的半导体器件的栅极堆叠件的截面图。
图4A至图4C是根据一些实施例的半导体器件的栅极堆叠件的截面图。
具体实施方式
以下公开提供了多种不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
此外，在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语，以容易的描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除图中所示的方位之外，空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其他方式定位(旋转90度或在其他方位)，并且通过在此使用的空间关系描述符进行相应地解释。
图1A至图1L是根据一些实施例的形成半导体器件的工艺的不同阶段的截面图。在一些实施例中，半导体器件是鳍状场效应晶体管(FinFET)器件。如图1A所示，提供了半导体衬底100。在一些实施例中，半导体衬底100是块状半导体衬底，诸如，硅晶圆。在其他一些实施例中，半导体衬底100包括诸如锗的其他元素半导体或包括化合物半导体。化合物半导体可包括碳化硅、砷化镓、砷化铟、磷化铟、其他合适的化合物半导体或它们的组合。在一些实施例中，半导体衬底100包括绝缘体上半导体(SOI)衬底。可以使用注氧隔离(SIMOX)工艺、晶圆接合工艺、其他合适的方法或它们的组合来制造SOI衬底。
如图1A所示，根据一些实施例，FinFET器件还包括从半导体衬底100处延伸出来的多个鳍104。在一些实施例中，鳍104包括硅鳍、锗鳍、其他合适的半导体鳍或它们的组合。在一些实施例中，通过蚀刻半导体衬底100而形成鳍104。如图1A所示，使用光刻工艺和蚀刻工艺在半导体衬底100中形成凹槽(或沟槽)102。因此，在各凹槽102之间形成鳍104。在一些实施例中，凹槽102是彼此平行且彼此间隔开的条形带(从FinFET器件的顶部观察)。
如图1A所示，半导体衬底100包括第一区101n和第二区101p。边界L位于第一区101n和第二区101p之间。在一些实施例中，第一区101n用于形成n型FinFET器件，而第二区101p用于形成p型FinFET器件。
如图1B所示，根据一些实施例，使一些鳍凹进以形成伪鳍104d。在一些实施例中，通过使用蚀刻工艺使鳍凹进。在一些实施例中，未凹进的鳍104n和104p分别用作NMOS器件和PMOS器件的沟道鳍。在一些实施例中，使鳍104n和104p之间的鳍凹进成为伪鳍104d，以防止在后续工艺中在鳍104n和104p之间发生短路。
如图1B所示，根据一些实施例，在半导体衬底100上方形成隔离结构106。隔离结构106围绕鳍104n和104p的下部。鳍104n和104p的上部从隔离结构106的顶面处突出。在一些实施例中，隔离结构106由介电材料制成。介电材料可包括氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(FSG)、低K介电材料、其他合适的材料或它们的组合。
在一些实施例中，在半导体衬底100上方沉积介电材料层。介电材料层覆盖鳍104n和104p以及伪鳍104d。在一些实施例中，使用化学汽相沉积(CVD)工艺、旋涂工艺、其他可应用的工艺或它们的组合来沉积介电材料层。在一些实施例中，实施诸如化学机械抛光(CMP)工艺的平坦化工艺以使介电材料层变薄，直到暴露出鳍104n和104p。然后，实施蚀刻工艺以去除介电材料层的一部分，使得鳍104n和104p从剩余的介电材料层中突出。因此，形成隔离结构106。
然后，在半导体衬底100上方形成栅极结构。图2A是根据一些实施例的在图1B示出的结构上方形成栅极结构之后的半导体器件的透视图。图2B是根据一些实施例的半导体器件的截面图。图1B是根据一些实施例的从图2B中的截线I-I截取得到的截面图。如图2A和图2B所示，在鳍104n和104p上方形成栅极堆叠件108。在一些实施例中，栅极堆叠件108横穿且包裹在鳍104n和104p周围。如图2B所示，栅极堆叠件108在第一区101n和第二区101p上方延伸。
栅极堆叠件108包括栅极介电层(未示出)和位于栅极介电层上方的栅电极(未示出)。在一些实施例中，栅极介电层由氧化硅、氮化硅、氮氧化硅、具有高介电常数(高K)的介电材料、其他合适的介电材料或它们的组合构成。高K介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝(alumina)合金、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪等或它们的组合。在一些实施例中，栅电极包括多晶硅或金属材料，诸如，TiN、TaN、NiSi、CoSi、Mo、Cu、W、Al、Co、Zr、Pt、其他合适的材料或它们的组合。在一些实施例中，栅极介电材料层和栅电极层顺序地沉积在隔离结构106以及鳍104n和104p上方。然后，栅极介电材料层和栅电极被图案化以形成栅极堆叠件108。
在一些实施例中，在栅电极层上方沉积和图案化硬掩模层(图2A中未示出)。硬掩模层用于辅助形成栅极堆叠件108。在一些实施例中，硬掩模层由氮化硅、其他合适的材料或它们的组合制成。
如图1C和图2A所示，根据一些实施例，在鳍104n和104p、隔离结构106和栅极堆叠件108上方沉积掩模层112。在一些实施例中，硬掩模层112由氮化硅、氮氧化硅、其他合适的材料或它们的组合制成。在一些实施例中，使用CVD工艺、旋涂工艺、喷射(spraying)工艺、其他合适的工艺或它们的组合来沉积掩模层112。
如图1D所示，根据一些实施例中，在掩模层112上方形成感光层114。在一些实施例中，感光层114包括光刻胶层且使用光刻工艺形成。光刻工艺可包括光刻胶涂布(例如，旋涂)、软烘、掩模对准、曝光、曝光后烘烤、使光刻胶显影、清洗、干燥(例如，硬烘)、其他合适的工艺或它们的组合。如图1D所示，感光层114覆盖掩模层112中位于第一区101n上方的大部分。然而，掩模层112中邻近区101n和101p之间的边界L且位于第一区101n上方的部分露出。也暴露出掩模层112中位于第二区101p上方且没有被光刻胶层114覆盖的部分。
如图1E所示，根据一些实施例，去除未被感光层114覆盖的掩模层112。因此，感光层114的图案被基本转印至掩模层112中。在一些实施例中，隔离结构106的一部分在去除未被感光层114覆盖的掩模层112的同一蚀刻工艺期间也被去除。在一些实施例中，通过使用以掩模层112为蚀刻掩模的蚀刻工艺使鳍104p(参见图1D)凹进以形成凹进的鳍104p’。在一些实施例中，如图1E所示，凹进的鳍104p’和隔离结构106的顶面基本彼此共平面。在其他其他一些实施例中，凹进的鳍104p’的顶面低于隔离结构106的顶面。换言之，蚀刻鳍104p以形成其顶面比隔离结构106的顶面低的凹进的鳍104p’。在一些实施例中，在形成凹进的鳍104p的蚀刻工艺期间进一步去除隔离结构106的一部分。本发明的实施例具有诸多变型。在其他其他一些实施例中，未使鳍104p凹进。
如上所述，在去除掩模层112和使鳍凹进的蚀刻工艺期间可去除隔离结构106的未被掩模层112覆盖的上部。如图1E所示，因此在隔离结构106中被掩模层112覆盖和未被掩模层112覆盖的部分之间形成阶梯高度d1。在一些实施例中，阶梯高度d1在约1nm至约25nm的范围内。然后，去除感光层114。
如图1F所示，根据一些实施例，在凹进的鳍104p’上方选择性地生长外延材料以形成外延鳍116p。在外延鳍116的生长期间，掩模层112防止外延材料生长在鳍104n上。在一些实施例中，外延鳍116p是应变材料，诸如，硅锗(SiGe)或其他合适的材料。外延鳍116用作发生应变的源极和漏极区。因此，栅极堆叠件108下面的沟道区发生应变或受到应力以增加器件的载流子迁移率和增强器件性能。在一些实施例中，外延鳍116p的表面积大于鳍104p的表面积。可进一步降低外延鳍116p和后续形成的接触件之间的电阻。
在一些实施例中，通过使用CVD工艺(诸如，低压化学汽相沉积(LPCVD))外延生长外延鳍116以在第二区101p中形成p型FinFET器件的源极和漏极区。在一些实施例中，在约400摄氏度至约800摄氏度的温度和约1Torr至约200Torr的压力下实施外延鳍116p的外延生长。例如，将SiH4和GeH4用作为反应气体。
本发明的实施例具有诸多变型。在一些实施例中，没有使鳍104p凹进以形成凹进的鳍。在一些实施例中，在没有凹进的鳍104p上形成外延鳍116p。
之后，如图1G所示，根据一些实施例，去除掩模层112，从而暴露出鳍104n。可使用蚀刻工艺去除掩模层112。
如图1H所示，根据一些实施例，在鳍104n、隔离结构106和外延鳍116p上方沉积掩模层118。在一些实施例中，掩模层118由氮化硅、氮氧化硅、其他合适的材料或它们的组合制成。在一些实施例中，使用CVD工艺、旋涂工艺、喷射工艺、其他合适的工艺或它们的组合来沉积掩模层118。
如图1I所示，根据一些实施例，在掩模层118上方形成感光层120。在一些实施例中，感光层120包括光刻胶层且使用光刻工艺形成。光刻工艺可包括光刻胶涂布(例如，旋转涂布)、软烘、掩模对准、曝光、曝光后烘烤、使光刻胶显影、清洗、干燥(例如，硬烘)、其他合适的工艺或它们的组合。如图1I所示，感光层120覆盖掩模层118中位于第二区101p上方的大部分。然而，掩模层118中邻近区101n和101p之间的边界L以及位于第二区101p上方的一部分露出。也暴露出掩模层118中未被感光层120覆盖且位于第一区101n上方的部分。
如图1J所示，根据一些实施例，去除未被感光层120覆盖的掩模层118。因此，感光层120的图案被基本转印至掩模层118中。在一些实施例中，在去除未被感光层120覆盖的掩模层118的同一蚀刻工艺期间还去除隔离结构106的一部分。在一些实施例中，通过使用以掩模层118作为蚀刻掩模的蚀刻工艺使鳍104n凹进(参见图1I)以形成凹进的鳍104n’。在一些实施例中，如图1J所示，凹进的鳍104n’和隔离结构106的顶面基本彼此共平面。在其他一些实施例中，凹进的鳍104n’的顶面低于隔离结构106的顶面。换言之，蚀刻鳍104n以形成其顶面比隔离结构106的顶面低的凹进的鳍104n’。在一些实施例中，在使鳍104n凹进的蚀刻工艺期间进一步去除隔离结构106的一部分。本发明的实施例具有诸多变型。在其他一些实施例中，鳍104n未凹进。
如上所述，在去除掩模层118和使鳍凹进的蚀刻工艺期间可去除隔离结构106中未被掩模层118覆盖的上部。如图1J所示，根据一些实施例，形成从隔离结构106的顶面处延伸的凹槽122。凹槽122设置在邻近区101n和101p之间的边界L的区域。参见图1D和1I，可以发现，凹槽122设置在基本未被感光层114和120覆盖的区域。因此，在随后蚀刻工艺之后，因为邻近区101n和101p之间的边界L的区域未受保护，所以形成凹槽122。在一些实施例中，凹槽122沿着区域101n和101p之间的边界L延伸。之后，去除感光层120。
如图1K所示，根据一些实施例，在凹进的鳍104n’上方选择生长外延材料以形成外延鳍116n。在生长外延鳍116n期间，掩模层118防止外延材料生长在外延鳍116p上。在一些实施例中，外延鳍116n是应变材料，诸如，磷化硅(SiP)、碳化硅(SiC)和/或其他合适的材料。外延鳍116n用作发生应变的源极和漏极区。因此，栅极堆叠件118下面的沟道区发生应变或受到应力以增加器件的载流子迁移率和增强器件性能。在一些实施例中，外延鳍116n的表面积大于鳍104n的表面积。可进一步降低外延鳍116n和随后形成的接触件之间的电阻。
在一些实施例中，通过使用CVD工艺(诸如，低压化学汽相沉积(LPCVD))外延生长外延鳍116n以在第一区101n中形成n型FinFET器件的源极和漏极区。在一些实施例中，在约400摄氏度至约800摄氏度的温度和约1Torr至约200Torr的压力下实施外延鳍116n的外延生长。例如，SiH4混合有含磷气体和/或含碳气体以充当反应气体。
本发明的实施例具有诸多变型。在一些实施例中，鳍104n未凹进成为凹进的鳍。在一些实施例中，在未凹进的鳍104n上形成外延鳍116n。
在一些实施例中，外延鳍116n由不同于外延鳍116p的材料制成。在一些实施例中，外延鳍116n和外延鳍116p分别掺杂有n型掺杂剂和p型掺杂剂。在一些实施例中，外延鳍116n和116p均在其生长或形成期间掺杂有相应合适的掺杂剂。在其他其他一些实施例中，顺序地进行随后的注入工艺以使外延鳍116n和116p分别掺杂有合适的掺杂剂。
之后，如图1L所示，根据一些实施例，去除掩模层118，从而暴露出外延鳍116p。可使用蚀刻工艺去除掩模层112。如图1L所示，半导体器件包括第一鳍结构和第二鳍结构。在一些实施例中，第一鳍结构包括诸如凹进的鳍104p’的下部和诸如外延鳍116p的上部。同样地，第二鳍结构包括诸如凹进的鳍104n’的下部和诸如外延鳍116n的上部。如图1L所示，在一些实施例中，第一和第二鳍结构的上部从隔离结构106的顶面107处突出。
在一些实施例中，形成外延鳍116p之后且形成外延鳍116n之前形成凹槽122(参照图1J)。如图1L所示，凹槽122从隔离结构106的顶面107开始延伸。凹槽122具有深度d2和宽度w。在一些实施例中，深度d2在约1nm至约25nm的范围内。在一些实施例中，宽度w在约20nm至约90nm的范围内。在一些实施例中，凹槽122的纵横比在约0.05至约1.25的范围内。
本发明的实施例具有诸多变型。例如，外延鳍116n不限于在外延鳍116p之前形成。在其他一些实施例中，外延鳍116p形成在外延鳍116n之前。
图3A是根据一些实施例的半导体器件的顶视图。如图3A所示，形成互补金属氧化物半导体鳍状场效应晶体管(CMOSFinFET)器件。CMOSFinFET器件包括外延鳍116n和116p。
图3B是根据一些实施例的沿着图3A的截线B-B而截取的栅极堆叠件108的截面图。在一些实施例中，硬掩模层302形成在栅极堆叠件108上方以辅助形成栅极堆叠件108。在一些实施例中，在去除掩模层112和118和使鳍凹进的蚀刻工艺期间，还蚀刻栅极堆叠件108上方硬掩模层302。与凹槽122相似，感光层114和120均未覆盖区101n和101p之间的边界L上方的掩模层302。即，硬掩模层302中邻近区101n和101p之间的边界L的区域还未受保护。因此，减小硬掩模层302的厚度，并且形成与凹槽122相似的凹槽304。在一些实施例中，将感光层114和120的图案设计为部分重叠。因此，形成凹槽304和122。在一些实施例中，在形成凹槽122的同时形成凹槽304。
如图3B和3A所示，凹槽304沿着区101n和101p之间的边界L延伸。在一些实施例中，根据一些实施例，凹槽304和122彼此基本对准。在一些实施例中，凹槽304和122的延伸方向基本彼此平行。在一些实施例中，凹槽122和304的延伸方向与外延鳍116n和116p的延伸方向基本平行。
在一些实施例中，去除位于栅极堆叠件108上方的硬掩模层302有利于随后的工艺。例如，随后的工艺包括栅极替换工艺。在一些实施例中，去除硬掩模层302以暴露出例如由多晶硅制成的栅电极。之后，去除栅电极，并且形成金属栅电极以替换原始的栅电极。金属栅电极可包括功函层和金属填充层。
功函层被配置为向晶体管提供理想的功函以增强器件性能(包括提高的阈值电压)。在形成n型FinFET的实施例中，功函层可以为能够提供适于器件的功函数值(诸如，等于或小于约4.5eV)的n型金属。n型金属可包括金属、金属碳化物、金属氮化物或它们的组合。例如，n型金属包括钽、氮化钽或它们的组合。另一方面，在形成p型FinFET的实施例中，功函层可以为能够提供适于器件的功函数值(诸如，等于或大于约4.8eV)的p型金属。p型金属可包括金属、金属碳化物、金属氮化物、其他合适的材料或它们的组合。例如，p型金属包括钛、氮化钛、其他合适的材料或它们的组合。在一些实施例中，金属填充层由铝、钨、金、铂、钴、其他合适的金属或它们的组合制成。
因为感光层114和120的图案部分地重叠，所以蚀刻邻近区101n和101p之间的边界L的区域以形成凹槽304。在其他其他一些情况下，如果感光层114和120的图案未重叠，硬掩模层302可具有邻近区101n和101p之间的边界L的突出部分。因此，较难去除硬掩模层302。可能需要进行额外的蚀刻操作和/或平坦化工艺操作来去除硬掩模层302的突出部分。因此可增加制造成本和制造时间。额外的蚀刻操作和/或平坦化操作可损坏半导体器件的元件。
图4A至图4C是根据一些实施例的半导体器件的栅极堆叠件的截面图。如图4A所示，在半导体衬底100上方形成接触件404n和404p以分别电连接至外延鳍116n和116p。接触件404n和404p用作半导体器件的源极/漏极接触件。
在一些实施例中，在隔离结构106和外延鳍116n和116p上方形成介电层402。在一些实施例中，介电层402由氧化硅、氮氧化硅、硼硅酸盐玻璃(BSG)、磷硅酸玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、低k材料、多孔介电材料、其他合适的材料或它们的组合构成。在一些实施例中，使用CVD工艺、旋涂工艺、PVD工艺、其他合适的工艺或它们的组合沉积介电层402。之后，图案化介电层402以形成暴露出外延鳍116n和116p的开口。在一些实施例中，光刻工艺和蚀刻工艺用于图案化介电层402。在一些实施例中，在图案化介电层402之前进行平坦化工艺以提供具有基本平坦的表面的介电层402。平坦化工艺可包括CMP工艺。在一些实施例中，在介电层402之前沉积蚀刻停止层(未示出)。蚀刻停止层包括例如氮化硅、氮氧化硅或其他合适的材料。
在一些实施例中，在介电层402和外延鳍116n和116p上方沉积导电层。之后，图案化导电层以形成接触件404n和404p。在一些实施例中，导电层包括铜、钨、铝、镍、钛、铂、其他合适的导电材料、或它们的组合。在一些实施例中，使用PVD工艺、电镀工艺、CVD工艺、其他合适的工艺或它们的组合来沉积导电层。在一些实施例中，进行诸如CMP工艺的平坦化工艺以去除介电层402的开口以外的沉积的导电层。因此，形成被介电层402围绕的接触件404n和404p。
本发明的实施例具有诸多变型。在一些实施例中，形成接触件404n和404p之前，分别在外延鳍116n和116p上形成金属硅化物区(未示出)。因此，可进一步降低接触件和外延鳍之间的电阻。
如图4A所示，根据一些实施例，接触件404n填充凹槽122。在一些实施例中，接触件404n与n型外延鳍(外延鳍116n)的源极/漏极区电接触，而接触件404p与p型外延鳍(外延鳍116p)的源极/漏极区电接触。
本发明的实施例具有诸多变型。如图4B所示，根据一些实施例，接触件404p填充凹槽122。在其他一些实施例中，接触件404n和404p均未填充凹槽122。如图4C所示，介电层402填充凹槽122。
本发明提供了关于CMOSFinFET器件的结构和形成方法的实施例。图案化的掩模层用于辅助形成n型外延鳍和p型外延鳍。图案化的掩模层的图案部分重叠。因此，在多次蚀刻工艺之后，在CMOSFinFET器件的n型和p型外延鳍之间形成凹槽，并且在该CMOSFinFET器件的栅极堆叠件上方的硬掩模层上形成另一个凹槽。由于硬掩模层上的凹槽，随后去除硬掩模层的工艺变得更简单。因此，减少制造成本和时间。提高了器件性能。
根据一些实施例，提供了一种半导体器件。半导体器件包括半导体衬底和位于半导体沉底上方的隔离结构。半导体器件还包括位于半导体衬底上方的第一外延鳍和第二外延鳍，第一外延鳍和第二外延鳍从隔离结构中突出。半导体器件还包括位于第一外延鳍和第二外延鳍上方且横跨第一外延鳍和第二外延鳍的栅极堆叠件。此外，半导体器件包括从隔离结构的顶面开始延伸的凹槽。凹槽介于第一外延鳍和第二外延鳍之间。
根据一些实施例，提供了一种半导体器件。半导体器件包括半导体衬底和位于半导体衬底上方的隔离结构。半导体器件还包括位于半导体衬底上方的n型外延鳍和p型外延鳍。n型外延鳍和p型外延鳍从隔离结构中突出。半导体器件还包括位于n型外延鳍和p型外延鳍上方且横跨n型外延鳍和p型外延鳍的栅极堆叠件。此外，半导体器件包括从隔离结构的顶面处开始延伸的凹槽。凹槽介于n型外延鳍和p型外延鳍之间。
根据一些实施例，提供了一种形成半导体器件的方法。该方法包括在半导体衬底上方形成第一鳍和第二鳍。该方法还包括在半导体衬底上方形成隔离结构以围绕第一鳍和第二鳍的下部。该方法还包括在第一鳍和第二鳍上方形成栅极堆叠件，栅极堆叠件横跨第一鳍和第二鳍。此外，该方法包括分别在第一鳍和第二鳍上方顺序地形成第一外延鳍和第二外延鳍。形成第一外延鳍之后和形成第二外延鳍之前，在隔离结构中形成凹槽。凹槽介于第一外延鳍和第二外延鳍之间。
上面论述了若干实施例的部件，使得本领域的普通技术人员可以更好地理解本发明的各个方面。本领域的技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、更换以及改变。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；
隔离结构，位于所述半导体衬底上方；
第一外延鳍和第二外延鳍，位于所述半导体衬底上方，其中，所述第一外延鳍和所述第二外延鳍从所述隔离结构中突出；
栅极堆叠件，位于所述第一外延鳍和所述第二外延鳍上方且横跨所述第一外延鳍和所述第二外延鳍；以及
凹槽，从所述隔离结构的顶面处开始延伸，其中，所述凹槽介于所述第一外延鳍和所述第二外延鳍之间。
2.根据权利要求1所述的半导体器件，其中，所述栅极堆叠件包括金属材料。
3.根据权利要求1所述的半导体器件，其中，所述第一外延鳍和所述第二外延鳍的材料彼此不同。
4.根据权利要求1所述的半导体器件，其中，所述第二外延鳍包括磷化硅、碳化硅或它们的组合。
5.根据权利要求1所述的半导体器件，其中，所述第一外延鳍包括硅锗。
6.根据权利要求1所述的半导体器件，其中，所述凹槽的延伸方向与所述第一外延鳍和所述第二外延鳍的延伸方向基本平行。
7.一种半导体衬底，包括：
半导体衬底；
隔离结构，位于所述半导体衬底上方；
n型外延鳍和p型外延鳍，位于所述半导体衬底上方，其中，所述n型外延鳍和所述p型外延鳍从所述隔离结构中突出；
栅极堆叠件，位于所述n型外延鳍和所述p型外延鳍上方且横跨所述n型外延鳍和所述p型外延鳍；以及
凹槽，从所述隔离结构的顶面处开始延伸，其中，所述凹槽介于所述n型外延鳍和所述p型外延鳍之间。
8.根据权利要求7所述的半导体器件，其中，所述栅极堆叠件包括金属材料。
9.一种形成半导体器件的方法，包括：
在半导体衬底上方形成第一鳍和第二鳍；
在所述半导体衬底上方形成隔离结构以围绕所述第一鳍的下部和所述第二鳍的下部；
在所述第一鳍上方和所述第二鳍上方形成栅极堆叠件，其中，所述栅极堆叠件横跨所述第一鳍和所述第二鳍；以及
分别在所述第一鳍和所述第二鳍上方顺序地形成第一外延鳍和第二外延鳍，其中，在形成所述第一外延鳍之后和在形成所述第二外延鳍之前在所述隔离结构中形成凹槽，并且所述凹槽介于所述第一外延鳍和所述第二外延鳍之间。
10.根据权利要求9所述的形成半导体器件的方法，其中，顺序地形成所述第一外延鳍和所述第二外延鳍的所述步骤包括：
在所述第二鳍上方形成第一掩模层；
在形成所述第一掩模层之后在所述第一鳍上方形成所述第一外延鳍；
去除所述第一掩模层；
在所述第一外延鳍上方形成第二掩模层；
在形成所述第二掩模层之后在所述第二鳍上方形成所述第二外延鳍；以及
去除所述第二掩模层。
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