TWI687980B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI687980B
TWI687980B TW105108729A TW105108729A TWI687980B TW I687980 B TWI687980 B TW I687980B TW 105108729 A TW105108729 A TW 105108729A TW 105108729 A TW105108729 A TW 105108729A TW I687980 B TWI687980 B TW I687980B
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epitaxial layer
fin structure
bump
lower half
substrate
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TW201735126A (zh
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童宇誠
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聯華電子股份有限公司
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Priority to US15/134,367 priority patent/US9960163B2/en
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Abstract

本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一鰭狀結構以及一凸塊於基底上，其中第一鰭狀結構及凸塊包含不同材料。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於基底上形成具有不同材料之鰭狀結構與凸塊的方法。
近年來，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體 元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構的設計仍存在許多瓶頸，進而影響整個元件的漏電流及整體電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一鰭狀結構以及一凸塊於基底上，其中第一鰭狀結構及凸塊包含不同材料。
本發明另一實施例揭露一種半導體元件，其主要包含一基底以及一鰭狀結構與一凸塊設於基底上，其中鰭狀結構及凸塊包含不同材料。
12:基底
14:NMOS區域
16:PMOS區域
18:鰭狀結構
20:凸塊
22:絕緣層
24:凹槽
26:磊晶層
28:缺陷差排
30:鰭狀結構
32:淺溝隔離
34:上半部
36:下半部
46:閘極介電層
48:閘極結構
52:多晶矽材料
54:側壁子
56:層間介電層
58:高介電常數介電層
60:功函數金屬層
62:低阻抗金屬層
64:硬遮罩
72:基底
74:NMOS區域
76:PMOS區域
78:第一磊晶層
80:第二磊晶層
82:鰭狀結構
84:凸塊
86:上半部
88:下半部
90:淺溝隔離
92:鰭狀結構
94:凸塊
96:上半部
98:中半部
100:下半部
102:缺陷差排
104:缺陷差排
112:基底
114:NMOS區域
116:PMOS區域
118:凸塊
120:絕緣層
122:凹槽
124:第一磊晶層
126:第二磊晶層
128:缺陷差排
130:鰭狀結構
第1圖至第6圖為本發明第一實施例製作一半導體元件之方法示意圖。
第7圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖。
第10圖為本發明第三實施例之一半導體元件之結構示意圖。
第11圖至第12圖為本發明第四實施例製作一半導體元件之方法示意 圖。
第13圖為本發明第五實施例之一半導體元件之結構示意圖。
請參照第1圖至第6圖，第1圖至第6圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，然後於基底12上定義一第一區域與一第二區域，例如本實施例之第一區域較佳為一NMOS區域14而第二區域較佳為一PMOS區域16，但不侷限於此。接著分別形成至少一鰭狀結構18以及一凸塊20於NMOS區域14以及至少一鰭狀結構18與另一凸塊20於PMOS區域16，其中各鰭狀結構18上可選擇性設有一由氮化矽或氧化矽所構成的硬遮罩(圖未示)。
需注意的是，本實施例雖於NMOS區域14與PMOS區域16中各形成一凸塊20，但凸塊20的數量與所設置的位置又可依據製程需求任意調整，例如可於NMOS區域14與PMOS區域16中各形成複數個凸塊，或於NMOS區域14與PMOS區域16的交界處僅設置一個或一個以上的凸塊，這些均屬本發明所涵蓋的範圍。
鰭狀結構18之形成方式可以包含先形成一圖案化遮罩(圖未示)，例如前述之遮罩層於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成各鰭狀結構18。除此之外，鰭狀結構18之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12 上，並利用磊晶製程於圖案化硬遮罩層所暴露出之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構18。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底12的一底氧化層上之一半導體層，並且不蝕穿此半導體層以形成各鰭狀結構18。
凸塊20的形成方式可比照前述形成鰭狀結構18的方式先於基底12上形成複數個鰭狀結構，然後再利用鰭狀結構切割(fin-cut)製程或另一道微影暨蝕刻製程降低部分鰭狀結構18的高度，以於NMOS區域14形成凸塊20以及於PMOS區域16形成凸塊20。由於凸塊20是與鰭狀結構18一同形成，因此兩者較佳由相同材料所構成。
然後沉積一絕緣層22覆蓋NMOS區域14與PMOS區域16的鰭狀結構18與凸塊20並使絕緣層22高於各鰭狀結構18頂部，接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing,CMP)製程去除部分絕緣層22甚至部分鰭狀結構18，使剩餘的絕緣層22上表面與鰭狀結構18上表面齊平。在本實施例中，絕緣層22較佳由氧化矽所構成，但不侷限於此。
隨後如第2圖所示，利用絕緣層22為遮罩進行一蝕刻製程，去除NMOS區域14與PMOS區域16的部分鰭狀結構18以形成複數個凹槽24。在本實施例中，去除部分鰭狀結構18的蝕刻製程中所使用的蝕刻劑可選自由氨水(ammonium hydroxide,NH4OH)、氫氧化鉀(potassium hydroxide,KOH)、氫氟酸(hydrofluoric acid,HF)以及氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)所構成的群組。
如第3圖所示，然後進行一磊晶成長製程，以形成一磊晶層26於各鰭狀結構18上並填滿各凹槽24，且所成長的磊晶層26頂部較佳高於絕緣層22上表面。在本實施例中，磊晶成長製程較佳藉由化學氣相沉積製程達成，例如氣相磊晶(vapor phase epitaxy,VPE)製程、超高真空化學氣相沉積(ultra-high vacuum CVD)製程或分子束磊晶(molecular beam epitaxy)製程等。
需注意的是，本實施例於NMOS區域14以及PMOS區域16形成的磊晶層26雖為相同材料，但不侷限於此，依據本發明之一實施例，又可於NMOS區域14與PMOS區域16分別形成不同材料的磊晶層26來形成鰭狀結構30。例如，NMOS區域14所形成的磊晶層26與PMOS區域16所形成的磊晶層26可具有不同濃度(如鍺濃度)，NMOS區域14所形成的磊晶層26與PMOS區域16所形成的磊晶層26可具有不同應力，或NMOS區域14所形成的磊晶層26與PMOS區域16所形成的磊晶層26同時具有不同濃度與不同應力，這些均屬本發明所涵蓋的範圍。
另外值得注意的是，由於前述以磊晶成長方式形成磊晶層26時通常會伴隨形成缺陷差排28，因此在本實施例中，在磊晶層26成長完之後磊晶層26中靠近原本鰭狀結構18的位置處較佳包含至少一缺陷差排28。
如第4圖所示，接著進行一平坦化製程，例如以CMP方式去除部分突出於絕緣層22上的部分磊晶層26甚至部分絕緣層22，使磊晶 層26上表面切齊絕緣層22上表面。之後再進行一蝕刻製程，去除部分絕緣層22，使部分上半部34突出於絕緣層22，以形成複數個新的鰭狀結構30以及一淺溝隔離(shallow trench isolation,STI)32環繞各鰭狀結構30，其中各鰭狀結構30包含一上半部34與一下半部36，上半部34與下半部36包含不同材料但下半部36與凸塊20包含相同材料。
在本實施例中，各鰭狀結構30下半部36、凸塊20以及基底12較佳由相同材料所構成，例如皆由矽所構成而各鰭狀結構30上半部34則由磊晶材料所構成。但不侷限於此，依據本發明其他實施例，基底12、凸塊20與下半部36所包含的材料較佳不同於鰭狀結構30上半部34的材料，其中基底12、凸塊20與下半部36可由矽、鍺、碳化矽(SiC)、鍺化矽(SiGe)、砷化鎵(GaAs)、磷化銦(InP)、砷化銦鎵(InGaAs)以及III-V族半導體材料中之任何一者或任何組合所構成，而鰭狀結構30上半部34則可由鍺、矽、砷化鎵、鋁砷化鎵(AlGaAs)、鍺化矽以及砷化鎵磷(GaAsP)等中任何一者或任何組合所構成。
從另一角度來看，本實施例之基底12、凸塊20與鰭狀結構30下半部36的晶格常數(lattice constant)較佳不同於鰭狀結構30上半部34的晶格常數，其中所謂的晶格常數可泛指基底12、凸塊20、鰭狀結構30上半部34以及鰭狀結構30下半部36中的任何區域。在一實施例中，基底12、凸塊20與鰭狀結構30下半部36可由一第一材料所構成，其具有第一晶格常數，且第一材料可包含單一元素、一化合物或一混合物。鰭狀結構30下半部36可由一第二材料所構成或由第一材料與第二材料混合而成，其具有一第二晶格常數，且第二晶格常數不同於第一晶格 常數。
如第5圖所示，接著可依據製程需求進行後續電晶體製程以形成閘極結構，例如可先形成一介質層(圖未示)和/或閘極介電層46於NMOS區域14與PMOS區域16，然後分別形成一閘極結構48於NMOS區域14與PMOS區域16的鰭狀結構30上。其中閘極結構48較佳由多晶矽材料所構成，NMOS區域14的閘極結構48較佳覆蓋NMOS區域14的鰭狀結構30與凸塊20，PMOS區域16的閘極結構48也較佳覆蓋PMOS區域16的鰭狀結構30與凸塊20。
在本實施例中，閘極結構48的製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，如第5圖所示，可先於鰭狀結構30上形成前述包含閘極介電層46與多晶矽材料52所構成的閘極結構48，然後於閘極結構48側壁形成側壁子54。在本實施例中，側壁子54可為單一側壁子或複合式側壁子，其可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。隨後可形成源極/汲極區域於閘極結構48兩側的鰭狀結構30內，並依據製程需求形成磊晶層、矽化金屬層、接觸洞蝕刻停止層以及層間介電層56等元件。
如第6圖所示，然後再進行一金屬閘極置換(replacement metal gate,RMG)製程將多晶矽所構成的閘極結構48轉換為金屬閘 極。其中NMOS區域14與PMOS區域16的各金屬閘極或閘極結構48較佳包含一U型高介電常數介電層58、一U型功函數金屬層60以及一低阻抗金屬層62。
在本實施例中，高介電常數介電層58包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層60較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層60可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層60可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層60與低阻抗金屬層62之間可包含另一阻障層(圖未示)，其中 阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層62則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
之後可去除部分高介電常數介電層58、部分功函數金屬層60與部分低阻抗金屬層62形成凹槽(圖未示)，然後再填入一硬遮罩64於凹槽內並使硬遮罩64與層間介電層56表面齊平，其中硬遮罩64可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。至此即完成本發明第一實施例之一半導體元件的製作。
請參照第7圖至第9圖，第7圖至第9圖為本發明第二實施例製作一半導體元件之方法示意圖。如第7圖所示，首先提供一基底72，例如一矽基底或矽覆絕緣(SOI)基板，然後於基底72上定義一第一區域與一第二區域，例如本實施例之第一區域較佳為一NMOS區域74而第二區域較佳為一PMOS區域76，但不侷限於此。
接著依序形成一第一磊晶層78與一第二磊晶層80與基底上。如同前述實施例，在磊晶層成長完之後第一磊晶層78中靠近基底72的位置處較佳包含至少一缺陷差排104。另外在本實施例中，第一磊晶層78與第二磊晶層80較佳包含不同材料及/或不同晶格常數，且第一磊晶層78與第二磊晶層80可包含鍺、矽、砷化鎵、鋁砷化鎵(AlGaAs)、鍺化矽以及砷化鎵磷(GaAsP)等中任何一者或任何組合。
需注意的是，本實施例於NMOS區域74與PMOS區域76形成的第一磊晶層78與第二磊晶層80雖為相同材料，但不侷限於此，依據本發明之一實施例，又可於NMOS區域74與PMOS區域76分別形成不同材料的第一磊晶層78與第二磊晶層80來形成鰭狀結構82。例如，NMOS區域74的第一磊晶層78與PMOS區域76的第一磊晶層78可包含不同材料，NMOS區域74的第二磊晶層80與PMOS區域76的第二磊晶層80可包含不同材料，或NMOS區域74的第一磊晶層78與第二磊晶層80同時與PMOS區域76的第一磊晶層78與第二磊晶層80為不同材料。其中所謂的不同材料包括兩者可具有不同濃度(如鍺濃度)或不同應力，這些均屬本發明所涵蓋的範圍。
然後如第8圖所示，進行一圖案轉移製程，例如可先形成一圖案化光阻(圖未示)於第二磊晶層80上，並以圖案化光阻為遮罩進行一蝕刻製程，去除部分第二磊晶層80與部分第一磊晶層78，以於基底72上形成複數個鰭狀結構82。隨後再進行鰭狀結構切割製程或另一道微影暨蝕刻製程去除部分第二磊晶層80與部分第一磊晶層78，以於NMOS區域74與PMOS區域76上分別形成凸塊84。在此階段，各鰭狀結構82較佳包含一上半部86與一下半部88，其中上半部86與下半部88包含不同材料但下半部88與凸塊84較佳包含相同材料。如同前述實施例，在磊晶層成長完之後第一磊晶層78中靠近基底72的位置處，或鰭狀結構82下半部88靠近基底72處較佳包含至少一缺陷差排104。
如第9圖所示，接著形成一淺溝隔離90於凸塊84上並環繞鰭 狀結構82。在本實施例中，形成淺溝隔離90的方法可先沉積一絕緣層(圖未示)覆蓋NMOS區域74與PMOS區域76的鰭狀結構82與凸塊84並使絕緣層高於各鰭狀結構82頂部，然後進行一平坦化製程，例如利用化學機械研磨製程去除部分絕緣層甚至部分鰭狀結構82，使剩餘的絕緣層上表面與鰭狀結構82上表面齊平。在本實施例中，絕緣層較佳由氧化矽所構成，但不侷限於此。之後進行一蝕刻製程，去除部分絕緣層並使剩餘的絕緣層上表面高於凸塊84與第一磊晶層78或下半部88上表面但低於第二磊晶層80或上半部86上表面，以形成淺溝隔離90。
隨後可比照第一實施例分別於NMOS區域74與PMOS區域76上形成閘極結構，然後再進行金屬閘極置換製程將多晶矽所構成的閘極結構轉換為金屬閘極。如同第一實施例，各電晶體區的金屬閘極較佳重疊或覆蓋該電晶體區的鰭狀結構與凸塊，例如NMOS區域74中的金屬閘極較佳覆蓋NMOS區域74的鰭狀結構82與凸塊84，而PMOS區域76中的金屬閘極則覆蓋PMOS區域76的鰭狀結構82與凸塊84。
請繼續參照第10圖，第10圖為本發明第三實施例之一半導體元件之結構示意圖。如第10圖所示，本實施例可於第7圖形成第一磊晶層78與第二磊晶層80後以微影暨蝕刻製程去除部分第二磊晶層80、部分第一磊晶層78以及部分基底72以形成複數個鰭狀結構92。然後再利用鰭狀結構切割製程或另一道微影暨蝕刻製程去除部分第二磊晶層80與部分第一磊晶層78，以於NMOS區域74與PMOS區域76上分別形成凸塊94。在此實施例中，各鰭狀結構92包含一上半部96、一中半部98以及一下半部100，其中上半部96、中半部98及下半部100較佳包含不同 材料及/或不同晶格常數，且下半部100與凸塊94包含相同材料或相同晶格常數。
更具體而言，本實施例之鰭狀結構92上半部96與中半部98較佳包含磊晶材料，例如中半部98包含第一磊晶層78，上半部96包含第二磊晶層80，下半部100與凸塊94則由矽所構成。從位置來看，各凸塊94上表面較佳切齊各鰭狀結構92下半部100上表面，但又可選擇略低於各鰭狀結構92下半部100上表面。
此外，本實施例又包含一淺溝隔離90較佳設於凸塊94上並環繞鰭狀結構92，其中淺溝隔離90上表面較佳高於中半部98上表面，但並不侷限於此，例如又可選擇將淺溝隔離90上表面略為降低使其上表面略低於中半部98上表面但仍完全覆蓋凸塊94。另外由於前述以磊晶成長方式形成磊晶層時通常會伴隨形成缺陷差排，因此在本實施例中，鰭狀結構92內可包含至少一缺陷差排102，其中缺陷差排102較佳設於鰭狀結構92中半部98靠近下半部100的地方。
請參照第11圖至第12圖，第11圖至第12圖為本發明第四實施例製作一半導體元件之方法示意圖。如第11圖所示，首先提供一基底112，例如一矽基底或矽覆絕緣(SOI)基板，然後於基底112上定義一第一區域與一第二區域，例如本實施例之第一區域較佳為一NMOS區域114而第二區域較佳為一PMOS區域116，但不侷限於此。
接著分別形成至少一凸塊118於NMOS區域114以及另一凸 塊118於PMOS區域116。需注意的是，本實施例雖於NMOS區域114與PMOS區域116中各形成一凸塊118，但凸塊118的數量與所設置的位置又可依據製程需求任意調整，例如可於NMOS區域114與PMOS區域116中各形成複數個凸塊，或於NMOS區域114與PMOS區域116的交界處僅設置一個或一個以上的凸塊，這些均屬本發明所涵蓋的範圍。
凸塊118的形成方式可比照前述形成鰭狀結構的方式先於基底112上形成複數個鰭狀結構，然後再利用鰭狀結構切割(fin-cut)製程或另一道微影暨蝕刻製程降低部分鰭狀結構的高度，以於NMOS區域114形成凸塊118以及於PMOS區域116形成凸塊118。
然後沉積一絕緣層120於基底112上並覆蓋NMOS區域114與PMOS區域116的凸塊118，接著進行一微影暨蝕刻製程去除部分絕緣層120與部分基底112，以於NMOS區域114與PMOS區域116中分別形成複數個凹槽122，其中各凹槽122底部較佳低於基底112上表面。在本實施例中，絕緣層120較佳由氧化矽所構成，但不侷限於此。
如第12圖所示，隨後依序形成一第一磊晶層124與第二磊晶層126於各凹槽122內並填滿凹槽122來構成複數個鰭狀結構130。在本實施例中，第一磊晶層124與第二磊晶層126較佳包含不同材料及/或不同晶格常數，且第一磊晶層124與第二磊晶層126可包含鍺、矽、砷化鎵、鋁砷化鎵(AlGaAs)、鍺化矽以及砷化鎵磷(GaAsP)等中任何一者或任何組合。
如同前述實施例，本實施例於NMOS區域114與PMOS區域116形成的第一磊晶層124與第二磊晶層126雖為相同材料，但不侷限於此，依據本發明之一實施例，又可於NMOS區域114與PMOS區域116分別形成不同材料的第一磊晶層124與第二磊晶層126來形成鰭狀結構130。例如，NMOS區域114的第一磊晶層124與PMOS區域116的第一磊晶層124可包含不同材料，NMOS區域114的第二磊晶層126與PMOS區域116的第二磊晶層126可包含不同材料，或NMOS區域114的第一磊晶層124與第二磊晶層126同時與PMOS區域116的第一磊晶層124與第二磊晶層126為不同材料。其中所謂的不同材料包括兩者可具有不同濃度(如鍺濃度)或不同應力，這些均屬本發明所涵蓋的範圍。
另外需注意的是，由於以磊晶成長方式形成第一磊晶層124時通常會伴隨形成缺陷差排128，因此在本實施例中，在第一磊晶層124成長完之後第一磊晶層124中靠近原本基底112的位置處較佳包含至少一缺陷差排128。在本實施例中，第一磊晶層124上表面較佳高於凸塊118的上表面，而缺陷差排128則較佳低於基底112上表面。
請繼續參照第13圖，第13圖為本發明第五實施例之一半導體元件之結構示意圖。如第13圖所示，本實施例同樣包含複數個鰭狀結構130分別設於NMOS區域114與PMOS區域116，其中各鰭狀結構130包含一第一磊晶層124與第二磊晶層126。相較於第12圖之實施例，本實施例之凸塊118上表面較佳高於第一磊晶層124上表面。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之 均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
14:NMOS區域
16:PMOS區域
20:凸塊
28:缺陷差排
30:鰭狀結構
32:淺溝隔離
34:上半部
36:下半部
46:閘極介電層
48:閘極結構
54:側壁子
56:層間介電層
58:高介電常數介電層
60:功函數金屬層
62:低阻抗金屬層
64:硬遮罩

Claims (12)

  1. 一種製作半導體元件的方法，包含：提供一基底；以及形成一第二鰭狀結構以及一凸塊於該基底上；形成一絕緣層於該凸塊上並環繞該第二鰭狀結構；去除部分該第二鰭狀結構；形成一磊晶層於該第二鰭狀結構上；平坦化該磊晶層；以及去除部分該絕緣層以形成一淺溝隔離以及一第一鰭狀結構突出於該淺溝隔離。
  2. 如申請專利範圍第1項所述之方法，另包含形成一缺陷差排於該磊晶層之一下半部。
  3. 如申請專利範圍第1項所述之方法，其中該第一鰭狀結構包含一上半部以及一下半部，該上半部及該下半部包含不同材料，且該下半部及該凸塊包含相同材料。
  4. 如申請專利範圍第3項所述之方法，其中該上半部包含該磊晶層，該下半部及該凸塊與該基底包含相同材料。
  5. 如申請專利範圍第3項所述之方法，其中該凸塊之上表面低於該下半部之上表面。
  6. 一種半導體元件，包含：一基底；以及一鰭狀結構以及一凸塊設於該基底上，其中該鰭狀結構包含一上半部以及一下半部，該下半部及該凸塊包含一第一磊晶層且該上半部包含一第二磊晶層。
  7. 如申請專利範圍第6項所述之半導體元件，其中該第一磊晶層和該第二磊晶層包含不同材料。
  8. 如申請專利範圍第6項所述之半導體元件，其中該第一磊晶層和該第二磊晶層包含不同晶格常數。
  9. 如申請專利範圍第6項所述之半導體元件，其中該凸塊之上表面低於該下半部之上表面。
  10. 如申請專利範圍第6項所述之半導體元件，另包含一淺溝隔離設於該凸塊上並環繞該鰭狀結構，其中該淺溝隔離之上表面高於該下半部之上表面。
  11. 如申請專利範圍第6項所述之半導體元件，其中該凸塊之上表面切齊該下半部之上表面。
  12. 如申請專利範圍第6項所述之半導體元件，另包含一缺陷差排設於該下半部。
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