TW201830578A - 接觸結構製造方法 - Google Patents

接觸結構製造方法 Download PDF

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TW201830578A
TW201830578A TW106117847A TW106117847A TW201830578A TW 201830578 A TW201830578 A TW 201830578A TW 106117847 A TW106117847 A TW 106117847A TW 106117847 A TW106117847 A TW 106117847A TW 201830578 A TW201830578 A TW 201830578A
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Taiwan
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gate
layer
dielectric layer
opening
transistor
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TW106117847A
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English (en)
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TWI745375B (zh
Inventor
徐宛萱
王怡琇
陳彥兆
張展瑋
汪于仕
呂信諺
邱意為
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台灣積體電路製造股份有限公司
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures

Abstract

一種接觸結構的製造方法，包括形成第一電晶體及第二電晶體於基板上，其中第一電晶體及第二電晶體共享源極/汲極區，源極/汲極區形成於第一電晶體之第一閘極及第二電晶體之第二閘極之間，形成第一開口於層間介電層中，且於第一閘極及第二閘極間，沉積蝕刻停止層於第一開口中，且於層間介電層之頂表面上，沉積介電層於蝕刻停止層上，對介電層施行第一蝕刻製程，直到露出蝕刻停止層，對蝕刻停止層進行第二蝕刻製程，直到移除蝕刻停止層的露出部份及介電層的部份。

Description

接觸結構製造方法
本發明實施例係關於接觸結構及其製造方法，且特別有關於一種具有擴大汲極接觸的接觸結構及其製造方法。
半導體工業因電子元件(例如電晶體、二極體、電阻及電容等等)集成密度之持續改進已經歷快速成長。此集成密度之改進大部份是來自不斷地降低最小特徵尺寸而來，而可允許更多元件被集成於給定區域。然而，越小的特徵尺寸可能會造成不期望的接觸電阻增加。隨著對微小化、更高的速度、更大的頻寬、更低的功耗和延遲等的需求，減少接觸電阻的需求日益增加。
根據一實施例，一種接觸結構的製造方法，包括：形成第一電晶體及第二電晶體於基板上，其中第一電晶體及第二電晶體共享源極/汲極區，源極/汲極區形成於第一電晶體之第一閘極及第二電晶體之第二閘極之間；形成第一開口於層間介電層中，且於第一閘極及第二閘極間；沉積蝕刻停止層於第一開口中，且於層間介電層之頂表面上；沉積介電層於蝕刻停止層上；沉積光阻層於介電層上；圖案化光阻層以於光阻層中 形成第二開口，其中第二開口之最外緣與第一開口之最外緣對準；對介電層施行第一蝕刻製程，直到露出蝕刻停止層；對蝕刻停止層進行第二蝕刻製程，直到移除蝕刻停止層的露出部份及介電層的部份以形成第三開口，其中第三開口的最大寬度大於第二開口的最大寬度；以及以導電材料填充第三開口。
根據一實施例，一種接觸結構的製造方法，包括：形成第一電晶體及第二電晶體於基板上，其中：第一電晶體包括第一源極、第一閘極及汲極；以及第二電晶體包括第二源極、第二閘極及汲極。方法更包括形成第一保護層及第二保護層，分別沿著第一電晶體及第二電晶體之側壁間隔物，其中第一保護層及第二保護層於第一閘極及第二閘極間且於汲極上；形成下汲極接觸於層間介電層中及於第一閘極及第二閘極間；形成第一開口於層間介電層中及於下汲極接觸上；沉積蝕刻停止層於第一開口中及於層間介電層之頂表面上；沉積介電層於蝕刻停止層上；對介電層施行第一蝕刻製程直到露出蝕刻停止層；對蝕刻停止層進行第二蝕刻製程直到移除蝕刻停止層之露出部份及部份介電層以形成第二開口，其中第二開口上部之寬度大於第一開口上部之寬度；以及以導電材料填充第二開口。
根據一實施例，一種接觸結構設備，包括：第一源極及共同汲極，於第一閘極的相反側上；第二源極及共同汲極，於第二閘極的相反側上，其中：第一閘極及第二閘極位於基板上之層間介電層中；以及第一閘極及第二閘極分別被第一閘極間隔物及第二閘極間隔物圍繞。設備更包括第一保護層， 沿著第一閘極間隔物之側壁形成，其中第一保護層位於共同汲極上，且第一保護層之頂表面有第一斜坡；第二保護層，沿著第二閘極間隔物之側壁形成，其中第二保護層位於共同汲極上，且第二保護層之頂表面有第二斜坡；以及第一汲極接觸，形成於第一閘極及第二閘極間，其中第一汲極接觸上部之寬度大於第一汲極接觸下部之寬度。
100‧‧‧半導體裝置
101‧‧‧第一電晶體
102‧‧‧第二電晶體
104‧‧‧基板
106‧‧‧第一隔離區域
108‧‧‧第二隔離區域
112‧‧‧第一源極
114‧‧‧汲極
116‧‧‧第二源極
120‧‧‧層間介電層
121‧‧‧第一閘極介電層
122‧‧‧第二閘極介電層
123‧‧‧第一閘極
124‧‧‧第二閘極
125‧‧‧第一閘極間隔物
126‧‧‧第二閘極間隔物
127‧‧‧第一保護層
128、130‧‧‧汲極接觸
129‧‧‧第二保護層
202、602、702‧‧‧開口
302‧‧‧蝕刻停止層
402‧‧‧介電層
502‧‧‧光阻層
1102、1104、1106、1108、1110、1112、1114、1116、1118、1120‧‧‧步驟
1200‧‧‧FinFET裝置
W1、W2‧‧‧寬度
以下將配合所附圖式詳述本發明之實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地擴大或縮小元件的尺寸，以清楚地表現出本發明的特徵。
第1圖係根據本發明的各種實施例繪示之半導體裝置的剖面圖；第2圖至第10圖係根據本發明的各種實施例繪示製造第1圖所示的半導體裝置的中間步驟；第11圖係根據本發明的各種實施例繪示形成第1圖中所示的半導體裝置方法的流程圖；以及第12圖係根據本發明的各種實施例繪示具有擴大的汲極/源極接觸的FinFET半導體裝置的剖面圖。
以下公開許多不同的實施方法或是例子來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明。當然這些實施例僅用以例示，且不該以此限定本發明的範圍。例如，在說明書中提到第一特徵形成於第二 特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關用詞，例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。
下文將以具有擴大的頂部關鍵尺寸的汲極接觸結構及其形成方法的實施例描述本發明。然而也可應用本發明實施例於各種半導體結構。舉例來說，此製程可適用於形成源極接觸結構。此外，本發明實施例不僅適用於平面型電晶體裝置，且適用於鰭式場效電晶體(fin field effect transistor，FinFET)裝置。在下文中將參照附圖進行說明各種實施例。
第1圖係根據本發明的各種實施例繪示之半導體裝置的剖面圖。半導體裝置100包括共用一個共同汲極的兩個電晶體，於基板104上並至少部份地於第一隔離區域106和第二隔離區域108之間形成這兩個電晶體。第一電晶體101包括第一 閘極123和其閘極介電層121、汲極114和其接觸128和130、以及第一源極112和其接觸(未示出)。第二電晶體102包括第二閘極124和閘極介電層122、汲極114和其接觸128和130、以及第二源極116和其接觸(未示出)。
應當注意，在第1圖中所示的共同汲極僅用於示意，而非限制本發明的各種實施例。本領域通常技術人士可理解各種變化、替換和修改。舉例來說，半導體裝置100可包括共用一個共同源極的兩個電晶體。
如第1圖所示，第一閘極間隔物125緊鄰於第一閘極123形成。如第1圖之剖面圖所示，第一閘極間隔物125包括兩部份。第一部份形成於第一閘極123一側。第二部份形成於第一閘極123的相反側。第一閘極間隔物125的第一部份分隔第一源極112和第一閘極123。第一閘極間隔物125的第二部份分隔汲極114和第一閘極123。
於緊鄰第二閘極124處形成第二閘極間隔物126。相似地，第二閘極間隔物126分隔第二源極116和第二閘極124。
於層間介電層120中形成閘極123和124。於層間介電層120上形成蝕刻停止層302。於蝕刻停止層302上形成介電層402。於第一閘極123和第二閘極124之間形成汲極接觸128和130。
於層間介電層120中且於第一閘極123和第二閘極124之間嵌入汲極接觸128。汲極接觸128的底表面與汲極114接觸。應當注意的是，可在汲極114和汲極接觸128之間形成矽化物區域(未示出)以改善汲極114的接觸電阻。在整個說明書 中，汲極接觸128可稱為下汲極接觸128。
在一些實施例中，下汲極接觸128是倒梯形，如第1圖所示。在第1圖所示的下汲極接觸128的形狀僅為範例，本領域技術人士將理解該中下方汲極接觸128可包括其它形狀，例如但不限於矩形、正方形和梯形等。
如第1圖所示，在汲極接觸128上堆疊汲極接觸130。在整個說明書中，汲極接觸130可稱為上汲極接觸130。上汲極接觸130的下部是倒梯形，且位於第一閘極123和第二閘極124之間。汲極接觸130的上部是矩形，並且延伸穿過介電層402和蝕刻停止層302。
如第1圖所示，上汲極接觸130底部的寬度大約等於下汲極接觸128頂部的寬度。上汲極接觸130的中間部份相鄰於第一閘極間隔物125和第二閘極間隔物126。為了保護閘極間隔物的側壁以及閘極123和124，於汲極接觸和第一閘極隔離物125之間形成第一保護層127。於汲極接觸和第二閘極間隔物126之間形成第二保護層129。
應當注意的是，雖然第1圖繪示出在半導體裝置100的剖面上為分隔的兩個保護層127和129，本領域通常技術人士將理解可具有各種變化、替換和修改。例如，在一些實施例中，保護層127和129可為一連續保護層的部份。
如第1圖中所示，第一保護層127的頂表面具有自第一閘極隔離物125頂表面邊緣向下延伸的斜坡。相似地，第二保護層129的頂表面具有自第二閘極間隔物126頂表面邊緣向下延伸的斜坡。保護層127和129的斜坡幫助增加形成上汲極 接觸130處的溝槽的尺寸，從而改善汲極接觸的金屬間隙填充。如第1圖所示，溝槽的寬度自W2增加到W1。W2是第一保護層127與第二保護層129之間的最小距離。W1是上汲極接觸130上部的寬度。在一些實施例中，W1與W2之比值為約1.1至約1.3間。
具有第1圖所示的擴大的溝槽的一個有利特徵是擴大的溝槽有助於減小接觸電阻，從而提高了半導體裝置100的性能。例如，可通過第1圖所示之擴大的汲極接觸130改善半導體裝置100的電阻-電容(RC)延遲。隨後將參照第2圖至第10圖描述形成上汲極接觸130和127和129保護層的詳細過程。
第2圖至第10圖係根據本發明的各種實施例繪示製造第1圖所示的半導體裝置的中間步驟。應當注意，在第1圖中所示的製造步驟以及半導體結構僅為範例。本領域技術人士將可理解可具有各種變化、替換和修改。
第2圖係根據本發明各種實施例繪示於半導體裝置上形成下汲極接觸後的半導體裝置剖面圖。於基板104上形成半導體裝置100。具體來說，於基板104中和隔離區域106和108間形成汲極114、源極112和116。在層間介電層120中形成閘極電極123和124。於閘極123和124之間形成下汲極接觸128。
可由矽形成基板104，儘管它也可能由其他III族、IV族和/或V族元素形成，如矽、鍺、鎵、砷或其組合等。基板104也可為絕緣體上矽(silicon-on-insulator，SOI)。SOI基板可包括一層形成於絕緣層(如埋氧等)之上的半導體材料(如矽、鍺等)，其形成於矽基板中。此外，也可使用其它基板如 多層基板(multi-layered substrates)、梯度基板(gradient substrates)、混合晶向基板(hybrid orientation substrates)和/或類似基板。
基板104可進一步包括各種電路，例如電晶體(如電晶體101和電晶體102)。為了簡化起見，僅呈現兩個共享汲極的電晶體以說明各種實施例的創新面向。
形成於基板104上的電路可為任何適合特定應用的電路。根據一個實施例中，電路可包括各種n型金氧半(NMOS)和/或p型金氧半(PMOS)裝置，如電晶體、電容、電阻、二極體、發光二極體、保險絲等。可互連電路以執行至少一個功能。功能可包括記憶體結構、處理結構、感測器、擴大器、功率分配、輸入/輸出電路等。
根據一個實施例，基板104可為p型基板，其摻雜p型摻質如硼、銦等。根據設計需求和不同的應用，可從p型基板104生長p型磊晶層(未示出)。可於p型磊晶層中形成源極112、116和汲極114。可通過使用合適的半導體製程磊晶生長p型磊晶層，例如化學氣相沉積(chemical vapor deposition，CVD)、超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition，UHV-CVD)等。
如第2圖所示，在第一閘極123的相反側形成第一源極112和汲極114。在第二閘極124的相反側形成第二源極116和汲極114。於基板104為n型基板的一實施例中，可通過佈植合適的p型摻質，如硼、鎵、銦和/或類似物形成源極和汲極區域。此外，在基板104是p型基板的一實施例中，可通過注入適 當的n型摻質如磷、砷和/或類似摻質來形成源極和汲極區域。
隔離區域106和108可為淺溝槽隔離(shallow trench isolation，STI)區，可由蝕刻基板104形成複數溝槽，並用本領域中已知的介電材料填充該些溝槽以形成隔離區域106和108。舉例來說，隔離區域106和108可填入介電材料如氧化物材料、高密度電漿(high-density plasma，HDP)氧化物和/或類似物。可於頂部表面上施加如化學機械拋光(chemical mechanical polish，CMP)製程的平坦化製程，使得過量的介電材料可被移除。
可由介電材料形成閘極介電層121和122，如氧化矽、氮氧化矽、氮化矽、氧化物、含氮氧化物、其組合和/或類似物。閘極介電層121和122具有大於約4的相對介電常數。其他這種材料的例子包括氧化鋁、氧化鑭、氧化鉿、氧化鋯、氮氧化鉿和/或其組合等。於一閘極介電層121和122包括氧化物層的實施例中，可由使用四乙氧基矽烷(tetraethoxysilane，TEOS)和氧作為前驅物的電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)製程形成閘極介電層121和122。根據一個實施例，閘極介電層121和122的厚度範圍可為約8Å至約200Å。
閘極123和124可包括導電材料，如金屬(如鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕)、金屬矽化物(如矽化鈦、矽化鈷、鎳、矽化鉭)、金屬氮化物(如氮化鈦、氮化鉭)、摻雜的多晶矽、其它導電材料、其組合和/或類似物。在一個其中由多晶矽形成閘極123和124的實施例中，可藉由低壓化學氣 相沉積(low-pressure chemical vapor deposition，LPCVD)來沉積摻雜或未摻雜的多晶矽，進而形成閘極電極123和124。在整個說明書中，閘極123和124也可分別稱為第一閘極123及第二閘極124。
可藉由於閘極123、124和基板104上毯覆沉積至少一層間隔層(未示出)及蝕刻間隔層以形成閘極間隔物125和126。閘極間隔物125和126可包括適當的介電材料例如氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物和/或類似物。可由常用的技術如CVD、PECVD、濺鍍和/或類似的技術來形成閘極間隔物125和126。
沿著第一閘極隔離物125的側壁和第二閘極間隔物126的側壁分別形成第一保護層127和第二保護層129。在一些實施例中，第一保護層127與第二保護層129可作為接觸蝕刻停止層(contact etch stop layers，CESL)。CESL層可包含常用的介電材料如氮化矽、氮氧化矽、碳氧化矽、碳化矽、其組合及其多層。在一些實施例中，除了停止蝕刻製程，CESL層也可施加應力於各個電晶體的通道區。
在一些實施例中，第一保護層127與第二保護層129是連續保護層的一部份。藉由原子層沉積(atomic layer deposition，ALD)製程沉積介電層和蝕刻該介電層，以形成如第2圖所示之連續保護層。在對半導體裝置100進行ALD製程之前，對半導體裝置100施加預熱處理製程。預熱處理製程使ALD製程的溫度增加到更高的溫度。在一些實施例中，於對半導體裝置100施加預熱製程後，ALD製程的溫度介於約550℃至 約600℃。
如第2圖所示，在基板104上形成層間介電層120。可由如低介電常數(low-k)介電材料，如氧化矽，形成層間介電層120。可通過本領域中已知的任何合適的方法來形成層間介電層120，例如旋轉塗佈、CVD、PECVD等。此外，本領域技術人士將認知雖然第2圖僅繪示單層層間介電層，但層間介電層120可包括複數介電層。
在一些實施例中，層間介電層120可包括下部和上部。由兩個獨立的製造步驟來形成層間介電層120的下部和上部。形成下部後，於層間介電層120的下部中及於第一閘極123和第二閘極124之間形成下汲極接觸128。下汲極接觸128用於提供汲極114和形成在層間介電層120上的互連結構(未示出)之間的電性連接。
可利用微影技術在層間介電層120光阻的下部沉積和圖案化光阻材料，以形成下汲極接觸128。根據下汲極接觸128的位置和形狀，露出一部分的光阻。可使用蝕刻製程，如各向異性乾蝕刻製程(anisotropic dry etch process)，於層間介電層120的下部中製造開口。可於填充接觸開口前沉積導電襯層(未示出)。在一些實施例中，導電襯層是保形的，並且可包括單層Ta、TaN、WN、WSi、TiN、Ru和其組合。導電襯層可作為阻障層，以防止導電材料如銅擴散到其下的基板104中。可使用合適的沉積製程，例如CVD、PVD、ALD和/或類似製程沉積導電襯層。
隨後在開口中填入導電材料。可使用適合的沉積 製程如CVD、PVD、ALD等沉積導電材料。於導電襯層上沉積導電材料以填充接觸開口。導電材料可為銅、鎢、鋁、銀、鈦、氮化鈦、鉭和其組合和/或類似物。
應當注意，可在汲極和源極區的頂表面上形成複數矽化物區。可藉由自我對準矽化物製程(salicide process)在相應的源極/汲極區上形成矽化物區。如本領域中所已知的，在用於形成矽化物區的自我對準矽化物製程中，藉由在裝置上先沉積薄金屬層如鈷、鎳、鈦等以形成金屬層。裝置隨後被退火，以於所沉積的金屬以及其下露出的矽區之間形成矽化物區。
第2圖進一步繪示在層間介電層120的上部形成開口202。可藉由應用和顯影合適的光阻層(未示出)，並除去部份層間介電層120上部，直到露出下汲極接觸128的頂表面以形成開口202。
應當注意的是，可藉由後閘極半導體製程(gate-last semiconductor fabrication process)形成第2圖中所示的閘極123和124。更具體來說，於基板104上沉積介電層(如氧化矽)和虛置閘極層(如多晶矽)。藉由蝕刻介電層和虛置閘極層形成兩個閘極堆疊結構。沉積和蝕刻介電材料(如氮化矽)以形成閘極間隔物125和126。然後在基板104上沉積層間介電層(如介電層120)。通過合適的蝕刻製程去除虛置閘極層和介電層以形成兩個閘極溝槽。如第2圖所示，於閘極溝槽填充高介電常數介電材料以形成閘極介電層121和122，以及填充閘極材料以形成閘極123和124。
第3圖係根據本發明各種實施例繪示於第2圖中所示的半導體裝置上形成蝕刻停止層302之後的剖面圖。可於開口202中以及層間介電層120的頂表面上沉積蝕刻停止層302。可由氮氧化鋁(AlON)、氧化鋁(Al2O3)、氮化鋁(AlN)、氧化鉿(HfOx)、氧化鋯(ZrOx)以及其組合和/或類似物形成蝕刻停止層302。
可使用合適的製造技術，如CVD，形成蝕刻停止層302，雖然也可使用任何可接受的製程形成有約10Å至約30Å厚度的蝕刻停止層302。根據一個實施例，蝕刻停止層302的厚度約等於12Å。
在一些實施例中，蝕刻停止層302的材料包括不同於覆蓋蝕刻停止層302的材料。材料的不同使得蝕刻停止層302的蝕刻速率慢於覆蓋它的材料。蝕刻停止層302提供何時結束蝕刻製程的明確指示，從而保護蝕刻停止層302下方的材料。
第4圖係根據本發明的各種實施例繪示於第3圖中所示的半導體裝置於蝕刻停止層302上形成介電層402之後的剖面圖。在蝕刻停止層302上形成介電層402。可由介電材料，例如氧化物或氮化矽形成介電層402，儘管也可使用其它合適的介電材料，如高介電常數介電材料。可使用PECVD製程形成介電層402，雖然也可使用任何其他合適的製程。
第5圖係根據本發明的各種實施例繪示於第4圖中所示的半導體裝置於介電層402上方形成罩幕層502後的剖面圖。在介電層402上沉積罩幕層502。在一些實施例中，可由光阻材料形成罩幕層502。在整個說明書中，罩幕層502也可稱為 光阻層502。
可通過合適的技術，例如旋轉塗佈等形成光阻層502。光阻材料可為SU-8(殼牌化學的註冊商標)光敏環氧(photo-sensitive epoxy)、膜狀的高分子材料和/或類似物。應當注意的是，本領域技術人士將認知雖然第5圖僅繪示一層光阻層，光阻層502可包括複數光阻層。
第6圖係根據本發明的各種實施例繪示於第5圖中所示的半導體裝置於罩幕層502中形成開口602後的剖面圖。考慮在第1圖所示的上汲極接觸件130的位置和尺寸後，曝光光阻層502的選擇區域。塗敷顯影劑於光阻層502，從而於光阻層502中形成開口602。
在一些實施例中，開口602的最外緣大抵對準在第2圖中繪示的開口202的最外緣。開口602的寬度定義為W3，如第6圖中所示。
於圖案化光阻層502後，介電層402的頂部有可能形成兩個光阻材料區域，如第6圖所示。剩餘的光阻區域有助於防止光阻層502下方的介電層402被下述於第7圖中的蝕刻製程蝕刻掉。
第7圖係根據本發明的各種實施例繪示於第6圖中所示的半導體裝置於進行蝕刻製程後的剖面圖。於半導體裝置100進行如乾蝕刻的蝕刻製程。根據第6圖中所示的圖案，結果是介電層402的暴露部份被去除。藉由蝕刻停止層302的幫助，更精確地控制介電層402的蝕刻。如第7圖所示，蝕刻製程造成在下汲極接觸128之上的開口702。
具有蝕刻停止層302的一個有利特徵是蝕刻停止層302的高選擇性有助於避免過蝕刻(over-etch)問題，從而保護下汲極接觸128的頂表面於施加蝕刻製程於介電層402時不被損壞。
第8圖係根據本發明的各種實施例，繪示於第7圖中所示的半導體裝置從半導體裝置移除剩餘光阻層後的剖面圖。可由合適的光阻剝離技術如化學溶劑清洗(chemical solvent cleaming)、電漿灰化(plasma etching)、乾剝離(dry stripping)和/或類似方法除去在第7圖所示的剩餘的光阻層。光阻剝離技術是眾所周知的，因此於本文不詳細討論其細節以避免重複。
第9圖係根據本發明的各種實施例繪示於第8圖中所示的半導體裝置於對蝕刻停止層302進行蝕刻製程後的剖面圖。可由使用合適的蝕刻製程如濕蝕刻、乾蝕刻和/或類似製程除去露出的蝕刻停止層302(第8圖中所示)。
在一些實施例中，由濕蝕刻製程去除露出的蝕刻停止層302，其中施加清洗液於蝕刻停止層302。在一些實施例中，清洗液是基於氫氟酸(HF)的清洗溶液、基於氨水(NH4OH)的清洗液、基於羥胺(hydroxylamine)的清洗液、它們的任意組合及類似物。
可於施加清洗液至蝕刻停止層302的製程前加熱半導體裝置100。在一實施例中，加熱半導體裝置100至約40℃。除去露出的蝕刻停止層302的時間為約30秒。在一替代實施例中，加熱半導體裝置100至約60℃。除去露出的蝕刻停止 層302的時間為約10秒。
為了具有擴大的開口，蝕刻製程被控制以去除部份保護層127、129和介電層402。具體而言，於蝕刻製程完成後，如虛線A-A'所示，介電層402的第一邊緣902係垂直對準第一閘極隔離物125的最外緣。類似地，如虛線B-B'所示，介電層402的第二邊緣904係垂直對準第二閘極隔離物126的最外緣。在一替代性實施例中，介電層402的第一邊緣902係大抵上對準第一閘極間隔物125。介電層402的第二邊緣904係大抵上對準第二閘極間隔物126。
此外，第一保護層127的頂表面有自第一閘極隔離物125的頂表面的邊緣向下延伸的第一斜坡，第二保護層129的頂表面有自第二閘極隔離物126的頂表面的邊緣向下延伸的第二斜坡。如在第9圖中所示，第一保護層127頂表面的變化速率大抵上等於第二保護層129的頂表面的變化速率。
應當注意的是，保護層127和129由高溫沉積製程形成。如上及第2圖所描述，由ALD製程以及用來將ALD製程的溫度增加至約550℃至約600℃的預熱處理形成保護層127和129。反之，介電層402由製程溫度大約500℃的CVD製程形成。當施加濕蝕刻製程到保護層和介電層402上時，不同的沉積製程造成蝕刻速率不同。該蝕刻速率差異有助於在保護層和介電層402形成不同的表面。
在完成蝕刻製程後，於下汲極接觸128上形成開口901。開口901包括兩個部份。開口901的第一部份是矩形。第一部份位於介電層402中。開口901的第二部份是倒梯形。如第 9圖所示，開口901的第二部份位於層間介電層120中。定義開口901的第一部份的寬度為W4。在整個描述中，可稱W4為開口901的最大寬度。
如第9圖中所示，於蝕刻製程期間移除部份介電層402。介電層402的側壁分別對準閘極間隔物125和126的側壁。如此一來，如第9圖所示，W4大於W3。在一些實施例中，W4與W3的比值介於約1.1至約1.3之間。
第10圖係根據本發明的各種實施例繪示於第9圖中所示的半導體裝置於填入金屬材料於半導體裝置的開口後的剖面圖。填入包括鎢、鈦、鋁、銅、其組合和/或類似物的金屬材料於開口901中(如第9圖中所示)。因此，於下汲極接觸128上形成上汲極接觸130。
如第10圖所示，上汲極接觸130包括上部和下部。上汲極接觸130的上部是矩形。上汲極接觸130的下部是倒梯形。此外，上汲極接觸130的下部與第一保護層127的第一斜坡和第二保護層129的第二斜坡接觸。上汲極接觸130上部的第一邊緣係垂直對準第一閘極間隔物125的最外緣。上汲極接觸130上部的第二邊緣係垂直對準第二閘極間隔物126的最外緣。
第11圖係根據本發明的各種實施例繪示形成第1圖中所示的半導體裝置方法的流程圖。該流程圖僅為範例，其不應不適當地限制權利要求的範圍。本領域的通常技術人士將認知可具有許多變化、替換和修改。例如，第11圖中所示的各種步驟可被添加、移除、替換、重排和重複。
於步驟1102，提供一種包括具有共同汲極的兩個 電晶體的半導體裝置。下汲極接觸已經形成於兩個電晶體的兩個閘極之間的層間介電層中。於層間介電層中及下汲極接觸上形成開口。
於步驟1104，在開口中和層間介電層的頂表面上沉積蝕刻停止層。蝕刻停止層由氮氧化鋁(AlON)、氧化鋁(Al2O3)、氮化鋁(AlN)、氧化鉿(HfOx)、氧化鋯(ZrOx)和/或其組合等形成。
於步驟1106，於蝕刻停止層上形成介電層。由氮化矽形成介電層。介電層位於開口中和層間介電層上。
於步驟1108，於介電層上沉積光阻層。於步驟1110，根據預定的圖案曝光光阻層。於步驟1112中，藉由施加顯影劑於光阻層，於光阻層中形成開口。
於步驟1114，進行蝕刻製程於介電層直至露出蝕刻停止層。於步驟1116中，由合適的光阻去除製程去除剩餘的光阻層。
於步驟1118，由合適的蝕刻製程去除露出的蝕刻停止層。在去除蝕刻停止層的過程中，去除保護層的上部和部份介電層。具體而言，控制蝕刻製程使得介電層的第一邊緣係垂直對準第一電晶體的側壁間隔物；介電層的第二邊緣係垂直對準第二電晶體的側壁間隔物；第一保護層的頂表面有自第一電晶體的第一閘極間隔物的頂表面的邊緣向下延伸的斜坡；第二保護層的頂表面有自第二電晶體的第二閘極間隔物的頂表面的邊緣向下延伸的斜坡。
於步驟1120，藉由電鍍製程填充導電材料於開口 中以形成上汲極接觸。上汲極接觸位於下汲極接觸之上且與之接觸。
第12圖係根據本發明的各種實施例繪示具有擴大的汲極/源極接觸的FinFET半導體裝置的剖面圖。在第2圖至第11圖所示的汲極接觸製程不僅應用於平面電晶體裝置，而且還應用於FinFET裝置。FinFET裝置1200包括共用一個共同汲極的兩個電晶體。這兩個電晶體形成於基板104上。第一電晶體101包括第一閘極123和其閘極介電層121，汲極114及其接觸128和130，以及第一源極112和其接觸(未繪示)。第二電晶體102包括第二閘極124和其閘極介電層122，汲極114及其接觸128和130，以及第二源極116和其接觸(未繪示)。
可藉由蝕刻部份鰭線，並藉由合適的磊晶生長製程生長源極/汲極區112、114和116以形成源極/汲極區112、114和116。如第12圖中所示，源極/汲極區112、114和116的頂表面高於閘極123和124的底表面。
第12圖中的上汲極接觸130的形狀類似於第1圖中所示，於此不再詳細討論以避免不必要的重複。如第12圖所示之具有擴大的汲極接觸130的一個有利特徵是擴大的汲極接觸有助於降低接觸電阻，從而改善FinFET半導體裝置1200的性能。
根據一實施例，一種接觸結構的製造方法，包括：形成一第一電晶體及一第二電晶體於一基板上，其中該第一電晶體及該第二電晶體共享一源極/汲極區，該源極/汲極區形成於該第一電晶體之一第一閘極及該第二電晶體之一第二閘極 之間；形成一開口於一層間介電層中，且於該第一閘極及該第二閘極間；沉積一蝕刻停止層於該第一開口中，且於該層間介電層之一頂表面上；沉積一介電層於該蝕刻停止層上；沉積一光阻層於該介電層上；圖案化該光阻層以於該光阻層中形成一第二開口，其中該第二開口之一最外緣與該第一開口之一最外緣對準；對該介電層施行一第一蝕刻製程，直到露出該蝕刻停止層；對該蝕刻停止層進行一第二蝕刻製程，直到移除該蝕刻停止層的一露出部份及該介電層的複數部份以形成一第三開口，其中該第三開口的一最大寬度大於該第二開口的一最大寬度；以及以一導電材料填充該第三開口。
根據一實施例，一種接觸結構的製造方法，包括：形成一第一電晶體及一第二電晶體於一基板上，其中：該第一電晶體包括一第一源極、一第一閘極及一汲極；以及該第二電晶體包括一第二源極、一第二閘極及該汲極。
該方法更包括形成一第一保護層及一第二保護層，分別沿著該第一電晶體及該第二電晶體之複數側壁間隔物，其中該第一保護層及該第二保護層於該第一閘極及該第二閘極間且於該汲極上；形成一下汲極接觸於一層間介電層中及於該第一閘極及該第二閘極間；形成一第一開口於該層間介電層中及於該下汲極接觸上；沉積一蝕刻停止層於該第一開口中及於該層間介電層之一頂表面上；沉積一介電層於該蝕刻停止層上；對該介電層施行一第一蝕刻製程直到露出該蝕刻停止層；對該蝕刻停止層進行一第二蝕刻製程直到移除該蝕刻停止層之一露出部份及部份該介電層以形成一第二開口，其中該第 二開口一上部之寬度大於該第一開口一上部之寬度；以及以一導電材料填充該第二開口。
根據一實施例，一種接觸結構設備，包括：一第一源極及一共同汲極，於一第一閘極的相反側上；一第二源極及該共同汲極，於一第二閘極的相反側上，其中：該第一閘極及該第二閘極位於一基板上之一層間介電層中；以及該第一閘極及該第二閘極分別被一第一閘極間隔物及一第二閘極間隔物圍繞。
該設備更包括一第一保護層，沿著該第一閘極間隔物之一側壁形成，其中該第一保護層位於該共同汲極上，且該第一保護層之一頂表面有一第一斜坡；一第二保護層，沿著該第二閘極間隔物之一側壁形成，其中該第二保護層位於該共同汲極上，且該第二保護層之一頂表面有一第二斜坡；以及一第一汲極接觸，形成於該第一閘極及該第二閘極間，其中該第一汲極接觸一上部之寬度大於該第一汲極接觸一下部之寬度。如本發明一些實施例所述之接觸結構的製造方法，更包括：於在該層間介電層中形成該第一開口的步驟前，形成一下汲極接觸於該層間介電層中，及該第一閘極和該第二閘極之間。
如本發明一實施例所述之接觸結構的製造方法，更包括：於在該層間介電層中形成該第一開口的步驟前，形成一下汲極接觸於該層間介電層中，及該第一閘極和該第二閘極之間。
如本發明一實施例所述之接觸結構的製造方法， 更包括：以該導電材料填充該第三開口以一上汲極接觸，其中該上汲極接觸之一底表面與該下汲極接觸之一頂表面接觸。
如本發明一實施例所述之接觸結構的製造方法，更包括：於形成該第一開口於該層間介電層中的步驟之前，沿著該第一電晶體之一側壁間隔物形成一第一保護層；以及沿著該第二電晶體之一側壁間隔物形成一第二保護層。
如本發明一實施例所述之接觸結構的製造方法，其中：於在該蝕刻停止層上進行該第二蝕刻製程之步驟後，該第一保護層之一第一邊緣係垂直對準於該第一電晶體之該側壁間隔物之一最外緣；以及該介電層之一第二邊緣係垂直對準於該第二電晶體之該側壁間隔物之一最外緣。
如本發明一實施例所述之接觸結構的製造方法，其中：於在該蝕刻停止層上進行該第二蝕刻製程之步驟後，該第一保護層之一頂表面有一第一斜坡，自該第一電晶體之該側壁間隔物之一頂表面之一邊緣向下延伸；以及該第二保護層之一頂表面有一第二斜坡，自該第二電晶體之該側壁間隔物之一頂表面之一邊緣向下延伸。
如本發明一實施例所述之接觸結構的製造方法，其中：該蝕刻停止層由氮氧化鋁形成。
如本發明一實施例所述之接觸結構的製造方法，其中：該介電層由氮化矽形成。
如本發明一實施例所述之接觸結構的製造方法，更包括：以該導電材料填充該第三開口以形成一上汲極接觸，該上汲極接觸包括倒梯形之一第一部份及矩形之一第二部份。
如本發明一實施例所述之接觸結構的製造方法，其中：該上汲極接觸之該第一部份位於該層間介電層中且於該第一閘極及該第二閘極間；以及該上汲極接觸之該第二部份位於該介電層中。
如本發明另一實施例所述之接觸結構的製造方法，更包括：於對該介電層進行該第一蝕刻製程之步驟前，沉積一光阻層於該介電層上；以及圖案化該光阻層以於該光阻層中形成一第三開口，其中該第三開口之一最外緣大抵與該第一開口之一最外緣對準。
如本發明另一實施例所述之接觸結構的製造方法，更包括：於進行該第二蝕刻製程於該蝕刻停止層之步驟後，移除該介電層之該部份以使得：該介電層之一第一邊緣與該第一電晶體之該側壁間隔物之一最外緣對準；以及該介電層之一第二邊緣與該第二電晶體之該側壁間隔物之一最外緣對準。
如本發明另一實施例所述之接觸結構的製造方法，更包括：於進行該第二蝕刻製程於該蝕刻停止層之步驟後，移除部份該第一保護層及該第二保護層以使得：該第一保護層之一頂表面有一第一斜坡，自該第一電晶體之該側壁間隔物之一頂表面之一邊緣向下延伸；以及該第二保護層之一頂表面有一第二斜坡，自該第二電晶體之該側壁間隔物之一頂表面之一邊緣向下延伸。
如本發明另一實施例所述之接觸結構的製造方法，更包括：以一導電材料填充該第二開口以形成一上汲極接 觸，其中：該第一保護層於該上汲極接觸及該第一閘極間；該第二保護層於該上汲極接觸及該第二閘極間；以及該上汲極接觸之一上部的寬度大於該上汲極接觸之一下部的寬度。
如本發明又一實施例所述之接觸結構設備，更包括：一第二汲極接觸，形成於該共同汲極及該第一汲極接觸間，其中該第二汲極接觸有一倒梯形。
如本發明又一實施例所述之接觸結構設備，其中：該第一保護層之該頂表面之一改變速率與該第二保護層之該頂表面之一改變速率大抵相同。
如本發明又一實施例所述之接觸結構設備，其中：該第一汲極接觸之該上部有一矩形；以及該第一汲極接觸之該下部有一倒梯形，且其中：該第一汲極接觸之該下部與該第一斜坡及該第二斜坡接觸；該第一汲極接觸之該上部之一第一邊緣與該第一閘極間隔物之一最外緣垂直對準；以及該第二汲極接觸之該上部之一第二邊緣與該第二閘極間隔物之一最外緣垂直對準。
如本發明又一實施例所述之接觸結構設備，其中：該第一汲極接觸之該上部之寬度與該第一保護層及該第二保護層間的最小寬度之比值介於大約1.1至大約1.3之間。
上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明為基礎，設計或修改其他製程及結構，以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通 常知識者也應了解，在不脫離本發明之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明的精神及範圍。

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  1. 一種接觸結構的製造方法，包括：形成一第一電晶體及一第二電晶體於一基板上，其中該第一電晶體及該第二電晶體共享一源極/汲極區，該源極/汲極區形成於該第一電晶體之一第一閘極及該第二電晶體之一第二閘極之間；形成一第一開口於一層間介電層中，且於該第一閘極及該第二閘極間；沉積一蝕刻停止層於該第一開口中，且於該層間介電層之一頂表面上；沉積一介電層於該蝕刻停止層上；沉積一光阻層於該介電層上；圖案化該光阻層以於該光阻層中形成一第二開口，其中該第二開口之一最外緣與該第一開口之一最外緣對準；對該介電層施行一第一蝕刻製程，直到露出該蝕刻停止層；對該蝕刻停止層進行一第二蝕刻製程，直到移除該蝕刻停止層的一露出部份及該介電層的複數部份以形成一第三開口，其中該第三開口的一最大寬度大於該第二開口的一最大寬度；以及以一導電材料填充該第三開口。
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US10770356B2 (en) 2020-09-08
TWI745375B (zh) 2021-11-11
US20180308761A1 (en) 2018-10-25
CN108122845A (zh) 2018-06-05
US10037918B2 (en) 2018-07-31
US20200402859A1 (en) 2020-12-24
US20180151560A1 (en) 2018-05-31
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