CN108122845A - 接触结构制造方法 - Google Patents

接触结构制造方法 Download PDF

Info

Publication number
CN108122845A
CN108122845A CN201710402860.1A CN201710402860A CN108122845A CN 108122845 A CN108122845 A CN 108122845A CN 201710402860 A CN201710402860 A CN 201710402860A CN 108122845 A CN108122845 A CN 108122845A
Authority
CN
China
Prior art keywords
layer
grid
dielectric layer
transistor
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710402860.1A
Other languages
English (en)
Other versions
CN108122845B (zh
Inventor
徐宛萱
王怡琇
陈彦兆
张展玮
汪于仕
吕信谚
邱意为
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108122845A publication Critical patent/CN108122845A/zh
Application granted granted Critical
Publication of CN108122845B publication Critical patent/CN108122845B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种接触结构的制造方法，包括形成第一晶体管及第二晶体管于基板上，其中第一晶体管及第二晶体管共享源极/漏极区，源极/漏极区形成于第一晶体管的第一栅极及第二晶体管的第二栅极之间，形成第一开口于层间介电层中，且于第一栅极及第二栅极间，沉积蚀刻停止层于第一开口中，且于层间介电层的顶表面上，沉积介电层于蚀刻停止层上，对介电层施行第一蚀刻工艺，直到露出蚀刻停止层，对蚀刻停止层进行第二蚀刻工艺，直到移除蚀刻停止层的露出部份及介电层的部份。

Description

接触结构制造方法
技术领域
本发明实施例涉及接触结构及其制造方法，且特别涉及一种具有扩大漏极接触的接触结构及其制造方法。
背景技术
半导体工业因电子元件(例如晶体管、二极管、电阻及电容等等)集成密度的持续改进已经历快速成长。此集成密度的改进大部份是来自不断地降低最小特征尺寸而来，而可允许更多元件被集成于给定区域。然而，越小的特征尺寸可能会造成不期望的接触电阻增加。随着对微小化、更高的速度、更大的频宽、更低的功耗和延迟等的需求，减少接触电阻的需求日益增加。
发明内容
根据一实施例，一种接触结构的制造方法，包括：形成第一晶体管及第二晶体管于基板上，其中第一晶体管及第二晶体管共享源极/漏极区，源极/漏极区形成于第一晶体管的第一栅极及第二晶体管的第二栅极之间；形成第一开口于层间介电层中，且于第一栅极及第二栅极间；沉积蚀刻停止层于第一开口中，且于层间介电层的顶表面上；沉积介电层于蚀刻停止层上；沉积光致抗蚀剂层于介电层上；图案化光致抗蚀剂层以于光致抗蚀剂层中形成第二开口，其中第二开口的最外缘与第一开口的最外缘对准；对介电层施行第一蚀刻工艺，直到露出蚀刻停止层；对蚀刻停止层进行第二蚀刻工艺，直到移除蚀刻停止层的露出部份及介电层的部份以形成第三开口，其中第三开口的最大宽度大于第二开口的最大宽度；以及以导电材料填充第三开口。
根据一实施例，一种接触结构的制造方法，包括：形成第一晶体管及第二晶体管于基板上，其中：第一晶体管包括第一源极、第一栅极及漏极；以及第二晶体管包括第二源极、第二栅极及漏极。方法还包括形成第一保护层及第二保护层，分别沿着第一晶体管及第二晶体管的侧壁间隔物，其中第一保护层及第二保护层于第一栅极及第二栅极间且于漏极上；形成下漏极接触于层间介电层中及于第一栅极及第二栅极间；形成第一开口于层间介电层中及于下漏极接触上；沉积蚀刻停止层于第一开口中及于层间介电层的顶表面上；沉积介电层于蚀刻停止层上；对介电层施行第一蚀刻工艺直到露出蚀刻停止层；对蚀刻停止层进行第二蚀刻工艺直到移除蚀刻停止层的露出部份及部份介电层以形成第二开口，其中第二开口上部的宽度大于第一开口上部的宽度；以及以导电材料填充第二开口。
根据一实施例，一种接触结构设备，包括：第一源极及共同漏极，于第一栅极的相反侧上；第二源极及共同漏极，于第二栅极的相反侧上，其中：第一栅极及第二栅极位于基板上的层间介电层中；以及第一栅极及第二栅极分别被第一栅极间隔物及第二栅极间隔物围绕。设备还包括第一保护层，沿着第一栅极间隔物的侧壁形成，其中第一保护层位于共同漏极上，且第一保护层的顶表面有第一斜坡；第二保护层，沿着第二栅极间隔物的侧壁形成，其中第二保护层位于共同漏极上，且第二保护层的顶表面有第二斜坡；以及第一漏极接触，形成于第一栅极及第二栅极间，其中第一漏极接触上部的宽度大于第一漏极接触下部的宽度。
附图说明
以下将配合所附附图详述本发明的实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘示且仅用以说明例示。事实上，可能任意地扩大或缩小元件的尺寸，以清楚地表现出本发明的特征。
图1为根据本发明的各种实施例绘示的半导体装置的剖面图；
图2至图10为根据本发明的各种实施例绘示的制造图1所示的半导体装置的中间步骤；
图11为根据本发明的各种实施例绘示形成图1中所示的半导体装置方法的流程图；以及
图12为根据本发明的各种实施例绘示具有扩大的漏极/源极接触的FinFET半导体装置的剖面图。
其中，附图标记说明如下：
100～半导体装置
101～第一晶体管
102～第二晶体管
104～基板
106～第一隔离区域
108～第二隔离区域
112～第一源极
114～漏极
116～第二源极
120～层间介电层
121～第一栅极介电层
122～第二栅极介电层
123～第一栅极
124～第二栅极
125～第一栅极间隔物
126～第二栅极间隔物
127～第一保护层
128、130～漏极接触
129～第二保护层
202、602、702～开口
302～蚀刻停止层
402～介电层
502～光致抗蚀剂层
1102、1104、1106、1108、1110、1112、1114、1116、1118、1120～步骤
1200～FinFET装置
具体实施方式
以下公开许多不同的实施方法或是例子来实行所提供的标的的不同特征，以下描述具体的元件及其排列的实施例以阐述本发明。当然这些实施例仅用以例示，且不该以此限定本发明的范围。例如，在说明书中提到第一特征形成于第二特征之上，其包括第一特征与第二特征是直接接触的实施例，另外也包括于第一特征与第二特征之间另外有其他特征的实施例，即，第一特征与第二特征并非直接接触。此外，在不同实施例中可能使用重复的标号或标示，这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间有特定的关系。
此外，其中可能用到与空间相关用词，例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，这些空间相关用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系，这些空间相关用词包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相关形容词也将依转向后的方位来解释。
下文将以具有扩大的顶部关键尺寸的漏极接触结构及其形成方法的实施例描述本发明。然而也可应用本发明实施例于各种半导体结构。举例来说，此工艺可适用于形成源极接触结构。此外，本发明实施例不仅适用于平面型晶体管装置，且适用于鳍式场效晶体管(fin field effect transistor，FinFET)装置。在下文中将参照附图进行说明各种实施例。
图1为根据本发明的各种实施例绘示的半导体装置的剖面图。半导体装置100包括共用一个共同漏极的两个晶体管，于基板104上并至少部份地于第一隔离区域106和第二隔离区域108之间形成这两个晶体管。第一晶体管101包括第一栅极123和其栅极介电层121、漏极114和其接触128和130、以及第一源极112和其接触(未示出)。第二晶体管102包括第二栅极124和栅极介电层122、漏极114和其接触128和130、以及第二源极116和其接触(未示出)。
应当注意，在图1中所示的共同漏极仅用于示意，而非限制本发明的各种实施例。本领域通常技术人士可理解各种变化、替换和修改。举例来说，半导体装置100可包括共用一个共同源极的两个晶体管。
如图1所示，第一栅极间隔物125紧邻于第一栅极123形成。如图1的剖面图所示，第一栅极间隔物125包括两部份。第一部份形成于第一栅极123一侧。第二部份形成于第一栅极123的相反侧。第一栅极间隔物125的第一部份分隔第一源极112和第一栅极123。第一栅极间隔物125的第二部份分隔漏极114和第一栅极123。
于紧邻第二栅极124处形成第二栅极间隔物126。相似地，第二栅极间隔物126分隔第二源极116和第二栅极124。
于层间介电层120中形成栅极123和124。于层间介电层120上形成蚀刻停止层302。于蚀刻停止层302上形成介电层402。于第一栅极123和第二栅极124之间形成漏极接触128和130。
于层间介电层120中且于第一栅极123和第二栅极124之间嵌入漏极接触128。漏极接触128的底表面与漏极114接触。应当注意的是，可在漏极114和漏极接触128之间形成硅化物区域(未示出)以改善漏极114的接触电阻。在整个说明书中，漏极接触128可称为下漏极接触128。
在一些实施例中，下漏极接触128是倒梯形，如图1所示。在图1所示的下漏极接触128的形状仅为范例，本领域技术人士将理解该中下方漏极接触128可包括其它形状，例如但不限于矩形、正方形和梯形等。
如图1所示，在漏极接触128上堆迭漏极接触130。在整个说明书中，漏极接触130可称为上漏极接触130。上漏极接触130的下部是倒梯形，且位于第一栅极123和第二栅极124之间。漏极接触130的上部是矩形，并且延伸穿过介电层402和蚀刻停止层302。
如图1所示，上漏极接触130底部的宽度大约等于下漏极接触128顶部的宽度。上漏极接触130的中间部份相邻于第一栅极间隔物125和第二栅极间隔物126。为了保护栅极间隔物的侧壁以及栅极123和124，于漏极接触和第一栅极隔离物125之间形成第一保护层127。于漏极接触和第二栅极间隔物126之间形成第二保护层129。
应当注意的是，虽然图1绘示出在半导体装置100的剖面上为分隔的两个保护层127和129，本领域通常技术人士将理解可具有各种变化、替换和修改。例如，在一些实施例中，保护层127和129可为一连续保护层的部份。
如图1中所示，第一保护层127的顶表面具有自第一栅极隔离物125顶表面边缘向下延伸的斜坡。相似地，第二保护层129的顶表面具有自第二栅极间隔物126顶表面边缘向下延伸的斜坡。保护层127和129的斜坡帮助增加形成上漏极接触130处的沟槽的尺寸，从而改善漏极接触的金属间隙填充。如图1所示，沟槽的宽度自W2增加到W1。W2是第一保护层127与第二保护层129之间的最小距离。W1是上漏极接触130上部的宽度。在一些实施例中，W1与W2的比值为约1.1至约1.3之间。
具有图1所示的扩大的沟槽的一个有利特征是扩大的沟槽有助于减小接触电阻，从而提高了半导体装置100的性能。例如，可通过图1所示的扩大的漏极接触130改善半导体装置100的电阻-电容(RC)延迟。随后将参照图2至图10描述形成上漏极接触130和127和129保护层的详细过程。
图2至图10为根据本发明的各种实施例绘示制造图1所示的半导体装置的中间步骤。应当注意，在图1中所示的制造步骤以及半导体结构仅为范例。本领域技术人士将可理解可具有各种变化、替换和修改。
图2为根据本发明各种实施例绘示于半导体装置上形成下漏极接触后的半导体装置剖面图。于基板104上形成半导体装置100。具体来说，于基板104中和隔离区域106和108间形成漏极114、源极112和116。在层间介电层120中形成栅极电极123和124。于栅极123和124之间形成下漏极接触128。
可由硅形成基板104，尽管它也可能由其他III族、IV族和/或V族元素形成，如硅、锗、镓、砷或其组合等。基板104也可为绝缘体上硅(silicon-on-insulator，SOI)。SOI基板可包括一层形成于绝缘层(如埋氧等)之上的半导体材料(如硅、锗等)，其形成于硅基板中。此外，也可使用其它基板如多层基板(multi-layered substrates)、梯度基板(gradientsubstrates)、混合晶向基板(hybrid orientation substrates)和/或类似基板。
基板104可进一步包括各种电路，例如晶体管(如晶体管101和晶体管102)。为了简化起见，仅呈现两个共享漏极的晶体管以说明各种实施例的创新面向。
形成于基板104上的电路可为任何适合特定应用的电路。根据一个实施例中，电路可包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)装置，如晶体管、电容、电阻、二极管、发光二极管、保险丝等。可互连电路以执行至少一个功能。功能可包括记忆体结构、处理结构、感测器、扩大器、功率分配、输入/输出电路等。
根据一个实施例，基板104可为p型基板，其掺杂p型掺质如硼、铟等。根据设计需求和不同的应用，可从p型基板104生长p型磊晶层(未示出)。可于p型磊晶层中形成源极112、116和漏极114。可通过使用合适的半导体工艺磊晶生长p型磊晶层，例如化学气相沉积(chemical vapor deposition，CVD)、超高真空化学气相沉积(ultra-high vacuumchemical vapor deposition，UHV-CVD)等。
如图2所示，在第一栅极123的相反侧形成第一源极112和漏极114。在第二栅极124的相反侧形成第二源极116和漏极114。于基板104为n型基板的一实施例中，可通过布植合适的p型掺质，如硼、镓、铟和/或类似物形成源极和漏极区域。此外，在基板104是p型基板的一实施例中，可通过注入适当的n型掺质如磷、砷和/或类似掺质来形成源极和漏极区域。
隔离区域106和108可为浅沟槽隔离(shallow trench isolation，STI)区，可由蚀刻基板104形成多沟槽，并用本领域中已知的介电材料填充该些沟槽以形成隔离区域106和108。举例来说，隔离区域106和108可填入介电材料如氧化物材料、高密度等离子体(high-density plasma，HDP)氧化物和/或类似物。可于顶部表面上施加如化学机械抛光(chemical mechanical polish，CMP)工艺的平坦化工艺，使得过量的介电材料可被移除。
可由介电材料形成栅极介电层121和122，如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、其组合和/或类似物。栅极介电层121和122具有大于约4的相对介电常数。其他这种材料的例子包括氧化铝、氧化镧、氧化铪、氧化锆、氮氧化铪和/或其组合等。于一栅极介电层121和122包括氧化物层的实施例中，可由使用四乙氧基硅烷(tetraethoxysilane，TEOS)和氧作为前驱物的等离子体辅助化学气相沉积(plasma enhanced chemical vapordeposition，PECVD)工艺形成栅极介电层121和122。根据一个实施例，栅极介电层121和122的厚度范围可为约至约
栅极123和124可包括导电材料，如金属(如钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(如硅化钛、硅化钴、镍、硅化钽)、金属氮化物(如氮化钛、氮化钽)、掺杂的多晶硅、其它导电材料、其组合和/或类似物。在一个其中由多晶硅形成栅极123和124的实施例中，可借由低压化学气相沉积(low-pressure chemical vapor deposition，LPCVD)来沉积掺杂或未掺杂的多晶硅，进而形成栅极电极123和124。在整个说明书中，栅极123和124也可分别称为第一栅极123及第二栅极124。
可借由于栅极123、124和基板104上毯覆沉积至少一层间隔层(未示出)及蚀刻间隔层以形成栅极间隔物125和126。栅极间隔物125和126可包括适当的介电材料例如氮化硅、氮氧化物、碳化硅、氮氧化硅、氧化物和/或类似物。可由常用的技术如CVD、PECVD、溅镀和/或类似的技术来形成栅极间隔物125和126。
沿着第一栅极隔离物125的侧壁和第二栅极间隔物126的侧壁分别形成第一保护层127和第二保护层129。在一些实施例中，第一保护层127与第二保护层129可作为接触蚀刻停止层(contact etch stop layers，CESL)。CESL层可包含常用的介电材料如氮化硅、氮氧化硅、碳氧化硅、碳化硅、其组合及其多层。在一些实施例中，除了停止蚀刻工艺，CESL层也可施加应力于各个晶体管的通道区。
在一些实施例中，第一保护层127与第二保护层129是连续保护层的一部份。借由原子层沉积(atomic layer deposition，ALD)工艺沉积介电层和蚀刻该介电层，以形成如图2所示的连续保护层。在对半导体装置100进行ALD工艺之前，对半导体装置100施加预热处理工艺。预热处理工艺使ALD工艺的温度增加到更高的温度。在一些实施例中，于对半导体装置100施加预热工艺后，ALD工艺的温度介于约550℃至约600℃。
如图2所示，在基板104上形成层间介电层120。可由如低介电常数(low-k)介电材料，如氧化硅，形成层间介电层120。可通过本领域中已知的任何合适的方法来形成层间介电层120，例如旋转涂布、CVD、PECVD等。此外，本领域技术人士将认知虽然图2仅绘示单层层间介电层，但层间介电层120可包括多介电层。
在一些实施例中，层间介电层120可包括下部和上部。由两个独立的制造步骤来形成层间介电层120的下部和上部。形成下部后，于层间介电层120的下部中及于第一栅极123和第二栅极124之间形成下漏极接触128。下漏极接触128用于提供漏极114和形成在层间介电层120上的互连结构(未示出)之间的电性连接。
可利用光刻技术在层间介电层120光致抗蚀剂的下部沉积和图案化光致抗蚀剂材料，以形成下漏极接触128。根据下漏极接触128的位置和形状，露出一部分的光致抗蚀剂。可使用蚀刻工艺，如各向异性干蚀刻工艺(anisotropic dry etch process)，于层间介电层120的下部中制造开口。可于填充接触开口前沉积导电衬层(未示出)。在一些实施例中，导电衬层是保形的，并且可包括单层Ta、TaN、WN、WSi、TiN、Ru和其组合。导电衬层可作为阻障层，以防止导电材料如铜扩散到其下的基板104中。可使用合适的沉积工艺，例如CVD、PVD、ALD和/或类似工艺沉积导电衬层。
随后在开口中填入导电材料。可使用适合的沉积工艺如CVD、PVD、ALD等沉积导电材料。于导电衬层上沉积导电材料以填充接触开口。导电材料可为铜、钨、铝、银、钛、氮化钛、钽和其组合和/或类似物。
应当注意，可在漏极和源极区的顶表面上形成多硅化物区。可借由自我对准硅化物工艺(salicide process)在相应的源极/漏极区上形成硅化物区。如本领域中所已知的，在用于形成硅化物区的自我对准硅化物工艺中，借由在装置上先沉积薄金属层如钴、镍、钛等以形成金属层。装置随后被退火，以于所沉积的金属以及其下露出的硅区之间形成硅化物区。
图2进一步绘示在层间介电层120的上部形成开口202。可借由应用和显影合适的光致抗蚀剂层(未示出)，并除去部份层间介电层120上部，直到露出下漏极接触128的顶表面以形成开口202。
应当注意的是，可借由后栅极半导体工艺(gate-last semiconductorfabrication process)形成图2中所示的栅极123和124。更具体来说，于基板104上沉积介电层(如氧化硅)和虚置栅极层(如多晶硅)。借由蚀刻介电层和虚置栅极层形成两个栅极堆迭结构。沉积和蚀刻介电材料(如氮化硅)以形成栅极间隔物125和126。然后在基板104上沉积层间介电层(如介电层120)。通过合适的蚀刻工艺去除虚置栅极层和介电层以形成两个栅极沟槽。如图2所示，于栅极沟槽填充高介电常数介电材料以形成栅极介电层121和122，以及填充栅极材料以形成栅极123和124。
图3为根据本发明各种实施例绘示于图2中所示的半导体装置上形成蚀刻停止层302的后的剖面图。可于开口202中以及层间介电层120的顶表面上沉积蚀刻停止层302。可由氮氧化铝(AlON)、氧化铝(Al2O3)、氮化铝(AlN)、氧化铪(HfOx)、氧化锆(ZrOx)以及其组合和/或类似物形成蚀刻停止层302。
可使用合适的制造技术，如CVD，形成蚀刻停止层302，虽然也可使用任何可接受的工艺形成有约至约厚度的蚀刻停止层302。根据一个实施例，蚀刻停止层302的厚度约等于
在一些实施例中，蚀刻停止层302的材料包括不同于覆盖蚀刻停止层302的材料。材料的不同使得蚀刻停止层302的蚀刻速率慢于覆盖它的材料。蚀刻停止层302提供何时结束蚀刻工艺的明确指示，从而保护蚀刻停止层302下方的材料。
图4为根据本发明的各种实施例绘示于图3中所示的半导体装置于蚀刻停止层302上形成介电层402的后的剖面图。在蚀刻停止层302上形成介电层402。可由介电材料，例如氧化物或氮化硅形成介电层402，尽管也可使用其它合适的介电材料，如高介电常数介电材料。可使用PECVD工艺形成介电层402，虽然也可使用任何其他合适的工艺。
图5为根据本发明的各种实施例绘示于图4中所示的半导体装置于介电层402上方形成掩模层502后的剖面图。在介电层402上沉积掩模层502。在一些实施例中，可由光致抗蚀剂材料形成掩模层502。在整个说明书中，掩模层502也可称为光致抗蚀剂层502。
可通过合适的技术，例如旋转涂布等形成光致抗蚀剂层502。光致抗蚀剂材料可为SU-8(壳牌化学的注册商标)光敏环氧(photo-sensitive epoxy)、膜状的高分子材料和/或类似物。应当注意的是，本领域技术人士将认知虽然图5仅绘示一层光致抗蚀剂层，光致抗蚀剂层502可包括多光致抗蚀剂层。
图6为根据本发明的各种实施例绘示于图5中所示的半导体装置于掩模层502中形成开口602后的剖面图。考虑在图1所示的上漏极接触件130的位置和尺寸后，曝光光致抗蚀剂层502的选择区域。涂敷显影剂于光致抗蚀剂层502，从而于光致抗蚀剂层502中形成开口602。
在一些实施例中，开口602的最外缘大抵对准在图2中绘示的开口202的最外缘。开口602的宽度定义为W3，如图6中所示。
于图案化光致抗蚀剂层502后，介电层402的顶部有可能形成两个光致抗蚀剂材料区域，如图6所示。剩余的光致抗蚀剂区域有助于防止光致抗蚀剂层502下方的介电层402被下述于图7中的蚀刻工艺蚀刻掉。
图7为根据本发明的各种实施例绘示于图6中所示的半导体装置于进行蚀刻工艺后的剖面图。于半导体装置100进行如干蚀刻的蚀刻工艺。根据图6中所示的图案，结果是介电层402的暴露部份被去除。借由蚀刻停止层302的帮助，更精确地控制介电层402的蚀刻。如图7所示，蚀刻工艺造成在下漏极接触128之上的开口702。
具有蚀刻停止层302的一个有利特征是蚀刻停止层302的高选择性有助于避免过蚀刻(over-etch)问题，从而保护下漏极接触128的顶表面于施加蚀刻工艺于介电层402时不被损坏。
图8为根据本发明的各种实施例，绘示于图7中所示的半导体装置从半导体装置移除剩余光致抗蚀剂层后的剖面图。可由合适的光致抗蚀剂剥离技术如化学溶剂清洗(chemical solvent cleaming)、等离子体灰化(plasma etching)、干剥离(drystripping)和/或类似方法除去在图7所示的剩余的光致抗蚀剂层。光致抗蚀剂剥离技术是众所周知的，因此于本文不详细讨论其细节以避免重复。
图9为根据本发明的各种实施例绘示于图8中所示的半导体装置于对蚀刻停止层302进行蚀刻工艺后的剖面图。可由使用合适的蚀刻工艺如湿蚀刻、干蚀刻和/或类似工艺除去露出的蚀刻停止层302(图8中所示)。
在一些实施例中，由湿蚀刻工艺去除露出的蚀刻停止层302，其中施加清洗液于蚀刻停止层302。在一些实施例中，清洗液是基于氢氟酸(HF)的清洗溶液、基于氨水(NH4OH)的清洗液、基于羟胺(hydroxylamine)的清洗液、它们的任意组合及类似物。
可于施加清洗液至蚀刻停止层302的工艺前加热半导体装置100。在一实施例中，加热半导体装置100至约40℃。除去露出的蚀刻停止层302的时间为约30秒。在一替代实施例中，加热半导体装置100至约60℃。除去露出的蚀刻停止层302的时间为约10秒。
为了具有扩大的开口，蚀刻工艺被控制以去除部份保护层127、129和介电层402。具体而言，于蚀刻工艺完成后，如虚线A-A'所示，介电层402的第一边缘902垂直对准第一栅极隔离物125的最外缘。类似地，如虚线B-B'所示，介电层402的第二边缘904垂直对准第二栅极隔离物126的最外缘。在一替代性实施例中，介电层402的第一边缘902大抵上对准第一栅极间隔物125。介电层402的第二边缘904大抵上对准第二栅极间隔物126。
此外，第一保护层127的顶表面有自第一栅极隔离物125的顶表面的边缘向下延伸的第一斜坡，第二保护层129的顶表面有自第二栅极隔离物126的顶表面的边缘向下延伸的第二斜坡。如在图9中所示，第一保护层127顶表面的变化速率大抵上等于第二保护层129的顶表面的变化速率。
应当注意的是，保护层127和129由高温沉积工艺形成。如上及图2所描述，由ALD工艺以及用来将ALD工艺的温度增加至约550℃至约600℃的预热处理形成保护层127和129。反的，介电层402由工艺温度大约500℃的CVD工艺形成。当施加湿蚀刻工艺到保护层和介电层402上时，不同的沉积工艺造成蚀刻速率不同。该蚀刻速率差异有助于在保护层和介电层402形成不同的表面。
在完成蚀刻工艺后，于下漏极接触128上形成开口901。开口901包括两个部份。开口901的第一部份是矩形。第一部份位于介电层402中。开口901的第二部份是倒梯形。如图9所示，开口901的第二部份位于层间介电层120中。定义开口901的第一部份的宽度为W4。在整个描述中，可称W4为开口901的最大宽度。
如图9中所示，于蚀刻工艺期间移除部份介电层402。介电层402的侧壁分别对准栅极间隔物125和126的侧壁。如此一来，如图9所示，W4大于W3。在一些实施例中，W4与W3的比值介于约1.1至约1.3之间。
图10为根据本发明的各种实施例绘示于图9中所示的半导体装置于填入金属材料于半导体装置的开口后的剖面图。填入包括钨、钛、铝、铜、其组合和/或类似物的金属材料于开口901中(如图9中所示)。因此，于下漏极接触128上形成上漏极接触130。
如图10所示，上漏极接触130包括上部和下部。上漏极接触130的上部是矩形。上漏极接触130的下部是倒梯形。此外，上漏极接触130的下部与第一保护层127的第一斜坡和第二保护层129的第二斜坡接触。上漏极接触130上部的第一边缘垂直对准第一栅极间隔物125的最外缘。上漏极接触130上部的第二边缘垂直对准第二栅极间隔物126的最外缘。
图11为根据本发明的各种实施例绘示形成图1中所示的半导体装置方法的流程图。该流程图仅为范例，其不应不适当地限制权利要求的范围。本领域的通常技术人士将认知可具有许多变化、替换和修改。例如，图11中所示的各种步骤可被添加、移除、替换、重排和重复。
于步骤1102，提供一种包括具有共同漏极的两个晶体管的半导体装置。下漏极接触已经形成于两个晶体管的两个栅极之间的层间介电层中。于层间介电层中及下漏极接触上形成开口。
于步骤1104，在开口中和层间介电层的顶表面上沉积蚀刻停止层。蚀刻停止层由氮氧化铝(AlON)、氧化铝(Al2O3)、氮化铝(AlN)、氧化铪(HfOx)、氧化锆(ZrOx)和/或其组合等形成。
于步骤1106，于蚀刻停止层上形成介电层。由氮化硅形成介电层。介电层位于开口中和层间介电层上。
于步骤1108，于介电层上沉积光致抗蚀剂层。于步骤1110，根据预定的图案曝光光致抗蚀剂层。于步骤1112中，借由施加显影剂于光致抗蚀剂层，于光致抗蚀剂层中形成开口。
于步骤1114，进行蚀刻工艺于介电层直至露出蚀刻停止层。于步骤1116中，由合适的光致抗蚀剂去除工艺去除剩余的光致抗蚀剂层。
于步骤1118，由合适的蚀刻工艺去除露出的蚀刻停止层。在去除蚀刻停止层的过程中，去除保护层的上部和部份介电层。具体而言，控制蚀刻工艺使得介电层的第一边缘垂直对准第一晶体管的侧壁间隔物；介电层的第二边缘垂直对准第二晶体管的侧壁间隔物；第一保护层的顶表面有自第一晶体管的第一栅极间隔物的顶表面的边缘向下延伸的斜坡；第二保护层的顶表面有自第二晶体管的第二栅极间隔物的顶表面的边缘向下延伸的斜坡。
于步骤1120，借由电镀工艺填充导电材料于开口中以形成上漏极接触。上漏极接触位于下漏极接触之上且与的接触。
图12为根据本发明的各种实施例绘示具有扩大的漏极/源极接触的FinFET半导体装置的剖面图。在图2至图11所示的漏极接触工艺不仅应用于平面晶体管装置，而且还应用于FinFET装置。FinFET装置1200包括共用一个共同漏极的两个晶体管。这两个晶体管形成于基板104上。第一晶体管101包括第一栅极123和其栅极介电层121，漏极114及其接触128和130，以及第一源极112和其接触(未绘示)。第二晶体管102包括第二栅极124和其栅极介电层122，漏极114及其接触128和130，以及第二源极116和其接触(未绘示)。
可借由蚀刻部份鳍线，并借由合适的磊晶生长工艺生长源极/漏极区112、114和116以形成源极/漏极区112、114和116。如图12中所示，源极/漏极区112、114和116的顶表面高于栅极123和124的底表面。
图12中的上漏极接触130的形状类似于图1中所示，于此不再详细讨论以避免不必要的重复。如图12所示的具有扩大的漏极接触130的一个有利特征是扩大的漏极接触有助于降低接触电阻，从而改善FinFET半导体装置1200的性能。
根据一实施例，一种接触结构的制造方法，包括：形成一第一晶体管及一第二晶体管于一基板上，其中该第一晶体管及该第二晶体管共享一源极/漏极区，该源极/漏极区形成于该第一晶体管的一第一栅极及该第二晶体管的一第二栅极之间；形成一开口于一层间介电层中，且于该第一栅极及该第二栅极间；沉积一蚀刻停止层于该第一开口中，且于该层间介电层的一顶表面上；沉积一介电层于该蚀刻停止层上；沉积一光致抗蚀剂层于该介电层上；图案化该光致抗蚀剂层以于该光致抗蚀剂层中形成一第二开口，其中该第二开口的一最外缘与该第一开口的一最外缘对准；对该介电层施行一第一蚀刻工艺，直到露出该蚀刻停止层；对该蚀刻停止层进行一第二蚀刻工艺，直到移除该蚀刻停止层的一露出部份及该介电层的多部份以形成一第三开口，其中该第三开口的一最大宽度大于该第二开口的一最大宽度；以及以一导电材料填充该第三开口。
根据一实施例，一种接触结构的制造方法，包括：形成一第一晶体管及一第二晶体管于一基板上，其中：该第一晶体管包括一第一源极、一第一栅极及一漏极；以及该第二晶体管包括一第二源极、一第二栅极及该漏极。
该方法还包括形成一第一保护层及一第二保护层，分别沿着该第一晶体管及该第二晶体管的多侧壁间隔物，其中该第一保护层及该第二保护层于该第一栅极及该第二栅极间且于该漏极上；形成一下漏极接触于一层间介电层中及于该第一栅极及该第二栅极间；形成一第一开口于该层间介电层中及于该下漏极接触上；沉积一蚀刻停止层于该第一开口中及于该层间介电层的一顶表面上；沉积一介电层于该蚀刻停止层上；对该介电层施行一第一蚀刻工艺直到露出该蚀刻停止层；对该蚀刻停止层进行一第二蚀刻工艺直到移除该蚀刻停止层的一露出部份及部份该介电层以形成一第二开口，其中该第二开口一上部的宽度大于该第一开口一上部的宽度；以及以一导电材料填充该第二开口。
根据一实施例，一种接触结构设备，包括：一第一源极及一共同漏极，于一第一栅极的相反侧上；一第二源极及该共同漏极，于一第二栅极的相反侧上，其中：该第一栅极及该第二栅极位于一基板上的一层间介电层中；以及该第一栅极及该第二栅极分别被一第一栅极间隔物及一第二栅极间隔物围绕。
该设备还包括一第一保护层，沿着该第一栅极间隔物的一侧壁形成，其中该第一保护层位于该共同漏极上，且该第一保护层的一顶表面有一第一斜坡；一第二保护层，沿着该第二栅极间隔物的一侧壁形成，其中该第二保护层位于该共同漏极上，且该第二保护层的一顶表面有一第二斜坡；以及一第一漏极接触，形成于该第一栅极及该第二栅极间，其中该第一漏极接触一上部的宽度大于该第一漏极接触一下部的宽度。如本发明一些实施例所述的接触结构的制造方法，还包括：于在该层间介电层中形成该第一开口的步骤前，形成一下漏极接触于该层间介电层中，及该第一栅极和该第二栅极之间。
如本发明一实施例所述的接触结构的制造方法，还包括：于在该层间介电层中形成该第一开口的步骤前，形成一下漏极接触于该层间介电层中，及该第一栅极和该第二栅极之间。
如本发明一实施例所述的接触结构的制造方法，还包括：以该导电材料填充该第三开口以一上漏极接触，其中该上漏极接触的一底表面与该下漏极接触的一顶表面接触。
如本发明一实施例所述的接触结构的制造方法，还包括：于形成该第一开口于该层间介电层中的步骤之前，沿着该第一晶体管的一侧壁间隔物形成一第一保护层；以及沿着该第二晶体管的一侧壁间隔物形成一第二保护层。
如本发明一实施例所述的接触结构的制造方法，其中：于在该蚀刻停止层上进行该第二蚀刻工艺的步骤后，该第一保护层的一第一边缘垂直对准于该第一晶体管的该侧壁间隔物的一最外缘；以及该介电层的一第二边缘垂直对准于该第二晶体管的该侧壁间隔物的一最外缘。
如本发明一实施例所述的接触结构的制造方法，其中：于在该蚀刻停止层上进行该第二蚀刻工艺的步骤后，该第一保护层的一顶表面有一第一斜坡，自该第一晶体管的该侧壁间隔物的一顶表面的一边缘向下延伸；以及该第二保护层的一顶表面有一第二斜坡，自该第二晶体管的该侧壁间隔物的一顶表面的一边缘向下延伸。
如本发明一实施例所述的接触结构的制造方法，其中：该蚀刻停止层由氮氧化铝形成。
如本发明一实施例所述的接触结构的制造方法，其中：该介电层由氮化硅形成。
如本发明一实施例所述的接触结构的制造方法，还包括：以该导电材料填充该第三开口以形成一上漏极接触，该上漏极接触包括倒梯形的一第一部份及矩形的一第二部份。
如本发明一实施例所述的接触结构的制造方法，其中：该上漏极接触的该第一部份位于该层间介电层中且于该第一栅极及该第二栅极间；以及该上漏极接触的该第二部份位于该介电层中。
如本发明另一实施例所述的接触结构的制造方法，还包括：于对该介电层进行该第一蚀刻工艺的步骤前，沉积一光致抗蚀剂层于该介电层上；以及图案化该光致抗蚀剂层以于该光致抗蚀剂层中形成一第三开口，其中该第三开口的一最外缘大抵与该第一开口的一最外缘对准。
如本发明另一实施例所述的接触结构的制造方法，还包括：于进行该第二蚀刻工艺于该蚀刻停止层的步骤后，移除该介电层的该部份以使得：该介电层的一第一边缘与该第一晶体管的该侧壁间隔物的一最外缘对准；以及该介电层的一第二边缘与该第二晶体管的该侧壁间隔物的一最外缘对准。
如本发明另一实施例所述的接触结构的制造方法，还包括：于进行该第二蚀刻工艺于该蚀刻停止层的步骤后，移除部份该第一保护层及该第二保护层以使得：该第一保护层的一顶表面有一第一斜坡，自该第一晶体管的该侧壁间隔物的一顶表面的一边缘向下延伸；以及该第二保护层的一顶表面有一第二斜坡，自该第二晶体管的该侧壁间隔物的一顶表面的一边缘向下延伸。
如本发明另一实施例所述的接触结构的制造方法，还包括：以一导电材料填充该第二开口以形成一上漏极接触，其中：该第一保护层于该上漏极接触及该第一栅极间；该第二保护层于该上漏极接触及该第二栅极间；以及该上漏极接触的一上部的宽度大于该上漏极接触的一下部的宽度。
如本发明又一实施例所述的接触结构设备，还包括：一第二漏极接触，形成于该共同漏极及该第一漏极接触间，其中该第二漏极接触有一倒梯形。
如本发明又一实施例所述的接触结构设备，其中：该第一保护层的该顶表面的一改变速率与该第二保护层的该顶表面的一改变速率大抵相同。
如本发明又一实施例所述的接触结构设备，其中：该第一漏极接触的该上部有一矩形；以及该第一漏极接触的该下部有一倒梯形，且其中：该第一漏极接触的该下部与该第一斜坡及该第二斜坡接触；该第一漏极接触的该上部的一第一边缘与该第一栅极间隔物的一最外缘垂直对准；以及该第二漏极接触的该上部的一第二边缘与该第二栅极间隔物的一最外缘垂直对准。
如本发明又一实施例所述的接触结构设备，其中：该第一漏极接触的该上部的宽度与该第一保护层及该第二保护层间的最小宽度的比值介于大约1.1至大约1.3之间。
上述内容概述许多实施例的特征，因此任何本领域技术人员，可更加理解本发明的各面向。任何本领域技术人员，可能无困难地以本发明为基础，设计或修改其他工艺及结构，以达到与本发明实施例相同的目的及/或得到相同的优点。任何本领域技术人员也应了解，在不脱离本发明的精神和范围内做不同改变、代替及修改，如此等效的创造并没有超出本发明的精神及范围。

Claims (1)

1.一种接触结构的制造方法，其特征在于，包括：
形成一第一晶体管及一第二晶体管于一基板上，其中该第一晶体管及该第二晶体管共享一源极/漏极区，该源极/漏极区形成于该第一晶体管的一第一栅极及该第二晶体管的一第二栅极之间；
形成一第一开口于一层间介电层中，且于该第一栅极及该第二栅极间；
沉积一蚀刻停止层于该第一开口中，且于该层间介电层的一顶表面上；
沉积一介电层于该蚀刻停止层上；
沉积一光致抗蚀剂层于该介电层上；
图案化该光致抗蚀剂层以于该光致抗蚀剂层中形成一第二开口，其中该第二开口的一最外缘与该第一开口的一最外缘对准；
对该介电层施行一第一蚀刻工艺，直到露出该蚀刻停止层；
对该蚀刻停止层进行一第二蚀刻工艺，直到移除该蚀刻停止层的一露出部份及该介电层的多个部份以形成一第三开口，其中该第三开口的一最大宽度大于该第二开口的一最大宽度；以及
以一导电材料填充该第三开口。
CN201710402860.1A 2016-11-29 2017-06-01 接触结构制造方法及半导体装置 Active CN108122845B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/364,136 US10037918B2 (en) 2016-11-29 2016-11-29 Contact structure and method of fabricating the same
US15/364,136 2016-11-29

Publications (2)

Publication Number Publication Date
CN108122845A true CN108122845A (zh) 2018-06-05
CN108122845B CN108122845B (zh) 2022-04-05

Family

ID=62190473

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710402860.1A Active CN108122845B (zh) 2016-11-29 2017-06-01 接触结构制造方法及半导体装置

Country Status (3)

Country Link
US (3) US10037918B2 (zh)
CN (1) CN108122845B (zh)
TW (1) TWI745375B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022062494A1 (zh) * 2020-09-22 2022-03-31 长鑫存储技术有限公司 开口结构及其形成方法、接触插塞及其形成方法
US11929280B2 (en) 2020-09-22 2024-03-12 Changxin Memory Technologies, Inc. Contact window structure and method for forming contact window structure
US12002748B2 (en) 2020-09-22 2024-06-04 Changxin Memory Technologies, Inc. Contact window structure, metal plug and forming method thereof, and semiconductor structure

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496169B2 (en) 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US10037918B2 (en) * 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure and method of fabricating the same
FR3069369B1 (fr) * 2017-07-21 2019-11-01 Stmicroelectronics (Rousset) Sas Circuit integre comportant un contact partage masque
GB2582245B (en) * 2018-12-14 2021-05-19 Plessey Semiconductors Ltd Active matrix LED array precursor
CN111508843B (zh) * 2019-01-31 2023-07-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
KR20210090768A (ko) 2020-01-10 2021-07-21 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11328957B2 (en) 2020-02-25 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11264350B2 (en) 2020-03-19 2022-03-01 Nanya Technology Corporation Semiconductor device with composite dielectric structure and method for forming the same
KR20210152849A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US11776844B2 (en) * 2021-03-24 2023-10-03 Globalfoundries Singapore Pte. Ltd. Contact via structures of semiconductor devices
US20230065045A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact formation method and related structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5607879A (en) * 1995-06-28 1997-03-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for forming buried plug contacts on semiconductor integrated circuits
US7071517B2 (en) * 2002-10-31 2006-07-04 Samsung Electronics Co., Ltd. Self-aligned semiconductor contact structures and methods for fabricating the same
US8129235B2 (en) * 2007-03-15 2012-03-06 United Microelectronics Corp. Method of fabricating two-step self-aligned contact
US20130049222A1 (en) * 2011-08-30 2013-02-28 Won Sic Woo Semiconductor device and method of manufacturing the same
CN103915384A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9412660B1 (en) * 2015-06-05 2016-08-09 Globalfoundries Inc. Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure
CN105845652A (zh) * 2010-10-28 2016-08-10 台湾积体电路制造股份有限公司 用于减少栅极电阻的接触结构及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6359307B1 (en) * 2000-01-29 2002-03-19 Advanced Micro Devices, Inc. Method for forming self-aligned contacts and interconnection lines using dual damascene techniques
KR100487951B1 (ko) * 2003-02-11 2005-05-06 삼성전자주식회사 자기정렬 콘택홀을 갖는 반도체 장치및 그 제조방법
US9379013B1 (en) * 2014-12-04 2016-06-28 Sony Corporation Method for forming a self-aligned contact in a damascene structure used to form a memory device
US10037918B2 (en) * 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure and method of fabricating the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5607879A (en) * 1995-06-28 1997-03-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for forming buried plug contacts on semiconductor integrated circuits
US7071517B2 (en) * 2002-10-31 2006-07-04 Samsung Electronics Co., Ltd. Self-aligned semiconductor contact structures and methods for fabricating the same
US8129235B2 (en) * 2007-03-15 2012-03-06 United Microelectronics Corp. Method of fabricating two-step self-aligned contact
CN105845652A (zh) * 2010-10-28 2016-08-10 台湾积体电路制造股份有限公司 用于减少栅极电阻的接触结构及其制造方法
US20130049222A1 (en) * 2011-08-30 2013-02-28 Won Sic Woo Semiconductor device and method of manufacturing the same
CN103915384A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9412660B1 (en) * 2015-06-05 2016-08-09 Globalfoundries Inc. Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022062494A1 (zh) * 2020-09-22 2022-03-31 长鑫存储技术有限公司 开口结构及其形成方法、接触插塞及其形成方法
US11929280B2 (en) 2020-09-22 2024-03-12 Changxin Memory Technologies, Inc. Contact window structure and method for forming contact window structure
US12002748B2 (en) 2020-09-22 2024-06-04 Changxin Memory Technologies, Inc. Contact window structure, metal plug and forming method thereof, and semiconductor structure

Also Published As

Publication number Publication date
US10037918B2 (en) 2018-07-31
US20180308761A1 (en) 2018-10-25
US10770356B2 (en) 2020-09-08
US20180151560A1 (en) 2018-05-31
TWI745375B (zh) 2021-11-11
US20200402859A1 (en) 2020-12-24
TW201830578A (zh) 2018-08-16
US11282750B2 (en) 2022-03-22
CN108122845B (zh) 2022-04-05

Similar Documents

Publication Publication Date Title
CN108122845A (zh) 接触结构制造方法
US11075164B2 (en) Semiconductor device including a conductive feature over an active region
CN105977144B (zh) FinFET沟道的形成方法及其结构
CN102891148B (zh) 用于单栅极非易失性存储器件的结构和方法
CN102013424B (zh) 集成电路及其制法
CN102315127B (zh) 半导体装置与半导体元件的制法
KR101376808B1 (ko) 반도체 장치 및 반도체 장치를 형성하는 방법
CN103165674B (zh) 具有多阈值电压的FinFET
US10262894B2 (en) FinFET device and method for forming the same
CN108962994A (zh) 用于形成不同晶体管的源极/漏极区的注入
CN109494219B (zh) 集成电路
CN106206688A (zh) 半导体器件结构的结构和形成方法
CN103378153A (zh) 用于集成有电容器的FinFET的结构和方法
KR101419122B1 (ko) 반도체 집적 회로 제조 방법
CN102376538A (zh) 形成多晶硅电阻装置的方法以及半导体装置
US11923455B2 (en) Semiconductor device and method of forming the same
CN108615701A (zh) 半导体装置的制造方法
TWI715218B (zh) 半導體元件及其製造方法
US10847634B2 (en) Field effect transistor and method of forming the same
CN108122742A (zh) 半导体装置结构的制造方法
CN110571193B (zh) 单扩散隔断结构的制造方法和半导体器件的制造方法
CN220856579U (zh) 半导体装置
US11942541B2 (en) Semiconductor device and method for forming the same
TWI798543B (zh) 半導體裝置及其製造方法
TWI683351B (zh) 半導體裝置及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant