CN108962994A - 用于形成不同晶体管的源极/漏极区的注入 - Google Patents

用于形成不同晶体管的源极/漏极区的注入 Download PDF

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CN108962994A
CN108962994A CN201711246449.6A CN201711246449A CN108962994A CN 108962994 A CN108962994 A CN 108962994A CN 201711246449 A CN201711246449 A CN 201711246449A CN 108962994 A CN108962994 A CN 108962994A
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source
drain regions
injection
transistor
grid
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CN108962994B (zh
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于殿圣
廖忠志
崔壬汾
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括形成第一晶体管，形成第一晶体管包括形成第一栅极堆叠件，在第一栅极堆叠件的侧部上外延生长第一源极/漏极区，并且实施第一注入以注入第一源极/漏极区。该方法还包括形成第二晶体管，形成第二晶体管包括形成第二栅极堆叠件，在第二栅极堆叠件的侧壁上形成第二栅极间隔件，在第二栅极堆叠件的侧部上外延生长第二源极/漏极区，以及实施第二注入以注入第二源极/漏极区。形成层间电介质以覆盖第一源极/漏极区和第二源极/漏极区。在形成层间电介质之前实施第一注入，并且在形成层间电介质之后实施第二注入。本发明实施例涉及用于形成不同晶体管的源极/漏极区的注入。

Description

用于形成不同晶体管的源极/漏极区的注入
技术领域
本发明实施例涉及用于形成不同晶体管的源极/漏极区的注入。
背景技术
IC材料和设计中的技术进步产生了一代又一代IC，其中，每一代IC都具有比前一代IC更小且更复杂的电路。在IC发展过程中，功能密度(即，单位芯片面积上互连器件的数量)通常在增加，而几何尺寸(即，可使用制造工艺创建的最小组件(或线))却已减小。该按比例缩小工艺通常通过提高生产效率和降低相关成本而提供益处。
这种按比例缩小工艺还增加了处理和制造IC的复杂性并且为了实现这些进步，需要IC处理和制造中的类似发展。例如，已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管以代替平面晶体管。尽管制造FinFET器件的现有FinFET器件和方法已通常满足它们的期望目的，但是随着电路的不断增加的按比例缩小出现了更多的问题。例如，随着集成电路的不断增加的按比例缩小，用于不同电路的FinFET(诸如核心(逻辑)电路、静态随机存取存储器(SRAM)电路和输入-输出器件)可能会面临先前没有观察到的不同的问题。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：在第一突出鳍的第一部分的侧壁和顶面上形成第一栅极堆叠件；在第二突出鳍的第一部分的侧壁和顶面上形成第二栅极堆叠件；蚀刻所述第一突出鳍的第二部分和所述第二突出鳍的第二部分以分别形成第一凹槽和第二凹槽；分别在所述第一凹槽和所述第二凹槽中外延生长第一源极/漏极区和第二源极/漏极区；对所述第一源极/漏极区实施第一注入而不对所述第二源极/漏极区实施注入；在所述第一注入之后，形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及对所述第二源极/漏极区实施第二注入而不对所述第一源极/漏极区实施注入，其中，通过所述第二接触开口实施所述第二注入。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在半导体区上形成第一栅极堆叠件和第二栅极堆叠件；在所述第一栅极堆叠件的侧壁上形成第一栅极间隔件；在所述第二栅极堆叠件的侧壁上形成第二栅极间隔件；形成第一源极/漏极区和第二源极/漏极区，其中，所述第一源极/漏极区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘，并且所述第二源极/漏极区具有与所述第二栅极堆叠件的侧壁垂直对准的内边缘；对所述第一源极/漏极区实施第一注入以产生第一注入区，并且所述第一注入区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘；形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及对所述第二源极/漏极区实施第二注入以产生第二注入区，其中，所述第二注入区通过所述层间电介质的部分与所述第二栅极间隔件间隔开。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：形成第一晶体管，包括：形成第一栅极堆叠件；在所述第一栅极堆叠件的侧部上外延生长第一源极/漏极区；以及实施第一注入以注入所述第一源极/漏极区；形成第二晶体管，包括：形成第二栅极堆叠件；在所述第二栅极堆叠件的侧部上外延生长第二源极/漏极区；以及实施第二注入以注入所述第二源极/漏极区；以及形成层间电介质以覆盖所述第一源极/漏极区和所述第二源极/漏极区，其中，在形成所述层间电介质之前实施所述第一注入，并且在形成所述层间电介质之后，实施所述第二注入。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图15是根据一些实施例的形成鳍式场效应晶体管(FinFET)的中间阶段的截面图和透视图。
图16示出根据一些实施例的一些电路的布局。
图17示出根据一些实施例的形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例提供了晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指代相同的元件。在所示的示例性实施例中，使用鳍式场效应晶体管(FinFET)的形成作为实例来解释本发明的构思。平面晶体管还可以采用本发明的构思。
图16示出器件区100和200中的电路的示例性布局。在整个说明书中，器件区100是形成长沟道晶体管的区域，并且器件区200是形成短沟道晶体管的区域。应当理解，术语“长沟道”和“短沟道”是相对彼此而言的。长沟道晶体管具有比短沟道晶体管的沟道更长的沟道。根据本发明的一些实施例，长沟道器件区100包括静态随机存取存储器(SRAM)单元或输入-输出(IO)电路，并且其中的晶体管是长沟道晶体管。短沟道器件区200可以包括逻辑电路/晶体管(有时称为核心电路/晶体管)，并且其中的晶体管是短沟道晶体管。例如，图16示出器件区100中的SRAM单元102。根据可选实施例，器件区100包括IO晶体管。SRAM单元102包括形成在N阱中的p型晶体管PU1和PU2以及形成在P阱中的n型晶体管PD1、PD2、PG1和PG2。基于有源区(可以是半导体鳍)104A、104B、104C和104D以及栅电极106A、106B、106C和106D形成晶体管PU1、PU2、PD1、PD2、PG1和PG2。晶体管202位于器件区200中，并且基于有源区(其还可以是半导体鳍)204和栅电极206来形成。晶体管202可以是p型晶体管或n型晶体管。
根据本发明的一些实施例，如图15所示，短沟道器件的沟道长度Lg2小于约30nm，并且长沟道器件的沟道长度Lg1大于约60nm。根据一些实施例，比率Lg1/Lg2可以大于约2.0，并且可以在约2和约10之间的范围内。
图1至图15示出根据本发明的一些实施例的形成晶体管的中间阶段的截面图和透视图。图1至图15中示出的步骤还在图17中示出的工艺流程300中示意性地示出。形成的晶体管包括位于器件区100中的长沟道晶体管(诸如作为实例的长沟道FinFET)和位于器件区200中的短沟道晶体管(诸如作为实例的短沟道FinFET)。根据本发明的一些示例性实施例，器件区100和200中的长沟道晶体管和短沟道晶体管分别具有相同的导电类型，并且可以都是p型晶体管或都是n型晶体管。例如，形成在器件区100中的长沟道晶体管可以是诸如图16中的晶体管PU1或PU2的p型晶体管，诸如图16中的晶体管PD1、PD2、PG1或PG2的n型晶体管，或IO电路中的p型晶体管或n型晶体管。形成在器件区200中的短沟道晶体管可以是p型晶体管或n型晶体管，具有图16所示的布局。
图1示出初始结构的透视图。初始结构包括晶圆10，晶圆10进一步包括衬底20。衬底20可以是半导体衬底，半导体衬底可以是硅衬底、硅锗衬底或由其他半导体材料形成的衬底。衬底20可以掺杂有p型杂质或n型杂质。诸如浅沟槽隔离(STI)区的隔离区22可以形成为延伸到衬底20中。衬底20的位于相邻STI区22之间的部分称为半导体带124和224，其中，半导体带124和224分别位于器件区100和200中。
STI区22可以包括衬垫氧化物(未示出)。衬垫氧化物可以由热氧化物形成，该热氧化物通过衬底20的表面层的热氧化形成。衬垫氧化物还可以是使用例如原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)或化学汽相沉积(CVD)所形成的沉积的氧化硅层。STI区22还包括位于衬垫氧化物上方的介电材料，其中可以使用可流动化学汽相沉积(FCVD)、旋涂等形成介电材料。
参考图2，凹进STI区22，从而使得半导体带124和224的顶部突出为高于相邻STI区22的顶面22A，以形成突出鳍124'和224'。相应步骤在图17所示的工艺中示出为步骤302。可以使用干蚀刻工艺实施蚀刻，其中NH3和NF3用作蚀刻气体。在蚀刻工艺期间，可以生成等离子体。还可以包括氩气。根据本发明的可选实施例，使用湿蚀刻工艺实施STI区22的凹进。例如，蚀刻化学物质可以包括稀释的HF。
参考图3，分别在突出鳍124'和224'的顶面和侧壁上形成伪栅极堆叠件130和230。相应步骤在图17所示的工艺中示出为步骤304。伪栅极堆叠件130可以包括伪栅极电介质132和位于伪栅极电介质132上方的伪栅电极134。伪栅极堆叠件230可以包括伪栅极电介质232和位于伪栅极电介质232上方的伪栅电极234。例如，可以使用多晶硅形成伪栅电极134和234，并且还可以使用其他材料。每个伪栅极堆叠件130和230还可以包括一个(或多个)硬掩模层136和236。硬掩模层136和236可以由氮化硅、碳氮化硅等形成。每个伪栅极堆叠件130和230分别横跨在单个或多个突出鳍124'和224'的上方。伪栅极堆叠件130和230还可以具有分别与相应的突出鳍124'和224'的纵向方向垂直的纵向方向。
接下来，分别在伪栅极堆叠件130和230的侧壁上形成栅极间隔件138和238。同时，还可以分别在突出鳍124'和224'的侧壁上形成鳍间隔件(未示出)。根据本发明的一些实施例，栅极间隔件138和238由诸如碳氮氧化硅(SiOCN)、氮化硅等的介电材料形成并且可以具有单层结构或包括多个介电层的多层结构。
根据一些实施例，每个栅极间隔件138包括低k介电层138A和非低k介电层138B(参考图6B)，其中通过毯式沉积步骤，以及之后的各向异性蚀刻步骤来形成层138A和138B中的每层。低k介电层138A可以由介电常数(k值)低于约3.0的低k介电材料形成，其可由SiON或SiOCN形成，其中形成有孔以便降低其k值。例如，非低k介电层138B可以由氮化硅形成。栅极间隔件238具有与栅极间隔件138相同的结构，并且可以包括分别由与层138A和138B相同的材料形成的层238A和238B。
然后实施蚀刻步骤(以下称为源极/漏极凹进)以蚀刻突出鳍124'和224'(以及下面的带124和224的部分)的未被伪栅极堆叠件130和230以及栅极间隔件138和238覆盖的部分，得到图4所示的结构。该凹进可以是各向异性的，并且因此鳍124'和224'的直接位于相应的伪栅极堆叠件130/230和栅极间隔件138/238下方的部分受到保护，并且不被蚀刻。根据一些实施例，凹进的半导体带124和224的顶面可以低于相邻的STI区22的顶面。因此，在STI区22之间形成凹槽140和240。可以在共同的蚀刻工艺中或在单独的工艺中实施凹进器件区100和200，并且凹槽140的深度可以等于或不等于凹槽240的深度。
接下来，通过在凹槽140和240中同时(或单独地)选择性地生长半导体材料来形成外延区(源极/漏极区)，从而得到图5中的结构。相应步骤在图17所示的工艺中示出为步骤306。根据一些示例性实施例，外延区142和242包括硅锗或硅。取决于所得到的FinFET是p型FinFET还是n型FinFET，可以随着外延的进行原位掺杂p型杂质或n型杂质。例如，当所得到的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)。相反地，当所得到的FinFET是n型FinFET时，可以生长硅磷(SiP)或硅碳磷(SiCP)。根据一些实施例，原位掺杂的p型杂质或n型杂质的浓度可以高于约1×1020/cm3，并且可以介于约1×1020/cm3和约2×1021/cm3之间。根据本发明的可选实施例，外延区142和242由诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或者它们的多层的Ⅲ-Ⅴ族化合物半导体形成。在用外延半导体材料填充凹槽140和240之后，外延区142和242的进一步外延生长导致外延区142和242水平扩展，并且可以形成小平面。相邻的外延区142和242可以连接或不连接。在整个说明书中，外延区142和242称为源极/漏极区。
参考图6A，形成并图案化光刻胶243。器件区200被光刻胶243覆盖，并且器件区100不被光刻胶覆盖。接下来，实施注入以注入p型杂质或n型杂质。相应步骤在图17所示的工艺中示出为步骤308。该注入称为外延后源极/漏极注入。由箭头139表示注入。注入的杂质的导电类型与在图5所示的步骤中引入的原位掺杂的杂质的导电类型相同。例如，如果在器件区100和200中所得到的FinFET是p型，则注入的杂质也是p型，并且如果器件区100和200中得到的FinFET为n型，则注入的杂质也是n型。作为注入的结果，源极/漏极区142中的杂质浓度可以增加至原位掺杂的杂质的杂质浓度的两倍至五倍。
图6B示出图6A所示结构的截面图，其中该截面图包括可以从图6A中包括线A-A的垂直平面和包括线B-B的垂直平面获得的截面图。根据一些实施例，垂直地实施注入。注入区145的底部的可能位置标记为145'，其可以高于、等于或低于外延区142的底部。源极/漏极区242由于光刻胶243而不被任何外延后注入而注入。由于使用与图4所示的蚀刻相同的掩模(栅极堆叠件130和间隔件138)实施注入，注入区145延伸到源极/漏极区142的内边缘和外边缘。在注入之后去除光刻胶243。
图7A示出形成接触蚀刻停止层(CESL)147和247以及层间电介质(ILD)46的透视图。相应步骤在图17所示的工艺中示出为步骤310。根据本发明的一些实施例，CESL 147和247由氮化硅、碳氮化硅等形成。可以使用诸如ALD或CVD的共形沉积方法形成CESL 147和247。ILD46形成在CESL 147和247上方，并且可以使用例如FCVD、旋涂、CVD等形成。ILD 46可以由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等形成。可以实施诸如化学机械抛光(CMP)或研磨的平坦化以使ILD46、伪栅极堆叠件130和230以及栅极间隔件138和238的顶面彼此齐平。
图7B示出图7A所示的结构的截面图，其截面图是从图7A中包括线A-A的垂直平面和包括线B-B的垂直平面获得的。在形成图7A和图7B所示的结构之后，利用金属栅极和替换栅极电介质替换伪栅极堆叠件130和230，其中，该伪栅极堆叠件包括硬掩模层136和236、伪栅电极134和234以及伪栅极电介质132和232，如图8和图9所示。在图6B、图7B，以及图8至图15中，示出STI区22的顶面122A和222A，并且突出鳍124'和224'分别突出为高于顶面122A和222A。
为了形成替换栅极，去除如图7A和图7B所示的硬掩模层136和236、伪栅电极134和234以及伪栅极电介质132和232，形成如图8所示的开口148和248。相应步骤在图17所示的工艺中示出为步骤312。突出鳍124'和224'的顶面和侧壁分别暴露于开口148和248。
接下来，参考图9，形成替换栅极堆叠件150和250，并且分别在栅极堆叠件150和250上方形成硬掩模168和268。相应步骤在图17所示的工艺中示出为步骤314。替换栅极堆叠件150和硬掩模168位于相对的栅极间隔件138之间，并且替换栅极堆叠件250和硬掩模268位于相对的栅极间隔件238之间。可以分别在开口148和248(图8)中形成额外的栅极间隔件151和251。下面简要讨论形成工艺。
根据一些实施例，栅极间隔件151和251首先形成为内衬于开口151和251的侧壁。根据可选实施例，不形成栅极间隔件151和251。为了形成栅极间隔件151和251，例如，可以使用诸如ALD或CVD的沉积方法形成毯式栅极间隔件层。毯式栅极间隔件层是共形的。根据本发明的一些实施例，栅极间隔件层由氮化硅(SiN)、SiC、SiON等形成。栅极间隔件151和251将分离后续形成的金属栅极以使其远离源极/漏极区142和242，并且减少它们之间的泄漏和电短路的可能性。栅极间隔件151可以包括低k介电层151A和介电层151B，其中，低k介电层151A由多孔SiON形成，以及介电层151B可以是高k介电层或具有大致等于3.9的k值(并且因此既不是高k介电材料也不是低k介电材料)。例如，低k介电层151A的k值可以介于约3.0和约3.5之间。栅极间隔件251可以具有与栅极间隔件151相同的结构，并且因此还可以包括由与介电层151A相同的材料形成的介电层251A和由与介电层151B相同的材料形成的介电层251B。
如图9所示，栅极堆叠件150和250包括分别延伸到开口148和248中的栅极电介质154/156和254/256。根据本发明的一些实施例，栅极电介质包括分别形成在突出鳍124'和224'的暴露的表面上的界面层(IL)154和254。每个IL 154和254可以包括通过突出鳍124'和224'的热氧化、化学氧化工艺或沉积工艺形成的诸如氧化硅层的氧化物层。栅极电介质还可以包括位于对应的IL 154和254上方的高k介电层156和256。高k介电层156和256可以由诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料形成。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0，并且有时高达20或更高。高k介电层156和256形成为共形层，并且分别在突出鳍124'和224'的侧壁以及栅极间隔件138/151和238/251的侧壁上延伸。根据本发明的一些实施例，使用ALD或CVD形成高k介电层156和256。
进一步参考图9，通过沉积形成含金属导电层162和262。可以使用诸如ALD或CVD的共形沉积方法实施沉积，从而使得含金属层162/262(和每个子层)的水平部分的水平厚度和垂直部分的垂直厚度具有大致彼此相等的厚度。例如，水平厚度和垂直厚度可以具有小于水平厚度和垂直厚度的约20％或10％的差值。
每个含金属层162和262包括至少一个层，或者可以包括由不同材料形成的多个层(未示出)。可以在共同的沉积工艺或单独的沉积工艺中形成含金属导电层162和262中的相应层。含金属层162和262中的层的材料可以包括根据相应的FinFET是n型FinFET还是p型FinFET而选择的功函金属。例如，当FinFET是n型FinFET时，每个含金属层162和262可以分别包括氮化钛(TiN)层、氮化钽(TaN)层和基于Al的层(例如由TiAl、TiAlN、TiAlC、TaAlN或TaAlC形成)。当FinFET是p型FinFET时，每个含金属层162和262可以分别包括TiN层、TaN层和另一TiN层。层162和262还可以包括两层或多于三层。
然后将填充金属填充在层162和262上方以形成金属区164和264。根据一些示例性实施例，填充金属包括W、Cu、Co、Al、Ru或它们的合金。在沉积金属区164和264之后，实施诸如CMP或机械研磨的平坦化步骤以去除位于ILD 46的顶面上方的沉积层的多余部分，并且因此形成栅极堆叠件150和250。
接下来，凹进栅极堆叠件150和250以形成凹槽，然后将介电材料填充到凹槽中以形成硬掩模168和268。然后实施另一平坦化步骤以使硬掩模168和268的顶面与ILD 46的顶面齐平。硬掩模168和268可以是由氮化硅、氮氧化硅、碳氧化硅等形成的介电硬掩模。
在后续步骤中，如图10所示，蚀刻ILD 46和CESL 147和247以形成接触开口170和270。相应步骤在图17所示的工艺中示出为步骤316。因此暴露源极/漏极区142和242。图11示出形成光刻胶172以覆盖器件区100，留下器件区200未被覆盖。接下来，实施注入以注入与图6A和6B所示的外延后注入具有相同的导电类型的p型杂质或n型杂质。图11所示的注入称为接触后源极/漏极注入。相应步骤在图17所示的工艺中示出为步骤318。由箭头273表示注入。作为注入的结果，注入区245中的杂质浓度可以增加原位掺杂的杂质的杂质浓度的两倍至五倍。可以垂直地实施注入。
如图11所示，接触开口270通过水平距离D1与栅极间隔件238间隔开。距离D1具有介于约5nm和约10nm之间的非零值。因此，相比于通过图6A和图6B所示的外延后注入形成的注入区145，相应的注入区245与相应晶体管的沟道区间隔开的距离更远。注入区245的底部的可能位置标记为245'，其可以高于、等于或低于外延区242的底部。源极/漏极区142由于光刻胶172而不被任何接触后注入而注入。然后去除光刻胶172，得到图12所示的结构。
图13示出形成源极/漏极硅化物区174和274以及源极/漏极接触插塞182和282。相应步骤在图17所示的工艺中示出为步骤320。根据一些实施例，金属层176和276(例如钛层)沉积为毯式层，接着在金属层176和276的顶部上进行氮化工艺，以形成金属氮化物层178和278。金属层176和276的底部未被氮化。接下来，实施退火(其可以是快速热退火)以使金属层176和276与源极/漏极区142和242的顶部部分反应以形成硅化物区174和274。金属层176和276的位于ILD 46的侧壁上的部分不反应。然后例如通过填充钨、钴等形成金属区180和280，然后通过平坦化去除多余的材料，得到较低的源极/漏极接触插塞182和282。接触插塞182包括层176、178和180，以及接触插塞282包括层276、278和280。因此，形成长沟道晶体管199和短沟道晶体管299。
参考图14，形成蚀刻停止层84。根据一些实施例，蚀刻停止层84由SiN、SiCN、SiC、SiOCN或另一介电材料形成。形成方法可以包括PECVD、ALD、CVD等。接下来，在蚀刻停止层84上方形成ILD 86。可以从与用于形成ILD 46的相同的候选材料(和方法)中选择ILD 86的材料，并且ILD 46和86可以由相同或不同的介电材料形成。根据一些实施例，ILD 86使用PECVD、CVD、旋涂等形成，并且可以包括氧化硅(SiO2)。
蚀刻ILD 86和蚀刻停止层84以形成开口(未示出)。例如，可以使用反应离子蚀刻(RIE)来实施蚀刻。如图15所示，在后续步骤中，形成插塞/通孔188、190、288和290。根据本发明的一些实施例，插塞/通孔188、190、288和290包括阻挡层92和位于阻挡层上方的含金属材料94。根据本发明的一些实施例，形成插塞/通孔188、190、288和290包括形成毯式阻挡层92并且在毯式阻挡层上方形成含金属材料94，并实施平坦化以去除毯式阻挡层和含金属材料的多余部分。阻挡层92可以由诸如氮化钛或氮化钽的金属氮化物形成。含金属材料94可以由钨、钴、铜等形成。根据一些实施例，介电接触间隔件196和296形成为环绕插塞/通孔188、190、288和290。
本发明的实施例具有一些优势特征。由于在器件区200中形成的晶体管是短沟道晶体管，因此如果使用外延后注入来实施源极/漏极注入，则注入的杂质更靠近沟道，并且更可能扩散到沟道区以降低晶体管的短沟道效应和漏致势垒降低(DIBL)性能。因此，对于器件区200中的短沟道器件，实施接触后注入，并且不实施外延后注入。相反，对于器件区100中的长沟道晶体管，例如SRAM晶体管，布局效应可能导致阈值电压不利地增加。外延后注入更靠近相应晶体管的沟道，并且因此具有降低阈值电压并降低沟道电阻的效果。此外，由于注入的杂质扩散到沟道区中，长沟道晶体管受短沟道效应和DIBL性能降低的影响较少。然而，在传统工艺中，对于长沟道晶体管和短沟道晶体管同时实施源极/漏极注入，并且不能调整长沟道晶体管和短沟道晶体管的器件性能。
根据本发明的一些实施例，一种方法包括在第一突出鳍的第一部分的侧壁和顶面上形成第一栅极堆叠件，在第二突出鳍的第一部分的侧壁和顶面上形成第二栅极堆叠件，蚀刻第一突出鳍的第二部分和第二突出鳍的第二部分以分别形成第一凹槽和第二凹槽，分别在第一凹槽和第二凹槽中外延生长第一源极/漏极区和第二源极/漏极区，并且对第一源极/漏极区实施第一注入而不对第二源极/漏极区实施注入。在第一注入之后，形成ILD以覆盖第一源极/漏极区和第二源极/漏极区。该方法还包括在ILD中形成第一接触开口和第二接触开口以露出第一源极/漏极区和第二源极/漏极区，并且对第二源极/漏极区实施第二注入而不对第一源极/漏极区实施注入。通过第二接触开口实施第二注入。
根据本发明的一些实施例，一种方法包括在半导体区上形成第一栅极堆叠件和第二栅极堆叠件，在第一栅极堆叠件的侧壁上形成第一栅极间隔件，在第二栅极堆叠件的侧壁上形成第二栅极间隔件，并且形成第一源极/漏极区和第二源极/漏极区。第一源极/漏极区具有与第一栅极堆叠件的侧壁大致垂直对准的内边缘，并且第二源极/漏极区具有与第二栅极堆叠件的侧壁大致垂直对准的内边缘。对第一源极/漏极区实施第一注入以产生第一注入区，并且第一注入区具有与第一栅极堆叠件的侧壁垂直对准的内边缘。形成ILD以覆盖第一源极/漏极区和第二源极/漏极区。在ILD中形成第一接触开口和第二接触开口以露出第一源极/漏极区和第二源极/漏极区。对第二源极/漏极区实施第二注入以产生第二注入区。第二注入区通过ILD的部分与第二栅极间隔件隔开。
根据本发明的一些实施例，一种方法包括形成第一晶体管，形成第一晶体管包括形成第一栅极堆叠件，在第一栅极堆叠件的侧部上外延生长第一源极/漏极区，并且实施第一注入以注入第一源极/漏极区。该方法还包括形成第二晶体管，形成第二晶体管包括形成第二栅极堆叠件，在第二栅极堆叠件的侧壁上形成第二栅极间隔件，在第二栅极堆叠件的侧部上外延生长第二源极/漏极区，以及实施第二注入以注入第二源极/漏极区。形成层间电介质以覆盖第一源极/漏极区和第二源极/漏极区。在形成层间电介质之前实施第一注入，在形成层间电介质之后实施第二注入。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，包括：在第一突出鳍的第一部分的侧壁和顶面上形成第一栅极堆叠件；在第二突出鳍的第一部分的侧壁和顶面上形成第二栅极堆叠件；蚀刻所述第一突出鳍的第二部分和所述第二突出鳍的第二部分以分别形成第一凹槽和第二凹槽；分别在所述第一凹槽和所述第二凹槽中外延生长第一源极/漏极区和第二源极/漏极区；对所述第一源极/漏极区实施第一注入而不对所述第二源极/漏极区实施注入；在所述第一注入之后，形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及对所述第二源极/漏极区实施第二注入而不对所述第一源极/漏极区实施注入，其中，通过所述第二接触开口实施所述第二注入。
在上述方法中，所述第一源极/漏极区是第一晶体管的部分，并且所述第二源极/漏极区是第二晶体管的部分，并且所述第一晶体管具有比所述第二晶体管更长的沟道。
在上述方法中，还包括在所述第一栅极堆叠件的侧壁上形成第一栅极间隔件并且在所述第二栅极堆叠件的侧壁上形成第二栅极间隔件，其中，所述第二接触开口通过所述层间电介质的部分与所述第二栅极间隔件隔开。
在上述方法中，所述第一晶体管是静态随机存取存储器(SRAM)单元或输入-输出电路中的晶体管，并且所述第二晶体管是核心电路。
在上述方法中，所述第一注入和所述第二注入引入相同的导电类型的杂质。
在上述方法中，垂直地实施所述第一注入和所述第二注入。
在上述方法中，所述第二注入导致额外的注入区，并且所述额外的注入区的底面高于所述第一源极/漏极区的底部。
在上述方法中，所述第二注入导致额外的注入区，并且所述额外的注入区的底面低于所述第一源极/漏极区的底部。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在半导体区上形成第一栅极堆叠件和第二栅极堆叠件；在所述第一栅极堆叠件的侧壁上形成第一栅极间隔件；在所述第二栅极堆叠件的侧壁上形成第二栅极间隔件；形成第一源极/漏极区和第二源极/漏极区，其中，所述第一源极/漏极区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘，并且所述第二源极/漏极区具有与所述第二栅极堆叠件的侧壁垂直对准的内边缘；对所述第一源极/漏极区实施第一注入以产生第一注入区，并且所述第一注入区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘；形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及对所述第二源极/漏极区实施第二注入以产生第二注入区，其中，所述第二注入区通过所述层间电介质的部分与所述第二栅极间隔件间隔开。
在上述方法中，形成所述第一源极/漏极区和所述第二源极/漏极区包括：蚀刻所述半导体区以分别形成第一凹槽和第二凹槽，以及分别在所述第一凹槽和所述第二凹槽中外延生长所述第一源极/漏极区和所述第二源极/漏极区。
在上述方法中，还包括当生长所述第一源极/漏极区和所述第二源极/漏极区时，原位掺杂杂质。
在上述方法中，所述第一源极/漏极区是第一晶体管的部分，并且所述第二源极/漏极区是第二晶体管的部分，并且所述第一晶体管是静态随机存取存储器(SRAM)单元或输入输出电路中的晶体管，并且所述第二晶体管位于核心电路中。
在上述方法中，所述第一注入和所述第二注入引入相同导电类型的杂质。
在上述方法中，垂直地实施所述第一注入和所述第二注入。
在上述方法中，在所述第一注入中，对所述第二源极/漏极区不实施注入。
在上述方法中，在所述第二注入中，对所述第一源极/漏极区不实施注入。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：形成第一晶体管，包括：形成第一栅极堆叠件；在所述第一栅极堆叠件的侧部上外延生长第一源极/漏极区；以及实施第一注入以注入所述第一源极/漏极区；形成第二晶体管，包括：形成第二栅极堆叠件；在所述第二栅极堆叠件的侧部上外延生长第二源极/漏极区；以及实施第二注入以注入所述第二源极/漏极区；以及形成层间电介质以覆盖所述第一源极/漏极区和所述第二源极/漏极区，其中，在形成所述层间电介质之前实施所述第一注入，并且在形成所述层间电介质之后，实施所述第二注入。
在上述方法中，还包括蚀刻所述层间电介质以形成接触开口，其中，通过所述接触开口实施第二注入。
在上述方法中，在所述第二注入中，不注入所述第一源极/漏极区。
在上述方法中，所述第一晶体管具有比所述第二晶体管更长的沟道。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
在第一突出鳍的第一部分的侧壁和顶面上形成第一栅极堆叠件；
在第二突出鳍的第一部分的侧壁和顶面上形成第二栅极堆叠件；
蚀刻所述第一突出鳍的第二部分和所述第二突出鳍的第二部分以分别形成第一凹槽和第二凹槽；
分别在所述第一凹槽和所述第二凹槽中外延生长第一源极/漏极区和第二源极/漏极区；
对所述第一源极/漏极区实施第一注入而不对所述第二源极/漏极区实施注入；
在所述第一注入之后，形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；
在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及
对所述第二源极/漏极区实施第二注入而不对所述第一源极/漏极区实施注入，其中，通过所述第二接触开口实施所述第二注入。
2.根据权利要求1所述的方法，其中，所述第一源极/漏极区是第一晶体管的部分，并且所述第二源极/漏极区是第二晶体管的部分，并且所述第一晶体管具有比所述第二晶体管更长的沟道。
3.根据权利要求1所述的方法，还包括在所述第一栅极堆叠件的侧壁上形成第一栅极间隔件并且在所述第二栅极堆叠件的侧壁上形成第二栅极间隔件，其中，所述第二接触开口通过所述层间电介质的部分与所述第二栅极间隔件隔开。
4.根据权利要求1所述的方法，其中，所述第一晶体管是静态随机存取存储器(SRAM)单元或输入-输出电路中的晶体管，并且所述第二晶体管是核心电路。
5.根据权利要求1所述的方法，其中，所述第一注入和所述第二注入引入相同的导电类型的杂质。
6.根据权利要求1所述的方法，其中，垂直地实施所述第一注入和所述第二注入。
7.根据权利要求1所述的方法，其中，所述第二注入导致额外的注入区，并且所述额外的注入区的底面高于所述第一源极/漏极区的底部。
8.根据权利要求1所述的方法，其中，所述第二注入导致额外的注入区，并且所述额外的注入区的底面低于所述第一源极/漏极区的底部。
9.一种形成半导体器件的方法，包括：
在半导体区上形成第一栅极堆叠件和第二栅极堆叠件；
在所述第一栅极堆叠件的侧壁上形成第一栅极间隔件；
在所述第二栅极堆叠件的侧壁上形成第二栅极间隔件；
形成第一源极/漏极区和第二源极/漏极区，其中，所述第一源极/漏极区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘，并且所述第二源极/漏极区具有与所述第二栅极堆叠件的侧壁垂直对准的内边缘；
对所述第一源极/漏极区实施第一注入以产生第一注入区，并且所述第一注入区具有与所述第一栅极堆叠件的侧壁垂直对准的内边缘；
形成层间电介质(ILD)以覆盖所述第一源极/漏极区和所述第二源极/漏极区；
在所述层间电介质中形成第一接触开口和第二接触开口以露出所述第一源极/漏极区和所述第二源极/漏极区；以及
对所述第二源极/漏极区实施第二注入以产生第二注入区，其中，所述第二注入区通过所述层间电介质的部分与所述第二栅极间隔件间隔开。
10.一种形成半导体器件的方法，包括：
形成第一晶体管，包括：
形成第一栅极堆叠件；
在所述第一栅极堆叠件的侧部上外延生长第一源极/漏极区；以及
实施第一注入以注入所述第一源极/漏极区；
形成第二晶体管，包括：
形成第二栅极堆叠件；
在所述第二栅极堆叠件的侧部上外延生长第二源极/漏极区；以及
实施第二注入以注入所述第二源极/漏极区；以及
形成层间电介质以覆盖所述第一源极/漏极区和所述第二源极/漏极区，其中，在形成所述层间电介质之前实施所述第一注入，并且在形成所述层间电介质之后，实施所述第二注入。
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