CN111129121A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111129121A
CN111129121A CN201910114968.XA CN201910114968A CN111129121A CN 111129121 A CN111129121 A CN 111129121A CN 201910114968 A CN201910114968 A CN 201910114968A CN 111129121 A CN111129121 A CN 111129121A
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region
gate electrode
semiconductor
source
drain
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蔣昕志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在一些实施例中，本公开涉及一种半导体装置，所述半导体装置包括位于块状氧化物之上的半导体区，所述块状氧化物位于半导体衬底之上。在所述块状氧化物上方有下部源极区，所述下部源极区通过所述半导体区的下部部分而在横向上与下部漏极区间隔开。上部源极区通过半导体区的上部部分而在横向上与上部漏极区间隔开且在垂直方向上与所述下部源极区及所述下部漏极区间隔开。所述上部源极区耦合到所述下部源极区，且所述上部漏极区耦合到所述下部漏极区。耦合到所述半导体衬底且位于栅极氧化物之上的栅极电极位于所述半导体区的所述上部部分上方。所述半导体区的所述下部部分及所述上部部分分别包括第一沟道区及第二沟道区。

Description

半导体装置
技术领域
本发明实施例是涉及半导体装置。
背景技术
随着技术快速进步，工程师们致力于使装置更小、但更复杂以改善并开发更高效、更可靠且具有更多能力的电子装置。实现这些目标的一种方式是通过改善晶体管的设计，因为电子装置包括大量的晶体管，这些晶体管一同施行装置的功能。整体电子装置性能可因晶体管例如更小、功耗更低且具有更快的开关速度而受益。
发明内容
在一些实施例中，本公开涉及一种半导体装置，所述半导体装置包括：块状氧化物，设置在半导体衬底之上；半导体区，设置在所述块状氧化物之上；下部源极区及下部漏极区，其中所述下部源极区及所述下部漏极区位于所述块状氧化物上方且直接接触所述块状氧化物，并且所述下部源极区与所述下部漏极区通过所述半导体区的下部部分在横向上间隔开；上部源极区及上部漏极区，所述上部源极区耦合到所述下部源极区，所述上部漏极区耦合到所述下部漏极区，其中所述上部源极区通过所述半导体区的上部部分而在横向上与所述上部漏极区间隔开，且其中所述上部源极区及所述上部漏极区在垂直方向上与所述下部源极区及所述下部漏极区间隔开；栅极氧化物，设置在所述半导体区的所述上部部分之上；栅极电极，设置在所述栅极氧化物正上方，所述栅极电极耦合到所述半导体衬底；第一沟道区，位于所述半导体区的所述下部部分内、所述块状氧化物上方以及所述下部源极区与所述下部漏极区之间；以及第二沟道区，位于所述半导体区的所述上部部分内、所述栅极氧化物下方以及所述上部源极区与所述上部漏极区之间，其中所述第二沟道区平行于所述第一沟道区。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A到图1D示出了具有包括两个沟道区的晶体管的集成芯片的一些实施例的剖视图。
图2A到图2B示出了具有包括四个沟道区的晶体管的集成芯片的一些附加实施例的剖视图。
图3到图11示出了形成具有包括两个沟道区的晶体管的集成芯片的方法的一些实施例的剖视图。
图12示出了形成具有包括两个沟道区的晶体管的集成芯片的方法的一些实施例的流程图。
图13到图22示出了形成具有包括四个沟道区的晶体管的集成芯片的方法的一些附加实施例的剖视图。
图23示出了形成具有包括四个沟道区的晶体管的集成芯片的方法的一些附加实施例的附加流程图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及配置形式的具体实例以简化本公开内容。当然，这些仅为实例而并非旨在进行限制。例如，在以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征以使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而并非自身表示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下”、“在...下面”、“下部的”、“上方”、“上部的”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
如今的电子装置中的典型的晶体管包括形成在半导体衬底内的源极及漏极，使得源极与漏极通过半导体衬底中的本体区(body region)而分隔开。半导体衬底可为位于块状氧化物顶上的硅以及被称为绝缘体上硅(silicon-on-insulator，SOI)衬底的衬底。源极及漏极具有与本体区的第二掺杂类型不同的第一掺杂类型。栅极电极排列在本体区上方且通过栅极氧化物层而与本体区分隔开。当向栅极电极施加比晶体管的阈值电压高的电压时，晶体管接通。当晶体管接通时，施加到栅极电极的电压会使得在源极与漏极之间的本体区内形成沟道区。沟道区包括可从源极流到漏极的移动电荷载流子。为了增大晶体管的开关速度，可减小沟道区内的电阻量(被称为“漏极-源极导通电阻(drain-source onresistance)”或RDS(on))。然而，存在会影响RDS(on)的值的许多因素，例如沟道区面积、源极及漏极中的扩散电阻、衬底的电阻及晶体管的温度。对这些因素进行调整来增大晶体管电流可能会带来其他功能及设计挑战。
在本公开中，提供一种新的晶体管设计，所述新的晶体管设计利用SOI衬底来产生具有较低的RDS(on)的晶体管，由此产生具有较高的电流及较快的开关速度的晶体管。所述新的晶体管设计具有多个沟道区，所述多个沟道区彼此电并联地排列且由相同的阈值电压表征，且因此，会在相同的条件下以相同的电流传导移动电荷载流子。由于所述各沟道区彼此电并联地排列，因此沟道区的总电阻(RDS(on))减小。有利地，这种新的晶体管设计是在不实质上增大集成电路上晶体管占用面积的大小的情况下实现的。
图1A示出了包括具有两个沟道区的晶体管的集成芯片的一些实施例的剖视图100A。
来自剖视图100A的集成芯片包括设置在半导体衬底102之上的块状氧化物104。半导体区110排列在块状氧化物104和/或经图案化的块状氧化物105之上。半导体区110被掺杂成第一掺杂类型(例如，n型或p型)。邻近半导体区110的隅角(corners)有上部源极区108a、上部漏极区108b、下部源极区108c及下部漏极区108d，上部源极区108a、上部漏极区108b、下部源极区108c及下部漏极区108d具有与第一掺杂类型不同的第二掺杂类型。上部源极区108a通过半导体区110的上部部分而在横向上与上部漏极区108b间隔开。下部漏极区108d通过半导体区110的下部部分而在横向上与下部源极区108c间隔开。下部源极区108c及下部漏极区108d可具有底表面，所述底表面排列在一个或多个层间介电(inter-layer dielectric，ILD)层120之上且接触所述一个或多个层间介电层120。在一些实施例中，上部源极区108a连接到下部源极区108c，且上部漏极区108b连接到下部漏极区108d。
在半导体区110的上部部分上方有栅极氧化物112，且在栅极氧化物112上方有栅极电极114。在一些实施例中，举例来说，块状氧化物104与栅极氧化物112具有相同的厚度且由相同的材料(例如，高介电常数介电质(high-k dielectric)或二氧化硅)制成。另外，在一些实施例中，举例来说，半导体衬底102与栅极电极114由相同的材料(例如，导电金属或经掺杂的多晶硅)制成。然而，在其他实施例中，块状氧化物104实质上比栅极氧化物112厚。另外，在其他实施例中，半导体衬底102可由经掺杂的单晶硅制成，而栅极电极114由经掺杂的多晶硅或导电金属制成。因此，在半导体衬底102、以及块状氧化物104的一部分内可设置有背侧栅极电极103。背侧栅极电极103可由与栅极电极114相同的材料(例如，经掺杂的多晶硅或导电金属)组成。背侧栅极电极103可延伸到块状氧化物104的一部分中以使位于第一沟道区116a下方的经图案化的块状氧化物105的厚度与栅极氧化物112相同。
在半导体区110的下部部分内有第一沟道区116a且在半导体区110的上部部分内有第二沟道区116b。第一沟道区116a可在结构上平行于第二沟道区116b。第一沟道区116a与第二沟道区116b的长度可相等。第一沟道区116a及第二沟道区116b是当晶体管导通时会有移动电荷载流子在其中流动的区。
第一金属接触件118a电耦合到上部源极区108a及下部源极区108c；且第二金属接触件118b电耦合到上部漏极区108b及下部漏极区108d。在一些实施例(未示出)中，在金属接触件118a、118b与上部源极区108a、上部漏极区108b、下部源极区108c、下部漏极区108d之间的界面处具有硅化物层。金属接触件118a、118b可具有与栅极电极114实质上齐平的上表面。金属接触件118a、118b通过所述一个或多个层间介电层120而与栅极电极114及背侧栅极电极103间隔开。接触通孔122将上部源极区108a、上部漏极区108b、下部源极区108c、下部漏极区108d、栅极电极114及背侧栅极电极103耦合到其各自的电压线。接触通孔122嵌置在所述一个或多个层间介电层120中。
栅极电极114及背侧栅极电极103电耦合到栅极电压线VG。电路耦合到栅极电压线VG以同时向栅极电极114与背侧栅极电极103提供相同的电压。上部源极区108a及下部源极区108c电耦合到源极电压线VS。上部漏极区108b及下部漏极区108d电耦合到漏极电压线VD。为使来自剖视图100A的集成芯片中的晶体管以较低的RDS(on)运转，将实施例设计成使第一沟道区116a与第二沟道区116b由相同的阈值电压表征。因此，当经由电路向栅极电压线VG施加比阈值电压大的电压时，剖视图100A的集成芯片中的晶体管导通，使得第一沟道区116a及第二沟道区116b允许移动电荷载流子分别从下部源极区108c、上部源极区108a移动到下部漏极区108d、上部漏极区108b。剖视图100A中的实施例的优点源自于：存在实质上电并联地排列的第一沟道区116a与第二沟道区116b，此使RDS(on)总体减小且因此使晶体管开关速度提高。
图1B示出了包括具有两个沟道区的晶体管的集成芯片的剖视图100B的附加实施例。剖视图100B的集成芯片包括与来自剖视图100A的集成芯片相同的特征，但具有不同的特性。在一些实施例中，下部源极区108c与下部漏极区108d可通过块状氧化物104而与半导体衬底102分隔开。在一些实施例中，残余源极/漏极区域(residual source/drain area)109可将上部源极区108a连接到下部源极区108c并将上部漏极区108b连接到下部漏极区108d。在其他实施例(未示出)中，可省略残余源极/漏极区域109以使上部源极区108a、上部漏极区108b通过半导体区110而分别与下部源极区108c、下部漏极区108d间隔开。上部源极区108a可在垂直方向上与下部源极区108c间隔开，且上部漏极区108b可在垂直方向上与下部漏极区108d间隔开。在一些实施例中，上部源极区108a、上部漏极区108b的长度和/厚度可分别小于下部源极区108c、下部漏极区108d的长度和/厚度。在许多实施例中，第一沟道区116a与第二沟道区116b的长度实质上相同。此可通过调整下部源极区108c及下部漏极区108d的位置来实现。下部源极区108c及下部漏极区108d可通过向半导体区110中进行离子植入来形成。可对离子植入角进行微调以减小第一沟道区116a的长度。因此，残余源极/漏极区域109可在圆形隅角处连接到下部源极区108c及下部漏极区108d。在一些实施例中，残余源极/漏极区域109的厚度可与下部源极区108c及下部漏极区108d相同。
在许多实施例中，举例来说，块状氧化物104与栅极氧化物112具有相同的厚度且由相同的材料(例如，高介电常数介电质或二氧化硅)制成。另外，在一些实施例中，举例来说，半导体衬底102与栅极电极114由相同的材料(例如，导电金属或经掺杂的多晶硅)制成。因此，栅极电压线VG耦合到半导体衬底102及栅极电极114。
由于剖视图100B的集成芯片中的晶体管的这些设计特征，当向栅极电压线VG施加的电压高于阈值电压时，第一沟道区116a与第二沟道区116b二者均包括移动电荷载流子，所述移动电荷载流子分别以相同的电流从下部源极区108c、上部源极区108a移动到下部漏极区108d、上部漏极区108b以使晶体管导通。在许多实施例中，沟道区116a、116b可具有介于约0.3微米与约2微米之间范围内的长度。在一些实施例中，阈值电压可介于约5伏与约8伏之间的范围内。
图1C示出了包括具有两个沟道区的晶体管的集成芯片的剖视图100C的附加实施例。
剖视图100C的集成芯片包括与剖视图100B的集成芯片相同的特征并具有额外的特征(设置在半导体衬底102内的背侧栅极电极103)。举例来说，背侧栅极电极103由与栅极电极114相同的材料(例如，经掺杂的多晶硅或导电金属)组成。背侧栅极电极103可由与半导体衬底102不同的材料组成。半导体衬底102可由例如多晶硅组成。在剖视图100C中，块状氧化物104比栅极氧化物112厚。背侧栅极电极103可延伸到块状氧化物104的位于第一沟道区116a下方的一部分中以使经图案化的块状氧化物105的厚度与栅极氧化物112相同。
图1D示出了包括具有两个沟道区的晶体管的集成芯片的剖视图100D的附加实施例。
剖视图100D的集成芯片包括与剖视图100B的集成芯片相同的特征，但具有不同的特性。在剖视图100D中，块状氧化物104比栅极氧化物112厚。在一些实施例中，上部源极区108a、上部漏极区108b、下部源极区108c、下部漏极区108d是通过垂直离子植入形成的，使得第一沟道区116a比第二沟道区116b长。另外，残余源极/漏极区域109可具有比下部源极区108c及下部漏极区108d小的厚度。在许多实施例中，举例来说，半导体衬底102可由经掺杂的单晶硅制成，而栅极电极114由经掺杂的多晶硅或导电金属制成。在其他实施例中，半导体衬底102可由与栅极电极114相同的材料组成。另外，在其他实施例(未示出)中，可在一些实施例中对图1D所示元件的几何形状和/或材料(例如，半导体区110的几何形状)进行微调以使第一沟道区116a与第二沟道区116b具有相同的阈值电压。
图2A示出了包括具有四个沟道区的晶体管的集成芯片的一些实施例的剖视图200A。
剖视图200A的集成芯片包括半导体衬底102，半导体衬底102包括背侧栅极电极103。在背侧栅极电极103之上排列有块状氧化物104。在块状氧化物104上方排列有半导体区110。在半导体区110的第一下部隅角中设置有下部漏极区108d，且在半导体区110的第二下部隅角中设置有下部源极区108c。下部漏极区108d通过第一沟道区116a而与下部源极区108c间隔开。第一沟道区116a处于半导体区110内且上覆于块状氧化物104上。在下部漏极区108d上方有上部源极区108a。第三沟道区116c处于半导体区110内且将上部源极区108a与下部漏极区108d分隔开。上部漏极区108b通过第二沟道区116b而在横向上与上部源极区108a间隔开且通过第四沟道区116d而在垂直方向上与下部源极区108c间隔开。在许多实施例中，第一沟道区116a、第二沟道区116b、第三沟道区116c及第四沟道区116d实质上具有相同的长度。在许多实施例中，沟道区116a到沟道区116d可具有实质上彼此相等且介于约0.3微米与约2微米之间范围内的长度。
邻近第二沟道区116b、第三沟道区116c及第四沟道区116d具有栅极氧化物112。在许多实施例中，举例来说，栅极氧化物112与块状氧化物104由相同的材料(例如，二氧化硅或高介电常数介电质)制成且具有相同的厚度。在上部源极区108a及下部漏极区108d旁边排列有第一外围栅极电极115a且第一外围栅极电极115a通过栅极氧化物112而与半导体区110分隔开。在上部漏极区108b及下部源极区108c旁边排列有第二外围栅极电极115b且第二外围栅极电极115b通过栅极氧化物112而与半导体区110分隔开。在第二沟道区116b上方排列有栅极电极114且栅极电极114通过栅极氧化物112而与半导体区110间隔开。在一些实施例中，第一外围栅极电极115a、第二外围栅极电极115b及栅极电极114具有相同的厚度。另外，举例来说，栅极电极114、第一外围栅极电极115a及第二外围栅极电极115b可由相同的材料(例如，导电金属或经掺杂的多晶硅)制成。相似地，在许多实施例中，背侧栅极电极103与半导体衬底102由相同的材料(例如，单晶硅)制成。在一些实施例中，半导体衬底102及背侧栅极电极103也可由与栅极电极114以及第一外围栅极电极115a及第二外围栅极电极115b相同的材料制成。在其他实施例中，半导体衬底102及背侧栅极电极103可由经掺杂的单晶硅制成，而栅极电极114以及第一外围栅极电极115a及第二外围栅极电极115b可由经掺杂的多晶硅或导电金属制成。
金属接触件118a到118d电耦合到上部源极区108a、上部漏极区108b、下部源极区108c及下部漏极区108d。在一些实施例(未示出)中，在金属接触件118a到118d与上部源极区108a、上部漏极区108b、下部源极区108c、下部漏极区108d之间的界面处具有硅化物层。在一些实施例中，耦合到上部源极区108a及上部漏极区108b的金属接触件118a、118b具有与栅极电极114的上表面、第一外围栅极电极115a的上表面及第二外围栅极电极115b的上表面实质上共面的上表面。相似地，耦合到下部源极区108c及下部漏极区108d的金属接触件118c、118d具有与半导体衬底102的下表面及背侧栅极电极103的下表面实质上共面的下表面。
一个或多个层间介电(ILD)层120将金属接触件118a到118d与栅极电极114、第一外围栅极电极115a、第二外围栅极电极115b、半导体衬底102及背侧栅极电极103分隔开。在所述一个或多个层间介电层120内嵌置有接触通孔122。举例来说，接触通孔122可包含导电金属，例如铝、钨或铜。接触通孔122的排列方式可有所变化。举例来说，在一些实施例中，如在剖视图200A的集成芯片中一样，耦合到第一外围栅极电极115a及第二外围栅极电极115b的接触通孔122可排列为邻近耦合到上部源极区108a及上部漏极区108b的接触通孔122。在其他实施例(未示出)中，耦合到第一外围栅极电极115a及第二外围栅极电极115b的接触通孔122可与耦合到下部源极区108c及下部漏极区108d的接触通孔122相邻。
栅极电压线VG、源极电压线VS及漏极电压线VD耦合到接触通孔122中的一者或多者。上部源极区108a及下部源极区108c电耦合到源极电压线VS。相似地，上部漏极区108b及下部漏极区108d电耦合到漏极电压线VD。第一外围栅极电极115a、第二外围栅极电极115b、栅极电极114及背侧栅极电极103电耦合到栅极电压线VG。电路耦合到栅极电压线VG以同时向第一外围栅极电极115a、第二外围栅极电极115b、栅极电极114及背侧栅极电极103提供相同的电压。这些电压线可采用许多方式耦合到剖视图200A的集成芯片中的晶体管的每一个组件，例如采用衬底穿孔和/或三维集成电路管芯封装结构。剖视图200A的集成芯片内的晶体管的组件被设计成使得当经由电路向栅极电压线VG施加比阈值电压高的栅极电压时，所有四个沟道区116a到116d均被激活以使每一沟道区116a到116d中的电流被测量到为相同的，从而使晶体管的总RDS(on)减小。在一些实施例中，阈值电压可介于约5伏与约8伏之间的范围内。剖视图200A中的实施例的优点源自于：存在实质上电并联地排列的第一沟道区116a、第二沟道区116b、第三沟道区116c及第四沟道区116d、此使RDS(on)总体减小且因此使晶体管开关速度提高。
图2B示出了包括具有四个沟道区的晶体管的集成芯片的剖视图200B的附加实施例。
剖视图200B的集成芯片包括与剖视图200A的集成芯片相同的特征，但具有不同的特性。在一些实施例中，半导体衬底102由与栅极电极114、第一外围栅极电极115a及第二外围栅极电极115b不同的材料组成。因此，在一些实施例中，设置在金属接触件118c、118d之间的背侧栅极电极103可由与栅极电极114以及第一外围栅极电极115a及第二外围栅极电极115b相同的材料组成。因此，背侧栅极电极103可由与半导体衬底102不同的材料组成。有利地，当栅极电极114、第一外围栅极电极115a、第二外围栅极电极115b及背侧栅极电极103由相同的材料(例如，经掺杂的多晶硅或导电金属)组成时，所有四个沟道区116a到116d可由相同的阈值电压表征。
图3到图11示出了形成具有包括两个沟道区的晶体管的集成芯片的方法的一些实施例的剖视图300到1100。尽管图3到图11是结合方法阐述的，然而应理解，图3到图11所公开的结构并非仅限于这种方法，而是可单独作为独立于所述方法之外的结构。
如图3所示剖视图300所示，提供绝缘体上硅衬底，所述绝缘体上硅衬底包括设置在块状氧化物104之上的半导体材料310，块状氧化物104设置在半导体衬底102之上。可执行附加处理步骤来对常常由单晶硅制成的半导体衬底102进行掺杂。半导体材料310具有第一掺杂类型(例如，n型或p型)。
如图4所示剖视图400所示，在半导体材料310上形成位于栅极氧化物层412之上的栅极电极层414。在许多实施例中，在高温下通过热氧化工艺来生长栅极氧化物层412。栅极氧化物层412被形成为具有实质上均匀的厚度。在许多实施例中，使栅极氧化物层412生长成具有与块状氧化物104的厚度相等的厚度。另外，栅极氧化物层412由与块状氧化物104相同的材料制成。栅极电极层414可通过气相沉积工艺(例如，化学气相沉积(chemical vapordeposition，CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapordeposition，PE-CVD)、物理气相沉积(physical vapor deposition，PVD)或原子层沉积(atomic layer deposition，ALD))形成。栅极电极层414可包含经掺杂的多晶硅。在一些实施例中，栅极电极层414包含与半导体衬底102相同的材料。
如图5的剖视图500所示，使用经图案化的硬掩模502来对栅极电极层414及栅极氧化物层412进行图案化以形成栅极电极114及栅极氧化物112。在一些实施例中，经图案化的硬掩模502可包含通过旋转涂布工艺形成且通过光刻工艺而被图案化的感光性材料(例如，光刻胶)。在其他实施例中，经图案化的硬掩模502可包括硬掩模层(例如，氮化硅层、碳化硅层或类似层)。对栅极电极层414的未被覆盖的部分以及栅极氧化物层412的未被覆盖的部分进行蚀刻(例如，湿蚀刻或干蚀刻)以留下栅极电极114及栅极氧化物112。经图案化的硬掩模502的长度可介于约0.3微米到约2微米的范围内。可将经图案化的硬掩模502移除。
如图6的剖视图600所示，在栅极电极114的顶表面以及栅极电极114的侧壁及栅极氧化物112的侧壁之上沉积附加的经图案化的硬掩模602。附加的经图案化的硬掩模602覆盖半导体材料310的顶部部分。根据附加的经图案化的硬掩模602执行蚀刻，以使半导体材料310的外侧的未被覆盖的部分被移除，从而形成半导体区110。半导体区110包括第一上部隅角区604、第二上部隅角区606、第一下部隅角区608及第二下部隅角区610。第一上部隅角区604在横向上与第二上部隅角区606间隔开，且同样，第一下部隅角区608在横向上与第二下部隅角区610间隔开。第一上部隅角区604上覆于第二下部隅角区610上且在垂直方向上与第二下部隅角区610间隔开，且第二上部隅角区606上覆于第一下部隅角区608上且在垂直方向上与第一下部隅角区608间隔开。所述蚀刻在暴露出块状氧化物104之前停止，从而在半导体区110的突出的中心部分旁边留下半导体区110的外围部分。
如图7的剖视图700所示，在一些实施例中，执行垂直离子植入702和/或倾斜离子植入(angled ion implantation)704以对半导体区110的区进行掺杂。垂直离子植入702及倾斜离子植入704形成上部源极区108a、上部漏极区108b、下部源极区108c及下部漏极区108d，上部源极区108a、上部漏极区108b、下部源极区108c及下部漏极区108d具有与第一掺杂类型不同的第二掺杂类型(例如，n型或p型)。在半导体区内、在下部源极区108c与下部漏极区108d之间以及在块状氧化物104上方具有第一沟道区116a。在半导体区内、在上部源极区108a与上部漏极区108b之间以及在栅极氧化物112下方具有第二沟道区116b。进行垂直离子植入702和/或倾斜离子植入704以使第一沟道区116a的长度实质上等于第二沟道区116b的长度。第一沟道区116a的长度及第二沟道区116b的长度可介于约0.3微米与约2微米之间的范围内。倾斜离子植入704是以一角度进行，所述角度将第一沟道区116a的长度减小到更相等于第二沟道区116b的长度。因此，可形成残余源极/漏极区域109，从而将上部源极区108a连接到下部源极区108c并将上部漏极区108b连接到下部漏极区108d。如果单纯使用垂直离子植入，则可省略残余源极/漏极区域109以使上部源极区108a及上部漏极区108b分别与下部源极区108c及下部漏极区108d间隔开。
如图8的剖视图800所示，在剖视图700中的实施例之上设置一个或多个层间介电(ILD)层120(例如，氧化物、低介电常数介电质或超低介电常数介电质)。
如图9的剖视图900所示，形成源极金属接触件118a及漏极金属接触件118b。在一些实施例(未示出)中，在形成源极金属接触件118a、漏极金属接触件118b之前，可在上部源极区108a、下部源极区108c、上部漏极区108b及下部漏极区108d之上形成硅化物层。举例来说，源极金属接触件118a、漏极金属接触件118b可通过镶嵌工艺形成且可包含导电金属，例如铝或铜。源极/漏极金属接触件通过所述一个或多个层间介电层120而与栅极电极114及栅极氧化物112间隔开。
如图10的剖视图1000所示，在源极金属接触件118a、漏极金属接触件118b之上形成一个或多个层间介电层120，且在所述一个或多个层间介电层120内形成接触通孔122。可使用镶嵌工艺形成接触通孔122。在源极金属接触件118a、漏极金属接触件118b以及在栅极电极114上形成接触通孔122。
如图11的剖视图1100所示，在半导体衬底102的背侧上沉积一个或多个层间介电层120，且在所述一个或多个层间介电层120内形成电耦合到半导体衬底102的接触通孔122。为了对半导体衬底102的背侧进行图案化，所述实施例可在制造期间翻转。通过嵌置在所述一个或多个层间介电层中的接触通孔122及附加的内连金属配线，将源极金属接触件118a耦合到源极电压线VS；将漏极金属接触件118b耦合到漏极电压线VD；且将栅极电极114及半导体衬底102耦合到栅极电压线VG，如图1B的剖视图100B所示。举例来说，在半导体衬底102的背侧上沉积所述一个或多个层间介电层120之前，可对半导体衬底102进行图案化且可沿第一沟道区116a沉积背侧栅极电极103，从而形成图1C的剖视图100C所示的背侧栅极电极103。背侧栅极电极103也可延伸到块状氧化物104的一部分中以使与第一沟道区116a相邻的块状氧化物104具有和与第二沟道区116b相邻的栅极氧化物112相同的厚度。在许多实施例中，背侧栅极电极103由与栅极电极114相同的材料组成。
图12示出了形成具有包括两个沟道区的晶体管的集成芯片的方法1200的一些实施例的流程图。
尽管方法1200是以一系列动作或事件在以下进行示出及阐述，然而应理解，这些动作或事件的示出次序不应被解释为具有限制性意义。举例来说，一些动作可以不同的次序发生和/或与除本文中所示出和/或阐述的动作或事件以外的其他动作或事件同时发生。另外，可能并不要求使用所有所示出的动作来实施本文说明的一个或多个方面或实施例。另外，本文中所绘示的一个或多个动作可采用一个或多个单独的动作和/或阶段来施行。
在动作1202处，在半导体衬底之上沉积块状氧化物。
在动作1204处，在块状氧化物之上沉积具有第一掺杂类型的半导体材料，由此提供SOI晶片。图3示出与动作1202及1204对应的一些实施例的剖视图300。
在动作1206处，在半导体材料之上生长栅极氧化物层且在栅极氧化物层之上沉积栅极电极层。图4示出与动作1206对应的一些实施例的剖视图400。
在动作1208处，使用例如通过光刻得到的经图案化的硬掩模来对栅极氧化物层及栅极电极层进行图案化。图5示出与动作1208对应的一些实施例的剖视图500。
在动作1210处，在栅极氧化物及栅极电极的相对侧上蚀刻半导体材料，同时使半导体材料与栅极电极间隔开以形成半导体区。图6示出与动作1210对应的一些实施例的剖视图600。
在动作1212处，执行离子植入来对半导体区进行掺杂以形成具有与半导体区相反的掺杂类型的下部源极区、下部漏极区、上部源极区及上部漏极区。图7示出与动作1212对应的一些实施例的剖视图700。
在动作1214处，在下部源极区、下部漏极区、上部源极区及上部漏极区之上沉积一个或多个层间介电(ILD)层。图8示出与动作1214对应的一些实施例的剖视图800。
在动作1216处，对所述一个或多个层间介电层进行图案化，且在上部源极区及下部源极区上形成源极金属接触件以及在上部漏极区及下部漏极区上形成漏极金属接触件。图9示出与动作1216对应的一些实施例的剖视图900。
在动作1218处，沉积一个或多个层间介电层，且形成接触通孔。将接触通孔嵌置在所述一个或多个层间介电层中并将接触通孔耦合到源极金属接触件、漏极金属接触件及栅极电极。图10示出与动作1218对应的一些实施例的剖视图1000。
在动作1220处，在半导体衬底的底侧上沉积一个或多个层间介电层。在所述一个或多个层间介电层中嵌置接触通孔并将接触通孔耦合到半导体衬底。图11示出与动作1220对应的一些实施例的剖视图1100。
在动作1222处，增加附加的一个或多个层间介电层以及内连金属配线以使源极电压线耦合到上部源极区及下部源极区，漏极电压线耦合到上部漏极区及下部漏极区，且栅极电压线耦合到半导体衬底及栅极电极。图1B示出与动作1222对应的一些实施例的剖视图100B。
图13到图22示出了形成具有包括四个沟道区的晶体管的集成芯片的方法的一些实施例的剖视图1300到2200。尽管图13到图22是结合方法阐述的，然而应理解，图13到图22所公开的结构并非仅限于这种方法，而是可单独作为独立于所述方法之外的结构。
如图13所示剖视图1300所示，提供绝缘体上硅(SOI)衬底，所述绝缘体上硅衬底包括设置在块状氧化物层1304之上的半导体材料1310，块状氧化物层1304设置在半导体衬底102之上。在许多实施例中，半导体衬底102可包含单晶硅。在一些实施例中，可进行附加处理步骤以使得对半导体衬底102进行掺杂。半导体材料1310具有第一掺杂类型(例如，n型或p型)。
如图14的剖视图1400所示，在一些实施例中，对半导体材料1310进行图案化以形成半导体区110，其中半导体材料1310的外围部分及块状氧化物层1304的外围部分被移除，从而留下半导体区110及经图案化的块状氧化物1404。在一些实施例(未示出)中，为形成半导体区110，可使用通过光刻及蚀刻(例如，干蚀刻或湿蚀刻)形成的掩模。形成所述掩模来覆盖半导体材料1310的中心部分以使所述蚀刻将半导体材料1310的未被覆盖的外围部分移除。半导体区110包括第一上部隅角区1405、第二上部隅角区1406、第一下部隅角区1408及第二下部隅角区1410。第一上部隅角区1405在横向上与第二上部隅角区1406间隔开，且同样，第一下部隅角区1408在横向上与第二下部隅角区1410间隔开。第一上部隅角区1405上覆于第一下部隅角区1408上且在垂直方向上与第一下部隅角区1408间隔开，且第二上部隅角区1406上覆于第二下部隅角区1410上且在垂直方向上与第二下部隅角区1410间隔开。接着，在半导体区110之上生长栅极氧化物层1412。栅极氧化物层1412覆盖半导体区110的顶表面、半导体区110的侧壁及经图案化的块状氧化物1404的侧壁。在许多实施例中，栅极氧化物层1412由与经图案化的块状氧化物1404相同的材料制成且被生长到与经图案化的块状氧化物1404相同的厚度。常常以高温通过热氧化工艺生长栅极氧化物层1412。
如图15的剖视图1500所示，在栅极氧化物层1412之上沉积共形栅极电极层1514。共形栅极电极层1514可包含经掺杂的多晶硅。在一些实施例中，共形栅极电极层1514可包含与半导体衬底102相同的掺杂浓度。
如图16的剖视图1600所示，在共形栅极电极层1514的一些部分之上形成经图案化的掩模1602以蚀刻(例如，湿蚀刻或干蚀刻)共形栅极电极层1514及栅极氧化物层1412来形成栅极电极114及栅极氧化物112。栅极电极114及栅极氧化物112沿半导体区110的侧壁具有外围部分且沿半导体区110的中心顶表面具有中心部分。
如图17的剖视图1700所示，形成上部源极区108a及上部漏极区108b。通过对位于栅极氧化物112的外围部分与中心部分之间的半导体区110的被暴露出的部分进行掺杂而形成上部源极区108a及上部漏极区108b。上部源极区108a及上部漏极区108b具有与半导体区110的第一掺杂类型相反的第二掺杂类型。上部源极区108a、上部漏极区108b可通过垂直离子植入技术形成。上部源极区、上部漏极区可因由垂直离子植入技术引起的残余效果而在栅极氧化物112下面部分地延伸。位于半导体区110内且位于栅极氧化物112的中心部分下方的上部源极区108a与上部漏极区108b之间的空间是第二沟道区116b所在之处。第二沟道区116b的长度可介于约0.3微米与约2微米之间的范围内。
如图18的剖视图1800所示，在上部源极区108a及上部漏极区108b之上在一个或多个层间介电(ILD)层120内形成金属接触件118。金属接触件118是导电的且可通过镶嵌工艺形成。金属接触件118的上表面、栅极电极114的上表面、及所述一个或多个层间介电层120的上表面可实质上共面。金属接触件118通过所述一个或多个层间介电层120而与栅极电极140间隔开。
如图19的剖视图1900所示，将SOI衬底翻转，且对半导体衬底102的背侧进行图案化以形成背侧栅极电极103。在半导体衬底之上形成经图案化的掩模1902，且执行蚀刻(例如，湿蚀刻或干蚀刻)以使背侧栅极电极103实质上上覆于栅极氧化物112的中心部分上。进一步对经图案化的块状氧化物层1404与半导体衬底102一起进行图案化以形成块状氧化物104。
如图20的剖视图2000所示，将经图案化的掩模1902移除，且在半导体区110内形成下部源极区108c及下部漏极区108d。与上部源极区108a、上部漏极区108b的形成相似，可执行垂直离子植入工艺以形成下部源极区108c、下部漏极区108d。正如同第二沟道区116b一样，位于半导体区110内且位于块状氧化物104下方的下部源极区108c与下部漏极区108d之间的空间是第一沟道区116a所在之处。下部源极区108c被形成为上覆于上部漏极区108b上，且下部漏极区108d被形成为上覆于上部源极区108a上。第三沟道区116c是由位于栅极氧化物112的外围部分旁边且位于半导体区110内的上部源极区108a与下部漏极区108d之间的空间界定的。第四沟道区116d是由位于栅极氧化物112的不同的外围部分旁边且位于半导体区110内的上部漏极区108b与下部源极区108c之间的空间界定的。沟道区116a到116d具有实质上彼此相等的长度。每一个沟道区116a到116d的长度可介于约0.3微米与2微米之间的范围内。
如图21的剖视图2100所示，沿半导体衬底102的侧壁、背侧栅极电极103的侧壁、块状氧化物104的侧壁及栅极氧化物112的侧壁设置一个或多个层间介电层120，同时使下部源极区108c、下部漏极区108d的一些部分不被覆盖。
如图22的剖视图2200所示，在所述一个或多个层间介电层120与下部源极区108c、下部漏极区108d之间的空间内沉积金属接触件118，以使下部源极区108c及下部漏极区108d分别耦合到金属接触件118中的一者。通过嵌置在所述一个或多个层间介电层120中的接触通孔122及附加的内连金属配线，将上部源极区108a及下部源极区108c耦合到源极电压线VS；将上部漏极区108b及下部漏极区108d耦合到漏极电压线VD；且将栅极电极114及背侧栅极电极103耦合到栅极电压线VG，如图2A的剖视图200A所示。在一些实施例中，
图22处的背侧栅极电极103由与栅极电极114不同的材料组成。在上述实施例中，在背侧栅极电极103及半导体衬底102之上沉积所述一个或多个层间介电层120之前，背侧栅极电极103可被移除且被替换为与栅极电极114具有相同材料的背侧栅极电极103。所得实施例示出在图2B的剖视图200B中。在移除背侧栅极电极103期间，也可移除块状氧化物104的一些部分以使块状氧化物104的厚度等于栅极氧化物112的厚度。
图23示出了形成具有包括四个沟道区116a到116b的晶体管的集成芯片的方法2300的一些实施例的流程图。
尽管方法2300是以一系列动作或事件在以下进行示出及阐述，然而应理解，这些动作或事件的示出次序不应被解释为具有限制性意义。举例来说，一些动作可以不同的次序发生和/或与除本文中所示出和/或阐述的动作或事件以外的其他动作或事件同时发生。另外，可能并不要求使用所有所示出的动作来实施本文说明的一个或多个方面或实施例。另外，本文中所绘示的一个或多个动作可采用一个或多个单独的动作和/或阶段来施行。
在动作2302处，在半导体衬底之上沉积块状氧化物层。
在动作2304处，在块状氧化物层之上沉积半导体材料。所述半导体材料具有第一掺杂类型。图13示出与动作2302及2304对应的一些实施例的剖视图1300。
在动作2306处，执行蚀刻以移除半导体材料的相对侧的外侧部分来形成半导体区。
在动作2308处，在半导体区之上生长栅极氧化物层。图14示出与动作2306及2308对应的一些实施例的剖视图1400。
在动作2310处，在栅极氧化物层之上沉积栅极电极层。图15示出与动作2310对应的一些实施例的剖视图1500。
在动作2312处，使用例如通过光刻得到的掩模来对栅极氧化物层及栅极电极层进行图案化。在图案化之后，在半导体区之上且沿半导体区的外侧壁分别留下中心栅极电极及外围栅极电极。图16示出与动作2312对应的一些实施例的剖视图1600。
在动作2314处，执行离子植入以对中心栅极电极与外围栅极电极之间的半导体区进行掺杂来形成上部源极区及上部漏极区。上部源极区及上部漏极区具有与半导体区相反的掺杂类型。图17示出与动作2314对应的一些实施例的剖视图1700。
在动作2316处，形成金属接触件，所述金属接触件嵌置在一个或多个层间介电(ILD)层中且耦合到上部源极区及上部漏极区。图18示出与动作2316对应的一些实施例的剖视图1800。
在动作2318处，使用例如通过光刻得到的掩模来对半导体衬底的底侧进行图案化。在图案化之后，半导体衬底的中心部分形成背侧栅极电极。图19示出与动作2318对应的一些实施例的剖视图1900。
在动作2320处，执行离子植入以对背侧栅极电极的相对侧上的半导体区进行掺杂来形成下部源极区及下部漏极区。下部源极区及下部漏极区具有与半导体区相反的掺杂类型。图20示出与动作2320对应的一些实施例的剖视图2000。
在动作2322处，形成嵌置在一个或多个层间介电层中的金属接触件。所述金属接触件耦合到下部源极区及下部漏极区。图21到图22示出与动作2322对应的一些实施例的剖视图2100、2200。
在动作2324处，增加附加的一个或多个层间介电层、接触通孔以及内连金属配线以使源极电压线耦合到上部源极区及下部源极区，漏极电压线耦合到上部漏极区及下部漏极区，且栅极电压线耦合到中心栅极电极、外围栅极电极及背侧栅极电极。图2A示出与动作2324对应的一些实施例的剖视图200A。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。
因此，本公开涉及一种新的结构及制造晶体管的方法，以通过具有多于一个沟道区来减小当晶体管导通时从源极到漏极的电阻(RDS(on))。
因此，在一些实施例中，本公开涉及一种半导体装置，所述半导体装置包括：块状氧化物，设置在半导体衬底之上；半导体区，设置在所述块状氧化物之上；下部源极区及下部漏极区，其中所述下部源极区及所述下部漏极区位于所述块状氧化物上方且直接接触所述块状氧化物，并且所述下部源极区与所述下部漏极区通过所述半导体区的下部部分在横向上间隔开；上部源极区及上部漏极区，所述上部源极区耦合到所述下部源极区，所述上部漏极区耦合到所述下部漏极区，其中所述上部源极区通过所述半导体区的上部部分而在横向上与所述上部漏极区间隔开，且其中所述上部源极区及所述上部漏极区在垂直方向上与所述下部源极区及所述下部漏极区间隔开；栅极氧化物，设置在所述半导体区的所述上部部分之上；栅极电极，设置在所述栅极氧化物正上方，所述栅极电极耦合到所述半导体衬底；第一沟道区，位于所述半导体区的所述下部部分内、所述块状氧化物上方以及所述下部源极区与所述下部漏极区之间；以及第二沟道区，位于所述半导体区的所述上部部分内、所述栅极氧化物下方以及所述上部源极区与所述上部漏极区之间，其中所述第二沟道区平行于所述第一沟道区。
在一些实施例中，所述块状氧化物与所述栅极氧化物具有相同的厚度且由相同的材料制成。在一些实施例中，所述下部源极区及所述上部源极区排列在所述半导体区的第一侧上，且其中所述下部漏极区及所述上部漏极区排列在所述半导体区的第二侧上，所述第二侧在横向上与所述第一侧间隔开。在一些实施例中，所述第一沟道区与所述第二沟道区具有相同的长度。在一些实施例中，所述下部漏极区及所述上部源极区排列在所述半导体区的第一侧上且其中所述下部源极区及所述上部漏极区排列在所述半导体区的第二侧上，所述第二侧在横向上与所述第一侧间隔开。在一些实施例中，所述半导体装置还包括：第一外围栅极电极，邻近所述上部源极区及所述下部漏极区排列且通过第一外围栅极氧化物而与所述半导体区间隔开，其中所述第一外围栅极电极耦合到所述栅极电极；第二外围栅极电极，邻近所述上部漏极区及所述下部源极区排列且通过第二外围栅极氧化物而与所述半导体区间隔开，其中所述第二外围栅极电极耦合到所述栅极电极；第三沟道区，在所述第一外围栅极氧化物旁边位于所述半导体区内以及位于所述上部源极区与所述下部漏极区之间；以及第四沟道区，位于所述第二外围栅极氧化物旁边以及所述上部漏极区与所述下部源极区之间，其中所述第四沟道区平行于所述第三沟道区，且其中所述第四沟道区垂直于所述第一沟道区。在一些实施例中，所述第一沟道区、所述第二沟道区、所述第三沟道区及所述第四沟道区具有相同的长度。在一些实施例中，所述块状氧化物、所述栅极氧化物、所述第一外围栅极氧化物及所述第二外围栅极氧化物具有相同的厚度且由相同的材料制成。在一些实施例中，所述栅极电极、所述第一外围栅极电极及所述第二外围栅极电极具有相同的厚度。
在其他实施例中，本公开涉及一种半导体装置，所述半导体装置包括：块状氧化物，设置在半导体衬底之上；半导体区，设置在所述块状氧化物之上；下部源极区及下部漏极区，其中所述下部源极区与所述下部漏极区位于所述块状氧化物上方且通过所述半导体区的下部部分间隔开；第一沟道区，位于所述块状氧化物上方、所述半导体区的所述下部部分内以及在横向上位于所述下部源极区与所述下部漏极区之间；栅极氧化物，设置在所述半导体区的上部部分之上，其中第二沟道区位于所述栅极氧化物下方以及所述半导体区的所述上部部分内；栅极电极，设置在所述栅极氧化物正上方，所述栅极电极耦合到所述半导体衬底；上部源极区，耦合到所述下部源极区，上覆于所述下部漏极区上，且通过所述半导体区内的第三沟道区而在垂直方向上与所述下部漏极区间隔开；上部漏极区，耦合到所述下部漏极区，上覆于所述下部源极区上，且通过所述半导体区内的第四沟道区而在垂直方向上与所述下部源极区间隔开，其中所述上部源极区通过所述第二沟道区而在横向上与所述上部漏极区间隔开；第一外围栅极电极，邻近所述上部源极区及所述下部漏极区排列且通过第一外围栅极氧化物而与所述第三沟道区间隔开，其中所述第一外围栅极电极耦合到所述半导体衬底；以及第二外围栅极电极，邻近所述上部漏极区及所述下部源极区排列且通过第二外围栅极氧化物而与所述第四沟道区间隔开，其中所述第二外围栅极电极耦合到所述半导体衬底。
在一些实施例中，所述第一沟道区、所述第二沟道区、所述第三沟道区及所述第四沟道区具有相同的长度。在一些实施例中，所述块状氧化物、所述栅极氧化物、所述第一外围栅极氧化物及所述第二外围栅极氧化物具有相同的厚度且由相同的材料制成。在一些实施例中，所述半导体衬底、所述栅极电极、所述第一外围栅极电极及所述第二外围栅极电极由相同的材料制成。在一些实施例中，介电层使所述半导体衬底、所述栅极电极、所述第一外围栅极电极及所述第二外围栅极电极彼此电绝缘。
在又一些实施例中，本公开涉及一种形成半导体装置的方法，所述方法包括：提供绝缘体上硅衬底，所述绝缘体上硅衬底包括设置在半导体衬底之上的块状氧化物及设置在所述块状氧化物之上的半导体区，其中所述半导体区具有第一掺杂类型；在所述半导体区之上形成栅极氧化物层；在所述栅极氧化物层之上形成栅极电极层；使用掩模对所述栅极氧化物层及所述栅极电极层进行图案化，从而在所述半导体区的第一部分之上留下栅极氧化物及栅极电极且使所述半导体区的第二部分不被覆盖，其中所述半导体区包括隅角区，所述隅角区包括在横向上间隔开的第一上部隅角区和第二上部隅角区以及在横向上间隔开的第一下部隅角区和第二下部隅角区，且其中所述第一下部隅角区及所述第二下部隅角区通过所述半导体区的一些部分而在垂直方向上与所述第一上部隅角区及所述第二上部隅角区间隔开；执行离子植入来对所述半导体区的各所述隅角区进行掺杂，使得各所述隅角区具有与所述第一掺杂类型不同的第二掺杂类型，其中执行所述离子植入形成分别排列在所述第一上部隅角区、所述第二上部隅角区、所述第一下部隅角区及所述第二下部隅角区中的上部源极区、上部漏极区、下部漏极区及下部源极区；将所述下部源极区及所述上部源极区耦合到源极电压线；将所述下部漏极区及所述上部漏极区耦合到漏极电压线；以及将所述半导体衬底及所述栅极电极耦合到栅极电压线。
在一些实施例中，所述半导体区包括：外围部分，在所述块状氧化物上方位于第一高度处；以及突出的中心部分，位于所述外围部分之间，其中所述突出的中心部分位于比所述第一高度高的第二高度处。在一些实施例中，所述隅角区位于所述半导体区的所述突出的中心部分内；所述第一上部隅角区上覆于所述第二下部隅角区上；以及所述第二上部隅角区上覆于所述第一下部隅角区上。在一些实施例中，在生长所述栅极氧化物层之后，所述栅极氧化物层覆盖所述半导体区的外侧壁及上表面。在一些实施例中，在对所述栅极氧化物层及所述栅极电极层进行图案化之后，第一外围栅极电极及第二外围栅极电极留存下来且沿所述半导体区的所述外侧壁排列，其中所述第一外围栅极电极及所述第二外围栅极电极分别通过第一外围栅极氧化物及第二外围栅极氧化物而与所述半导体区间隔开。在一些实施例中，所述第一上部隅角区上覆于所述第一下部隅角区上；以及所述第二上部隅角区上覆于所述第二下部隅角区上。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种半导体装置，其特征在于，包括：
块状氧化物，设置在半导体衬底之上；
半导体区，设置在所述块状氧化物之上；
下部源极区及下部漏极区，其中所述下部源极区及所述下部漏极区位于所述块状氧化物上方且直接接触所述块状氧化物，并且所述下部源极区与所述下部漏极区通过所述半导体区的下部部分在横向上间隔开；
上部源极区及上部漏极区，所述上部源极区耦合到所述下部源极区，所述上部漏极区耦合到所述下部漏极区，其中所述上部源极区通过所述半导体区的上部部分而在横向上与所述上部漏极区间隔开，且其中所述上部源极区及所述上部漏极区在垂直方向上与所述下部源极区及所述下部漏极区间隔开；
栅极氧化物，设置在所述半导体区的所述上部部分之上；
栅极电极，设置在所述栅极氧化物正上方，所述栅极电极耦合到所述半导体衬底；
第一沟道区，位于所述半导体区的所述下部部分内、所述块状氧化物上方以及所述下部源极区与所述下部漏极区之间；以及
第二沟道区，位于所述半导体区的所述上部部分内、所述栅极氧化物下方以及所述上部源极区与所述上部漏极区之间，其中所述第二沟道区平行于所述第一沟道区。
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