CN109300780B - 形成栅极接触点的导电间隔物的方法以及所得装置 - Google Patents

形成栅极接触点的导电间隔物的方法以及所得装置 Download PDF

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CN109300780B
CN109300780B CN201810825723.3A CN201810825723A CN109300780B CN 109300780 B CN109300780 B CN 109300780B CN 201810825723 A CN201810825723 A CN 201810825723A CN 109300780 B CN109300780 B CN 109300780B
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conductive
gate contact
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CN109300780A (zh
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谢瑞龙
拉尔斯·W·赖柏曼
B·C·保罗
丹尼尔·恰尼莫盖姆
尼格尔·G·凯夫
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GlobalFoundries US Inc
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Abstract

本发明涉及形成栅极接触点的导电间隔物的方法以及所得装置，其中，一种方法包括在半导体衬底的第一区域上方形成第一栅极结构。邻近该第一栅极结构形成第一侧壁间隔物。凹入该第一栅极结构及该第一侧壁间隔物，以定义第一栅极接触空腔。在该第一栅极接触空腔中形成第二侧壁间隔物。在该第一栅极接触空腔中形成第一导电栅极接触点。移除该第二侧壁间隔物，以定义第一间隔物空腔。在该第一间隔物空腔中形成导电材料，以形成接触该第一导电栅极接触点的第一导电间隔物。

Description

形成栅极接触点的导电间隔物的方法以及所得装置
技术领域
本揭示内容通常涉及集成电路的制造，尤其涉及形成栅极接触点的导电间隔物的各种方法以及所得装置。
背景技术
在例如微处理器、储存装置等当前的集成电路中，在有限的芯片面积上设置并运行有大量的电路元件，尤其是场效应晶体管(field effect transistor；FET)。FET具有各种不同的配置，例如平面装置、FinFET装置、纳米线装置等。这些FET装置通常以开关模式操作，也就是说，这些装置呈现高导通状态(开状态；on-state)和高阻抗状态(关状态；off-state)。场效应晶体管的状态由栅极电极控制，在施加适当的控制电压后，该栅极电极控制在漏极区与源极区之间所形成的沟道区的电导率。
为提升FET的操作速度并增加集成电路装置上的FET的密度，多年来，装置设计人员已大幅降低了FET的物理尺寸，尤其晶体管装置的沟道长度。由于晶体管装置的尺寸降低，因此随着装置的更新换代增加了电路组件的操作速度，并且在此期间也增加了此类产品中的“封装密度”，也就是每单位面积的晶体管装置的数目。通常，由于当前集成电路中的大量电路元件以及所需的复杂布局，因此无法在制造该些电路元件的同一装置层级内建立各电路元件的电性连接或“线路布置”。因此，在形成于该产品的该装置层级上方的一个或多个额外堆叠的所谓“金属化层”中形成各种电性连接，构成该集成电路产品的总体线路图案。这些金属化层通常由绝缘材料层以及形成于该材料层中的导电金属线或导电过孔组成。一般来说，该些导线提供层级内部的电性连接，而该导电过孔提供不同层级金属线之间的层级间连接或垂直连接。这些导线及导电过孔可由各种不同材料例如铜组成，具有适当的阻挡层等。集成电路产品中的第一金属化层通常被称为“M1”层。而用以在该M1层与下方层级导电结构之间建立电性连接的导电过孔(下面将作更详细解释)通常被称为“V0”过孔。位于这些金属化层中的导线及导电过孔通常由铜组成，且它们通过已知的镶嵌或双镶嵌技术形成于绝缘材料层中。
图1A显示由形成于半导体衬底12中及上方的多个晶体管装置11组成的示例集成电路产品10的横剖视图。图1B显示单个晶体管装置11的简单平面视图。这些附图显示多个所谓“CA接触”结构14，其用以建立与装置11的简单示意源极/漏极区20的电性连接；以及栅极接触结构点16，其有时被称为“CB接触”结构，经形成以建立与该晶体管装置的栅极结构的电性接触点。如图1B中所示，CB栅极接触点16通常垂直位于围绕装置11的隔离材料13上方，也就是，CB栅极接触点16通常不位于衬底12中所定义的主动区上方，但它可能在一些先进架构中。
请参照图1A至1B，晶体管11包括示例栅极结构22(也就是栅极绝缘(介电)层22A及栅极电极22B)、栅极覆盖层24、侧壁间隔物26以及简单示意的源极/漏极区20。如上所述，在流程的此点，在衬底12中也已形成隔离区13。在图1A中所示的制造点，在衬底12上方已形成绝缘材料层30A、30B，也就是层间介电材料。其它材料层例如接触蚀刻停止层及类似物未显示于附图中。附图中还显示示例抬升式外延源极/漏极(S/D)区32以及通常包括所谓“沟槽硅化物”(trench silicide；TS)结构36的源极/漏极接触结构34。CA接触结构14可为分立接触元件的形式，也就是从上方观看时具有通常类似方形的形状(如图1B中所示)或圆柱状的一个或多个形成于层间介电材料中的个别接触塞。在其它应用中(图1B中未显示)，CA接触结构14也可为线型特征，其接触下方的线型特征例如接触源极/漏极区20的TS结构36(TS结构36是通常沿平行于栅极结构22的方向贯穿源极/漏极区20上的整个主动区的线型特征)。TS结构36、CA接触点14及CB接触点16在业内都被视为装置级接触点。
在一个具体实施例中，形成TS结构36、CA接触点14及CB接触点16的流程可为如下所述。在沉积第一绝缘材料层30A以后，在第一绝缘材料层30A中形成TS开口(opening)，以暴露部分的下方源极/漏极区20。随后，穿过该TS开口形成传统金属硅化物，接着在该金属硅化物区域上形成钨(未单独显示)，并对栅极覆盖层24的顶部向下执行化学机械抛光(chemical mechanical polishing；CMP)制程。接着，沉积第二绝缘材料层30B，并在第二绝缘材料层30B中形成针对CA接触点14的接触开口，以暴露位于源极/漏极区20上方的下方钨金属化的部分。接着，在掩蔽针对CA接触点14的开口期间，在第二绝缘材料层30B中并穿过栅极覆盖层24形成针对CB接触16的开口，以暴露栅极电极22B的部分。通常，CB接触点16可为圆形或方形塞的形式。随后，通过执行一个或多个共同金属沉积及CMP制程操作(利用第二绝缘材料层30B作为抛光停止层以移除位于该些接触开口外部的多余导电材料)，在第二绝缘材料层30B中的相应开口中形成导电CA接触点14及导电CB接触点16。CA接触点14及CB接触点16通常包含均匀金属体，例如钨，且还可包括位于该均匀金属体与绝缘材料层30B之间的一个或多个金属阻挡层(未显示)。如上所述，源极/漏极接触结构34、CA接触点14及CB接触点16在业内都被视为装置层级接触点。
请继续参照图1A，其显示IC产品10的多层级金属化系统的部分。更具体地说，图1A显示该多层级金属化系统的所谓M1金属化层的示例。该M1金属化层形成于绝缘材料层38例如低k绝缘材料中。该M1金属化层通常包括多条根据需求布线横跨IC产品10的金属线42。形成多个导电过孔-所谓V0过孔40，以在该M1金属化层与该装置层级接触点-CA接触点14及CB接触点16之间建立电性连接。金属化线42通常通过横跨大体整个衬底的绝缘材料层38中形成长的连续沟槽来形成。随后，用一种或多种导电材料填充这些沟槽，以及执行一个或多个化学机械抛光(CMP)制程以移除该些沟槽外部的多余导电材料。
图1B显示示例晶体管装置11的简单平面视图，仅显示装置11的装置层级接触点-CA接触点14及CB接触点16-以及它们的相对装置。图1B中还显示栅极覆盖层24、侧壁间隔物26以及形成于源极/漏极区20上方的沟槽硅化物结构36。如上所述，整个CB栅极接触点16垂直位于围绕产品10的隔离区13上方，也就是，CB栅极接触点16不位于衬底12中所定义的主动区上方。CB栅极接触点16通常位于隔离区13上方，以避免或减少在CB接触点16与TS结构36之间形成电性短路的可机会，也就是，依据试图防止此类电性短路的各种设计规则，这两个结构之间所必须保持最小间距43。遗憾的是，CB接触点16仅位于隔离区13上方的要求涉及面积损失(penalty)。需要一种用以在该装置的主动区上方形成CB栅极接触16的方法，以节约集成电路产品上的宝贵绘图空间(plot space)。
本揭示内容涉及在主动区上方形成晶体管的栅极接触的各种方法以及所得装置，从而可避免或至少减轻上述问题的其中一个或多个的影响。
发明内容
下面提供本发明的简要总结，以提供本发明的一些态样的基本理解。本发明内容并非详尽概述本发明。其并非意图识别本发明的关键或重要元件或划定本发明的范围。其唯一目的在于提供一些简化形式的概念，作为后面所讨论的更详细说明的前序。
一般来说，本揭示内容涉及在栅极接触上形成导电间隔物的各种方法以及所得装置。所揭露的一种示例方法包括：除其它以外，在半导体衬底的第一区域上方形成第一栅极结构。形成邻近该第一栅极结构的第一侧壁间隔物。凹入该第一栅极结构及该第一侧壁间隔物，以定义第一栅极接触空腔(cavity)。在该第一栅极接触空腔中形成第二侧壁间隔物。在该第一栅极接触空腔中形成第一导电栅极接触点。移除该第二侧壁间隔物，以定义第一间隔物空腔。在该第一间隔物空腔中形成导电材料，以形成接触该第一导电栅极接触点的第一导电间隔物。
除此之外，另一种方法包括：在半导体衬底上方形成多个栅极结构。形成邻近各该多个栅极结构的第一侧壁间隔物。凹入该多个栅极结构及该第一侧壁间隔物，以定义第一栅极接触空腔。在该第一栅极接触空腔中形成第二侧壁间隔物。在该第一栅极接触空腔中形成第一导电栅极接触点。在该多个栅极结构的第一子集上方形成掩膜层。移除未被该掩膜层覆盖的该多个栅极结构的第二子集的该第二侧壁间隔物，以定义第一间隔物空腔。在该第一间隔物空腔中形成导电材料，以形成接触该多个栅极结构的该第二子集的该第一导电栅极接触点的第一导电间隔物。
除此之外，所揭露的一种示例装置包括：位于半导体衬底上方的第一栅极结构，邻近该第一栅极结构的第一侧壁间隔物，接触该第一栅极结构的第一导电栅极接触点，以及接触该第一侧壁间隔物以及该第一导电栅极接触点的侧壁的第一导电间隔物。
附图说明
参照下面结合附图所作的说明可理解本揭示内容，该些附图中类似的附图标记表示类似的元件，且其中：
图1A至1B显示集成电路产品的装置层级接触点及金属化层的各种示例现有技术布置；以及
图2A至2N显示本文中所揭露的用以在主动区上方形成晶体管的栅极接触点的各种新颖方法以及所得装置。
尽管本文中所揭露的发明主题容许各种修改及替代形式，但本发明主题的特定实施例以示例方式显示于附图中并在本文中作详细说明。不过，应当理解，本文中有关特定实施例的说明并非意图将本发明限于所揭露的特定形式，相反，意图涵盖落入由所附权利要求定义的本发明的精神及范围内的所有修改、等同及替代。
具体实施方式
下面说明本发明的各种示例实施例。出于清楚目的，不是实际实施中的全部特征都在本说明书中进行说明。当然，应当了解，在任意此类实际实施例的开发中，必须作大量的特定实施决定以实现开发者的特定目标，例如符合与系统相关及与商业相关的约束条件，该些决定将因不同实施而异。而且，应当了解，此类开发努力可能复杂而耗时，但其仍然是本领域的普通技术人员借助本揭示内容所执行的常规程序。
现在将参照附图来说明本发明主题。附图中示意各种结构、系统及装置仅是出于解释目的以及避免使本揭示内容与本领域技术人员已知的细节混淆，但仍包括该些附图以说明并解释本揭示内容的示例。本文中所使用的词语和词组的意思应当被理解并解释为与相关领域技术人员对这些词语及词组的理解一致。本文中的术语或词组的连贯使用并不意图暗含特别的定义，亦即与本领域技术人员所理解的通常或惯用意思不同的定义。若术语或词组意图具有特别意思，亦即不同于本领域技术人员所理解的意思，则此类特别定义会以直接明确地提供该术语或词组的特别定义的定义方式明确表示于说明书中。
本揭示内容涉及在主动区上方形成晶体管的导电栅极接触点结构(CB)的各种方法以及所得装置。本文中所揭露的方法及装置可用于制造使用各种技术例如NMOS、PMOS、CMOS等的产品，且它们可用于制造各种不同的装置，例如存储器产品、逻辑产品、ASIC等。在完整阅读本申请以后，本领域的技术人员将了解，本文中所揭露的发明可用于形成使用具有各种不同配置的晶体管装置(例如平面装置、FinFET装置、纳米线装置等)的集成电路产品。此类装置的栅极结构可通过“先栅极”或“替代栅极”制造技术形成。因此，当前揭露的发明不应当被认为限于任意特定形式的晶体管或形成晶体管装置的栅极结构的方式。当然，本文中所揭露的发明不应当被认为限于本文中所示及所述的例子。现在通过参照附图来更详细地说明本文中所揭露的方法及装置的各种示例实施例。下面所述的各种材料层可通过任意各种不同的已知技术形成，例如化学气相沉积(chemical vapor deposition；CVD)制程、原子层沉积(atomic layer deposition；ALD)制程、热生长制程、旋涂技术等。而且，本文中及附图中所使用的词语“相邻”将作广义解释，且应当被解释为涵盖一个特征实际接触另一个特征或者邻近另一个特征的情形。
图2A至2N显示本文中所揭露的用以在形成于集成电路(IC)产品100上的晶体管的栅极接触结构(CB)上形成导电间隔物的各种新颖方法，该产品可包括数个不同区域，在该些区域上方可形成CB接触点。附图包含简单平面视图，显示在附图中作各种横剖视图的位置。该平面视图显示最终将形成于半导体衬底102上方的鳍片、栅极、沟槽硅化物(TS)源极/漏极接触点、栅极接触结构(CB)，以及源极/漏极接触结构(CA)。如图2A中所示，视图X1-X1及X2-X2是沿与该装置的栅极长度方向对应的方向穿过该装置所做的剖视图。不是所有视图都显示于每张附图中。还应当注意，尽管一些附图包含产品100的平面视图，但不是剖视图中所示的制程的所有态样将会被显示于该平面视图中，以避免使附图过度复杂。
请继续参照图2A，示例IC产品100将形成于半导体衬底102中及上方。该衬底可具有不同的区域，在这些区域上方可形成CA及CB接触点，例如CB交叉耦接区104A(也就是，提供SRAM中的栅极至源极/漏极交叉耦接)、位于主动区104B(也就是，高密度区)上方的CB，以及位于STI(浅沟槽隔离)区104C(也就是，较低密度区)上方的CB。产品100可包括NMOS晶体管、PMOS晶体管或两种类型的晶体管。该晶体管可具有任意所需配置，例如FinFET装置、平面装置等。此外，各种掺杂区例如环状注入区、阱区等未显示于附图中。衬底102可具有各种配置，例如所示块体硅配置。衬底102也可具有绝缘体上硅(silicon-on-insulator；SOI)配置，其包括块体硅层、埋置绝缘层以及主动层，其中，在该主动层中及上方形成半导体装置。衬底102可由硅制成，或者它可由硅以外的材料制成。因此，术语“衬底”或“半导体衬底”应当被理解为涵盖所有半导体材料以及此类材料的所有形式。
图2A显示处于已执行数个制程操作的制造点的产品100。首先，在衬底102中形成隔离区104，以定义主动区(102X)，在该主动区可形成晶体管装置。在所示例子中，主动区102X包括多个鳍片。接着，在个别区104A、104B、104C中的衬底102上方形成多个示例栅极结构106A、106B、106C。各栅极结构106A、106B、106C包括侧壁间隔物108A、108B、108C。为形成侧壁间隔物108A、108B、108C，执行共形沉积制程，以在衬底102上方形成共形间隔物材料层，例如氮化硅，随后执行非等向性蚀刻制程。栅极结构106A、106B、106C通常分别包括栅极绝缘层(未单独显示)，例如二氧化硅或高k(k值大于10)绝缘材料，以及充当栅极电极的一个或多个导电材料层(未单独显示)，例如金属、金属合金、氮化钛、氮化钽、钨、铝、多晶硅等。侧壁间隔物108A、108B、108C通常由氮化硅形成。栅极结构106A、106B、106C可通过已知的“先栅极”或“替代栅极”制造技术形成。在形成栅极结构106A、106B、106C及间隔物108A、108B、108C以后，在该晶体管装置的源极/漏极区中形成可选的外延半导体材料110A、110B。外延半导体材料110A、110B无需在所有实施例中形成。栅极结构106A、106B、106C的物理尺寸及栅极结构106A、106B、106C的栅极间距可依据特定应用而变化。图2A中还显示介电层112，例如低k介电质或二氧化硅，其沉积于横向隔开的栅极结构106A、106B、106C之间的衬底102上方。
图2B显示在执行一个或多个蚀刻制程以相对介电层112选择性凹入栅极结构106A、106B、106C及间隔物108A、108B、108C从而定义空腔114A、114B、114C以后的产品100。
图2C显示执行数个制程操作以后的产品100。在凹入侧壁间隔物108A、108B、108C上方的空腔114A、114B、114C中形成内间隔物116A、116B、116C。形成共形间隔物材料层(例如，硅碳氧化物(SiCO))并执行非等向性蚀刻制程以移除该共形层的水平部分，从而导致形成内间隔物116A、116B、116C。内间隔物116A、116B、116C是由不同于间隔物108A、108B、108C的材料构成，以允许随后的选择性蚀刻。内间隔物116A、116B、116C可具有与间隔物108A、108B、108C相同的横向厚度或者它们可具有不同的横向厚度，取决于该间隔物材料层的厚度。
图2D显示执行一个或多个制程以形成覆盖层118A、118B、118C(例如，氮化硅)来填充空腔114A、114B、114C以后的产品100。可执行覆被(blanket)沉积制程，接着执行平坦化制程，以定义覆盖层118A、118B、118C。
图2E显示执行一个或多个制程以在定义源极/漏极区的外延半导体材料110A、110B上方形成沟槽硅化物(TS)接触点120A、120B(例如，金属硅化物或金属硅化物与金属的组合)以后的产品。TS接触点120A、120B也可被称为源极/漏极(SD)接触。利用图案化掩膜(未显示)执行蚀刻制程，以移除位于外延半导体材料110A、110B上方的介电层112，从而定义空腔。执行一个或多个制程(例如，清洗、沉积、退火、平坦化等)，以用导电硅化物材料填充该空腔，从而定义TS接触点120A、120B。在一个例子中，TS接触点120A、120B为线型结构，其延伸出入图2E中的图示页面，在区域104B中(沿与该装置的栅极宽度方向对应的方向)大体上延伸主动区102X的整个长度。
图2F显示执行一个或多个制程以后的产品100。执行蚀刻制程以凹入TS接触120A、120B，并执行沉积制程以在凹入TS接触点120A、120B及覆盖层118A、118B、118C上方形成介电层122(也就是，显示为与介电层112合并)。
图2G显示执行一个或多个制程以在介电层122中图案化CB空腔124A、124B、124C以后的产品100。在介电层122上方形成图案化堆叠物(例如，OPL(有机平坦化层)、光阻、BARC(底部抗反射涂层)等-未显示)，并对其图案化以定义与CB空腔124A、124B、124C对应的开口。通过该图案化开口执行蚀刻制程以定义CB空腔124A、124B、124C。
图2H显示执行一个或多个蚀刻制程以选择性地移除覆盖层118A、118B、118C的暴露部分以后的产品100。
图2I显示执行一个或多个制程(例如，沉积及平坦化)以在CB空腔124A、124B、124C中形成CB接触点126A、126B、126C(例如，钨或某种其它导电金属或材料)以后的产品100。
图2J显示在CB接触点126B上方形成图案化掩膜128(例如，OPL、光阻、BARC等)，并执行蚀刻制程以凹入CB接触点126A、126C以后的产品100。图案化掩膜128防止CB接触点126B的凹入。
图2K显示执行蚀刻制程以移除内间隔物116A、116C，从而定义间隔物空腔130A、130C以后的产品100。由于内间隔物116A、116C由不同于间隔物108A、108C的材料制成，因此该蚀刻可为选择性的。
图2L显示执行一个或多个制程以后的产品100。执行灰化制程以移除掩膜128。执行沉积制程(例如，原子层沉积)以在间隔物空腔130A、130C中形成导电间隔物132A、132C(例如，TiN、ALD、W、Ru等)。执行回蚀刻以将该导电材料的高度降低至大致与CB接触点126A、126C相同的高度。
图2M显示执行沉积制程以在凹入TS接触点120A、120B及覆盖层118A、118B、118C上方形成介电层134(也就是，显示为与介电层122合并)以后的产品100。
图2N显示执行数个制程以在介电层134中形成CA接触点136B、136C以后的产品100。执行图案化蚀刻制程以在介电层134中定义CA开口，从而暴露区域104B中的TS接触点120B以及由CB接触点126C及导电间隔物132C定义的组合结构。
导电间隔物132A通过将CB接触126A(也就是，与栅极结构106耦接)与TS接触120A(也就是，与源/漏外延材料110A耦接)耦接来提供栅极至源/漏交叉连接。导电间隔物132C为CA接触136C提供较宽的着陆区，以与CB接触126C相接。由于在形成导电间隔物132A、132C的制程步骤期间掩蔽区域104B，因此CB接触126B(见图2M)可形成于主动区上方，从而缩小单位单元尺寸。在集成流程中可实现针对不同区域104A、104B、104C的这些不同目标。
由于本发明可以本领域的技术人员借助本文中的教导而明白的不同但等同的方式修改并实施，因此上面所揭露的特定具体实施例仅为示例性质。例如，可以不同的顺序执行上述制程步骤。而且，本发明并非意图限于本文中所示的架构或设计的细节，而是如下面的权利要求所述。因此，显然，可对上面所揭露的特定具体实施例进行修改或变更，且所有此类变更落入本发明的范畴及精神内。要注意的是，用于说明本说明书以及所附权利要求中的各种制程或结构的例如“第一”、“第二”、“第三”或者“第四”等术语的使用仅被用作此类步骤/结构的快捷参考，并不一定意味着按排列顺序执行/形成此类步骤/结构。当然，依据准确的权利要求语言，可能要求或者不要求此类制程的排列顺序。因此，本发明请求保护的范围如权利要求所述。

Claims (19)

1.一种制造集成电路的方法，该方法包括：
在半导体衬底的第一区域上方形成第一栅极结构；
形成邻近该第一栅极结构的第一侧壁间隔物；
形成邻近该第一侧壁间隔物的第一介电层；
凹入该第一栅极结构及该第一侧壁间隔物，以定义第一栅极接触空腔；
在该第一栅极接触空腔中形成第二侧壁间隔物；
在该第一栅极接触空腔中形成第一导电栅极接触点；
在形成该第一导电栅极接触点以后，移除该第二侧壁间隔物，以暴露该第一侧壁间隔物的上表面且在该第一介电层与该第一导电栅极接触点之间定义第一间隔物空腔；以及
在该第一间隔物空腔中形成导电材料，以形成接触该第一导电栅极接触点及该第一侧壁间隔物的该上表面的第一导电间隔物，其中，在形成该导电材料以后，该第一侧壁间隔物覆盖该第一栅极结构的整个侧壁，使得该第一导电间隔物接触第一源极/漏极接触点。
2.如权利要求1所述的方法，还包括：
在该第一栅极接触空腔中形成第一栅极覆盖层；
在该第一栅极覆盖层上方形成第二介电层；
在该第二介电层中形成第二栅极接触空腔，从而暴露该第一栅极覆盖层；
移除该第一栅极覆盖层；以及
在移除该第一栅极覆盖层以后，形成该第一导电栅极接触点。
3.如权利要求2所述的方法，其中，形成该第一导电栅极接触点还包括在该第一栅极接触空腔及该第二栅极接触空腔中形成该第一导电栅极接触点，且该方法还包括：
凹入该第一导电栅极接触点，以暴露至少一部分的该第二侧壁间隔物；以及
在凹入该第一导电栅极接触点以后，移除该第二侧壁间隔物。
4.如权利要求3所述的方法，还包括：
在该第一导电栅极接触点及该第一导电间隔物上方形成第三介电层；以及
在该第三介电层中形成接触该第一导电栅极接触点的第二导电栅极接触点。
5.如权利要求4所述的方法，其中，该第二导电栅极接触点接触至少一部分的该第一导电间隔物。
6.如权利要求3所述的方法，还包括：
形成邻近该第一栅极结构的第一源极/漏极区；以及
形成接触该第一源极/漏极区的该第一源极/漏极接触点。
7.如权利要求1所述的方法，还包括：
在该第一栅极结构上方形成该第一介电层；以及
在凹入该第一栅极结构及该第一侧壁间隔物之前，平坦化该第一介电层以暴露该第一栅极结构及该第一侧壁间隔物，其中，该第一栅极接触空腔定义于该第一介电层中。
8.一种制造集成电路的方法，该方法包括：
在半导体衬底上方形成多个栅极结构；
邻近各该多个栅极结构形成第一侧壁间隔物；
形成邻近该第一侧壁间隔物的第一介电层；
凹入该多个栅极结构及该第一侧壁间隔物，以定义第一栅极接触空腔；
在该第一栅极接触空腔中形成第二侧壁间隔物；
在该第一栅极接触空腔中形成第一导电栅极接触点；
在该多个栅极结构的第一子集上方形成掩膜层；
在形成该第一导电栅极接触点以后，移除未被该掩膜层覆盖的该多个栅极结构的第二子集的该第二侧壁间隔物，以暴露该第一侧壁间隔物的上表面且在该第一介电层与该第一导电栅极接触点之间定义第一间隔物空腔；以及
在该第一间隔物空腔中形成导电材料，以形成接触该多个栅极结构的该第二子集的该第一导电栅极接触点及该第一侧壁间隔物的该上表面的第一导电间隔物，其中，在形成该导电材料以后，该第一侧壁间隔物覆盖该多个栅极结构的整个侧壁，使得该多个栅极结构的该第二子集中的该第一导电间隔物接触第一源极/漏极接触点。
9.如权利要求8所述的方法，还包括：
在该第一栅极接触空腔中形成第一栅极覆盖层；
在该第一栅极覆盖层上方形成该第一介电层；
在该第一介电层中形成第二栅极接触空腔，从而暴露该第一栅极覆盖层；
移除该第一栅极覆盖层；以及
在移除该第一栅极覆盖层以后，形成该第一导电栅极接触点。
10.如权利要求9所述的方法，其中，形成该第一导电栅极接触点还包括在该第一栅极接触空腔及该第二栅极接触空腔中形成该第一导电栅极接触点，其中，该掩膜层形成于该多个栅极结构的该第一子集的该第一导电栅极接触点上方。
11.如权利要求10所述的方法，还包括：
凹入该多个栅极结构的该第二子集的该第一导电栅极接触点，以暴露至少一部分的该第二侧壁间隔物；以及
在凹入该第一导电栅极接触点以后，移除该第二侧壁间隔物。
12.如权利要求11所述的方法，还包括：
在该第一导电栅极接触点及该第一导电间隔物上方形成第二介电层；以及
在该第二介电层中形成接触该第一导电栅极接触点的第二导电栅极接触点，该第二导电栅极接触点用于该多个栅极结构的该第二子集。
13.如权利要求12所述的方法，其中，该第二导电栅极接触点接触至少一部分的该第一导电间隔物。
14.如权利要求12所述的方法，还包括：
形成邻近该多个栅极结构的第一源极/漏极区；以及
形成接触该第一源极/漏极区的该第一源极/漏极接触点。
15.如权利要求8所述的方法，其中，该多个栅极结构的该第一子集形成于主动区上方，且该多个栅极结构的该第二子集形成于该主动区外部的隔离区上方。
16.如权利要求8所述的方法，还包括：
在该多个栅极结构上方形成该第一介电层；以及
在凹入该多个栅极结构及该第一侧壁间隔物之前，平坦化该第一介电层以暴露该多个栅极结构及该第一侧壁间隔物，其中，该第一栅极接触空腔定义于该第一介电层中。
17.一种集成电路产品，包括：
第一栅极结构，位于半导体衬底上方；
第一侧壁间隔物，邻近该第一栅极结构；
第一导电栅极接触点，接触该第一栅极结构及该第一侧壁间隔物的上表面；
第一导电间隔物，接触该第一侧壁间隔物以及该第一导电栅极接触点的侧壁；
第二栅极结构，位于该半导体衬底上方；
第二侧壁间隔物，邻近该第二栅极结构；
第二导电栅极接触点，接触该第二栅极结构及该第二侧壁间隔物的上表面；
第一源极/漏极区，邻近该第二栅极结构；
第一源极/漏极接触点，接触该第一源极/漏极区；以及
第二导电间隔物，接触该第二侧壁间隔物及该第一导电栅极接触点的侧壁，其中，该第一导电间隔物接触该第一源极/漏极接触点。
18.如权利要求17所述的集成电路产品，还包括通过隔离结构定义于该半导体衬底中的主动区，其中，该第一栅极结构形成于该主动区外部的该隔离结构上方。
19.如权利要求17所述的集成电路产品，还包括：
介电层，位于该第一导电栅极接触点上方；以及
第二导电栅极接触点，位于该介电层中，其中，该第二导电栅极接触点接触该第一导电栅极接触点以及至少一部分的该第一导电间隔物。
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