CN106531805A - 互连结构及其制造方法以及使用互连结构的半导体器件 - Google Patents

互连结构及其制造方法以及使用互连结构的半导体器件 Download PDF

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CN106531805A
CN106531805A CN201610683475.4A CN201610683475A CN106531805A CN 106531805 A CN106531805 A CN 106531805A CN 201610683475 A CN201610683475 A CN 201610683475A CN 106531805 A CN106531805 A CN 106531805A
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silicide
contact area
present
layer
semiconductor device
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CN201610683475.4A
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CN106531805B (zh
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林瑀宏
刘继文
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括半导体衬底、存在于半导体衬底中的接触区和位于接触区的纹理化的表面上的硅化物。多个溅射残留物存在于硅化物和接触区之间。由于接触区的表面被纹理化，因此由硅化物提供的接触面积相应的增加，从而降低了半导体器件中的互连结构的电阻。本发明实施例涉及互连结构及其制造方法以及使用互连结构的半导体器件。

Description

互连结构及其制造方法以及使用互连结构的半导体器件
技术领域
本发明实施例涉及互连结构及其制造方法以及使用互连结构的半导体器件。
背景技术
半导体集成电路(IC)工业经历了高速发展。顾名思义，现代集成电路由数百万个诸如晶体管和电容器的有源器件构成。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代IC都具有比上一代更小和更复杂的电路。最初这些器件相互隔离，但是，随后通过多个金属层互连在一起以形成功能电路。随着IC变的越来越复杂，互连结构也变的更复杂，导致了金属层数量的增加。
互连部件包括诸如金属线(布线)的横向互连件和诸如导电通孔和接触件的垂直互连件。然而，复杂的互连件限制了现代集成电路的性能和密度
发明内容
根据本发明的一个实施例，提供了一种半导体器件，包括：半导体衬底：接触区，存在于所述半导体衬底中，其中，所述接触区包括纹理化的表面；硅化物，位于所述接触区上；以及多个溅射残留物，存在于所述硅化物和所述接触区之间。
根据本发明的另一个实施例，还提供了一种互连结构，包括：硅化物，存在于接触区上，其中，纹理化所述接触区和所述硅化物之间的界面，以及多个溅射残留物存在于所述硅化物中；导体，存在于所述硅化物上；以及阻挡层，存在于所述导体和所述硅化物之间。
根据本发明的又另一实施例，还提供了一种制造互连结构的方法，所述方法包括：在介电层中形成开口以暴露接触区的部分；实施物理去除工艺以纹理化所述接触区的表面；在所述接触区的被纹理化的所述表面上形成金属层；在所述金属层上形成阻挡层；以及实施退火工艺，其中，所述金属层与所述接触区反应从而在所述接触区和所述阻挡层之间形成硅化物。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应当注意，根据工业中的标准实践，各个部件并非按比例绘制。事实上，为了清楚讨论，各个部件的尺寸可以任意增大或减小。
图1A至图1E是根据本发明的一些实施例的用于制造FinFET器件的方法的在各个阶段的示意性斜视图。
图2A至图2F是制作FinFET器件中的互连结构的方法的局部截面图。
图3是本发明一些实施例的互连结构的局部截面图。
图4A至图4F是根据本发明的一些实施例的用于制造半导体器件的方法在各个阶段的示意性斜视图。
图5是本发明一些实施例的互连结构的局部截面图。
具体实施方式
下列公开提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下文中，将描述器件和布置的具体实例，以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括在第一部件和第二部件之间形成额外的部件使得第一部件和第二部件可以不直接接触的实施例。而且，本发明在各个实例中可重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，为便于描述，在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外，在使用中或操作中的器件的不同方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且通过在本文中使用的空间关系描述符可同样地作相应地解释。
随着半导体器件的尺寸不断缩小，满足导电要求以及多个金属化制作中的可靠性变得越来越困难。例如，包括金属线和导电通孔(从集成电路(IC)器件不同的层与金属线互连)的互连结构的形成通常要求低电阻而且也要求阻挡导电通孔中的导电金扩散至ILD层中的金属的阻挡层。为了降低IC器件中的RC延迟，阻挡层也起控制互连件的电阻的作用。本发明涉及降低诸如FinFET器件的半导体器件中的互连结构的电阻的方法。
图1A至图1E是根据本发明的一些实施例的用于制造FinFET器件的方法的在各个阶段的示意性斜视图。参考图1。提供了衬底110。在一些实施例中，衬底110可以是半导体材料以及可以包括已知结构，例如，已知结构包括诸如梯度层和掩埋氧化物。在一些实施例中，衬底110包括未掺杂或者掺杂的块状硅(p型、n型或它们的组合等)。也可以使用适合用作半导体器件形成的其他材料。诸如锗、石英、蓝宝石及玻璃的其他材料可以可选地用于衬底110。可选地，硅衬底110可以是绝缘体上半导体(SOI)衬底的有源层或诸如形成在块体硅层上的硅锗层的多层结构。
多个p阱区116和多个n阱区112形成在衬底110中。在p阱区116的两个之间形成n阱区112的一个。将诸如硼离子的P掺杂剂材料注入p阱区116内，以及将诸如砷离子的N掺杂剂材料注入n阱区112内。在p阱区116的注入期间，用掩模(诸如光刻胶)覆盖n阱区112，在n阱区112的注入期间，用掩模(诸如光刻胶)覆盖p阱区116。
衬底110上形成多个半导体鳍122、124。半导体鳍124形成在p阱区116上，以及半导体鳍122形成在n阱区112上。在一些实施例中，半导体鳍122、124包括硅。值得注意的是，图1中的半导体鳍122、124的数量是说明性的，并不应当限制本发明的保护范围。本领域的技术人员可以根据实际情况选择合适的半导体鳍122、124的数量。
例如，可以通过使用光刻技术图案化和蚀刻衬底110来形成半导体鳍122、124。在一些实施例中，光刻胶材料层(未示出)沉积在衬底110上方。根据所需图案(这里为半导体鳍122、124)光照(暴露)并显影光刻胶材料层，从而去除光刻胶材料层的一部分。剩下的光刻胶材料保护下面的材料免于后续的例如蚀刻的工艺步骤的损坏。应当注意的是，例如氧化物掩模或氮化硅掩模的其他掩模也可以用在蚀刻工艺中。
多个隔离结构130形成在衬底110上。作为围绕半导体鳍122、124的浅沟槽隔离(STI)的隔离结构130可以通过采用正硅酸乙酯(TEOS)和氧气为前体的化学汽相沉积(CVD)技术来形成。在一些其他的实施例中，隔离结构130是SOI晶圆的绝缘层。
参考图1B。至少一个伪栅极142形成在半导体鳍122、124的部分上，并暴露半导体鳍122、124的其他部分。可以横跨多个半导体鳍122、124来形成伪栅极142。多个栅极间隔件140形成在衬底110的上方并且沿着伪栅极142的侧面。在一些实施例中，栅极间隔件140可包括二氧化硅、氮化硅、氮氧化硅或其他合适的材料。栅极间隔件140可包括单层或多层结构。栅极间隔件140的毯状层可通过CVD、PVD、ALD或其他合适的技术来形成。然后，在毯状层上实施各向异性蚀刻以在伪栅极142的两侧形成一对栅极间隔件140。在一些实施例中，栅极间隔件140用于偏移随后形成的诸如源极/漏极区域的掺杂区域。栅极间隔件140还可以用于设计或改变源极/漏极区域(结)轮廓。
参考图1C。部分地去除(或部分的沟槽化)半导体鳍122、124的被伪栅极142和栅极间隔件140暴露的部分以在半导体鳍122、124中形成沟槽126。在一些实施例中，沟槽126形成为具有介电鳍侧壁结构125作为沟槽126的上部。在一些实施例中，沟槽126的侧壁基本彼此竖直平行。在一些实施例中，沟槽126形成为非竖直轮廓。
在图1C中，半导体鳍122包括至少一个沟槽部分122r和至少一个沟道部分122c。沟槽126形成在沟槽部分122r上，以及伪栅极142覆盖沟道部分122c的部分。半导体鳍124包括至少一个沟槽部分124r和至少一个沟道部分124c。沟槽126形成在沟槽部分124r上，以及伪栅极142覆盖沟道部分124c的部分。
沟槽化(trenching)工艺可以包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。沟槽化工艺可以包括选择性湿蚀刻或选择性干蚀刻。湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液、或其他合适的溶液。干蚀刻工艺和湿蚀刻工艺具有可以调整的蚀刻参数，诸如使用的蚀刻剂、蚀刻温度、蚀刻液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流速和其他合适的参数。例如，湿蚀刻液可以包括NH4OH、KOH(氢氧化钾)，HF(氢氟酸)，TMAH(四甲基氢氧化铵)、其他合适的湿蚀刻溶液或它们的组合。干蚀刻工艺包括使用氯基化学物质的偏置的等离子体蚀刻工艺。其他干蚀刻气体包括CF4、NF3、SF6和He。也可以使用这样的机制各向异性地实施干蚀刻，诸如DRIE(深反应离子蚀刻)。
参考图1D。多个外延结构160分别形成半导体鳍124的沟槽126中，以及多个外延结构150分别形成在半导体鳍122的沟槽126中。外延结构160与邻近的外延结构150分开。外延层150和160从沟槽R突出，外延结构160可以是n型外延结构，以及外延结构150可以是p型外延结构。可使用一个或多个外延或外延的(epi)工艺来形成该外延结构150和160，使得可在半导体鳍122、124上以晶体状态形成Si部件、SiGe部件和/或其他合适的部件。在一些实施例中，外延结构150和160的晶格常数不同于半导体鳍122、124的晶格常数，并且，外延结构150和160具有应力或应变以使SRAM器件实现载流子迁移以及提高器件的性能。外延结构150和160可以包括诸如锗(Ge)或硅(Si)的半导体材料；或者诸如砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、碳化硅(SiC)或磷砷化镓(GaAsP)的化合物半导体材料。
在一些实施例中，在不同的外延工艺中形成外延结构150和160。外延结构160可以包括SiP、SiC、SiPC、Si、III-V族化合物半导体材料或它们的组合，以及外延结构150可以包括SiGe、SiGeC、Ge、Si、III-V族化合物半导体材料或它们的组合。在形成外延结构160的期间，随着外延的进行，可以掺杂诸如磷或砷的n型杂质。例如，当外延结构160包括SiC或Si，可以掺杂n型杂质。此外，在形成外延结构150的期间，随着外延的进行，可以掺杂诸如硼或BF2的p型杂质。例如，当外延结构150包括SiGe，可以掺杂p型杂质。外延工艺包括CVD沉积技术(如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延生长和/或其他合适的工艺。该外延工艺可使用气体和/或液体前体，气体和/或液体前体与半导体鳍122、124(例如，硅)的成分相互作用。因此，可获得应变的沟道以提高载流子迁移率和加强器件性能。该外延结构150和160可以是原位掺杂的。如果外延结构150和160不是原位掺杂的，那么将执行第二注入工艺(例如，结注入工艺)以掺杂该外延结构150和160。可执行一个或多个退火工艺以激活外延结构150和160。该退火工艺包括快速热退火(RTA)和/或激光退火工艺。
在一些实施例中，外延结构150具有顶部和设置在顶部和衬底110之间的主体部。顶部的宽度大于主体部的宽度。外延结构160具有顶部和设置在顶部和衬底110之间的主体部。顶部的宽度大于主体部的宽度。外延结构150和160用作FinFET半导体器件100的源极/漏极电极。
在一些实施例中，外延结构150和160具有不同的形状。外延结构160的顶部可以具有至少一个存在于隔离结构130上方的刻面表面，以及外延结构150的顶部可以具有至少一个存在于隔离结构130上方的非刻面(或圆)表面，权利要求范围不限于这个方面。
参考图1E。形成外延结构150和160之后，去除伪栅极142，从而在栅极间隔件140之间形成沟槽。通过沟槽暴露隔离结构130和半导体鳍122、124的部分。可以通过实施一个或多个蚀刻工艺去除伪栅极142。栅极堆叠件170形成并填充沟槽。栅极堆叠件170包括栅电极和在栅电极和隔离结构130之间沉积的栅极电介质。可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺分别形成栅极电介质和栅电极。栅极介电质是由诸如氮化硅、氮氧化硅、具有高介电常数(高k)的介电材料或它们的组合的介电材料制成。在一些实施例中，栅电极是金属电极。在一些实施例中，栅极堆叠件170还包括位于栅电极上的覆盖层。
在制造FinFET器件100之后，形成用于将FinFET器件的电极互连到其他器件的互连结构。在图2A到2F中讨论了互连结构制造的细节，其中图2A到2F是制造FinFET器件中的互连结构的方法的局部示意图。
参考图2A。在FinFET器件上形成介电层220。介电层220覆盖外延层210以及外延层210周围的鳍120。鳍120可以是图1D中的鳍122、124的任何一个，以及外延结构210可以是如图1D中示出的外延结构150和160的任何一个。介电层220可以是层间介电质(ILD)以及可以包含氧化物材料的低k材料。例如，可以通过化学汽相沉积(CVD)技术步骤、旋涂工艺步骤或它们的组合形成介电层220。介电层220用于隔离形成在不同和/相同的层上的导电部件。
在介电层220中形成开口222。在一些实施例中，多个开口形成在介电层220中。例如，开口222可以是接触开口、通孔开口、单镶嵌开口、双镶嵌开口或它们的组合。例如，可以通过在介电层220上方形成图案化的光刻胶层(未示出)以及通过使用图案化的光刻胶层(未示出)作为掩模使用干蚀刻工艺步骤以去除介电层220的部分以限定开口222来形成开口222。也可以使用各个干蚀刻工艺。在蚀刻工艺步骤后，例如，通过光刻去除工艺来去除图案化的光刻胶层(未示出)。在形成开口222期间，也去除外延结构210的一些。当外延结构210暴露并与空气反应时，在外延结构210的表面上形成氧化物层212。
参考图2B，执行蚀刻工艺以去存在于暴露的外延结构210上的氧化物层212。去除工艺可以是诸如溅射工艺的物理去除工艺。在物理去除工艺期间，能量离子214轰击在外延结构210的暴露部分上并且腐蚀外延结构210上的氧化物层212。例如,能量离子214可以是氩(Ar)离子、氖(Ne)离子、氪(Kr)离子或氙(Xe)离子。
由于能量离子214的轰击，因此氧化物层212和外延结构210的部分脱落。在去除工艺之后，残留的氧化物层212变成坏的且不连续的。氧化物层212和外延结构210的部分的脱落导致外延结构210的粗糙且不规则的表面。在一些实施例中，在外延结构210的顶部上形成多个凹槽R。凹槽R随机地布置在外延结构210的表面上。凹槽R的密度在在外延结构210的表面上也是随机的。凹槽R的深度在从约1.5nm至约3.5nm的范围，并且凹槽R的深度差在从约0.5nm至约3nm的范围，凹槽R的深度对应于生成的能量离子214的RF功率。在一些实施例中，溅射工艺的RF功率高于500w,以及在外延结构210上的凹槽R的深度差在从约1.5nm至约3nm的范围内。在一些实施例中，溅射工艺的RF功率低于400w,以及在外延结构210上的凹槽R的深度差在从约0.5nm至约1.5nm的范围内。由于诸如SiGe的p型外延结构的蚀刻速率大于诸如SiP的n型外延结构的蚀刻速率,因此，p型FinFET器件的深度差比n型FinFET器件深度差高约20nm。
在物理去除工艺期间，诸如氩(Ar)离子、氖(Ne)离子、氪(Kr)离子或氙(Xe)离子的能量离子214的一些可以嵌入在外延结构210中。包括深度、密度或存在于外延结构210的表面上的离子214的量是随机的且是不规则的。离子214的分布可以与提供的能量离子214的RF功率相关。
参考图2C。通过实施化学去除工艺来去除保留在外延结构210上的氧化物层212(如图2B所示)。可以使用包括NF3和NH3的化学混合物实施化学去除工艺。然而，在化学去除工艺中，也可以利用用于去除氧化物层212而不损坏外延结构210的其他合适的化学物质。
通过实施物理去除工艺和化学去除工艺去除氧化物层212。利用物理去除工艺以纹理化外延结构210的表面由此形成外延结构210的粗糙且不规则的表面。在物理去除工艺期间，在外延结构210的表面上形成凹槽R，以及小量的离子214注射至外延结构210内。由于凹槽R的存在，因此外延结构210的表面面积增加。利用化学去除工艺以去除氧化物层212。在实施化学去除工艺之后，离子214不与化学物质反应并且仍存在于外延结构210中。
参考图2D。金属层230形成为内衬于开口222的侧壁上和顶面以及形成于介电层220的上方。在一些实施例中，金属230可为金属合金层。金属层230包括用于自对准硅化物(自对准硅化物)工艺的诸如钛(Ti)、钴(Co)、镍(Ni)、铂(Pt)或钨(W)的金属。介电层230可以通过诸如CVD工艺、PVD工艺或溅射沉积的沉积工艺形成。
阻挡层240进一步形成在金属层230上。阻挡层240可以用作阻挡件以防止随后形成的导体扩散到下面的介电层220内。在一些实施例中，该阻挡层240包括钽(Ta)、钛(Ti)等。在一些实施例中，阻挡层240的厚度为约10埃至约250埃。在一些实施例中，金属层230和阻挡层240的组合厚度小于约120埃以防止在随后的开口填充工艺期间的间隙填充问题。可以通过PVD、CVD、PECVD、LPCVD工艺或其他已知的沉积技术来沉积阻挡240。
参考图2E。实施退火工艺以在外延结构210上形成硅化物250。利用退火工艺以将非晶硅转变为低电阻的多晶相。通常将硅化工艺用于形成至源极和漏极区的硅化物接触件以解决临界尺寸公差的问题。在一些实施例中，该金属层是钛层以及被退火成为硅化钛250。实施退火工艺以形成高电阻率富钛相，硅化钛的厚度在从约30埃至约60埃的范围内。在一些实施例中，由于外延层210是n型外延结构，因此硅化钛250可以是TiSi2。在一些实施例中，由于外延层210是p型外延结构，硅化钛250可以是TiSiGe。
在各个实施例中，由于外延结构210表面被纹理化，并在外延结构210上形成凹槽R，因此外延层210和硅化物250之间的界面粗糙且不规则，相应的增加了外延结构210与硅化物250的接触面积。来自物理去除工艺的离子214仍然保留在硅化物250中。外延结构210和硅化物250之间界面的深度差在从约1.5nm至约3.5nm的范围内。
参考图2F。在阻挡层240上方形成导体260以填充开口222。在一些实施例中，导体260在介电层220中形成为互连结构。在一些实施例中，导体260通过诸如CVD工艺、PVD工艺或溅射沉积的沉积工艺形成。在一些实施例中，导体260包括钨(W)、铜(Cu)或钴(Co)。
金属层230的底部与外延结构210反应并成为硅化物250。因此，剩余的金属层230存在于阻挡层240和开口222的侧壁之间，并且不存在于硅化物250和阻挡层240之间。即，阻挡层240的底部与硅化物250直接接触，从而降低了互连结构的接触电阻。
去除导体260的位于介电层220上方的部分。在一些实施例中，去除工艺是实施为去除位于开口222外部的导体260、阻挡层240和金属层230的多余部分的化学机械抛光(CMP)工艺，从而暴露介电层220的顶面并获得平坦的表面。
包括导体260和硅化物250的互连结构形成在介电层230中并连接至外延结构210。由于硅化物层250和外延结构210之间变成粗糙和不规则，所以，它们之间的接触面积相应的增加。因此，由于增加的接触面积降低了互连结构的电阻。
参考图3，图3是本发明的一些其他实施例的互连结构的局部截面图。鳍120具有位于其上多个外延结构。如图2A到图2F所讨论的，实施物理去除工艺和化学工艺以纹理化外延结构210的表面以及以去除位于外延结构210的暴露部分上的氧化物层。连接的外延结构210形成山状的顶面，以及外延结构210的顶面的深度差大于单个的外延结构210的顶面的深度差。例如，外延结构210的顶面的深度差在从约3nm至约25nm的范围，该深度差对应于生成的能量离子214的RF功率。在一些实施例中，溅射工艺的RF功率高于500w,以及外延结构210的顶面的深度差在从约15nm至约25nm的范围内。在一些实施例中，溅射工艺的RF功率低于400w,以及外延结构210的顶面的深度差在从约3nm至约15nm的范围内。
因此，位于阻挡层240和外延结构210之间的硅化物250的厚度是不均匀的，外延结构210的每个的宽度不相同。邻近的外延结构210之间的差在从约3nm至约20nm的范围内。硅化物250的厚度差在从约3nm至约25nm的范围内。
上述互连结构并不限于用于具有外延结构的FinFET器件中，但是不能用于具有硅化物接触件的任何合适的半导体器件中。例如，上述互连结构可以用于例如纳米线组件，如在图4A至图4F中讨论。
参考图4A到图4F。图4A至图4F是根据本发明的一些实施例的用于制造半导体器件的方法在各个阶段的示意性斜视图。参照图4A，方法始于绝缘体上半导体(SOI)结构310。SOI结构301包括半导体衬底312、埋氧(BOX)层314和SOI层316。在一些实施例中，SOI层316由诸如硅的半导体材料来形成。BOX层314可以包括氧化硅、氮化硅或氮氧化硅。BOX层314存在于半导体衬底312和SOI层316之间。更详细的，BOX层314存在于SOI层316下面以及半导体衬底312顶部处，以及可以通过将高能量掺杂剂注入SOI结构310内以及然后退火该结构以形成埋氧层来形成BOX层314。在一些实施例中，可以在SOI层316的形成之前，沉积或生长BOX层314。在一些其他实施例中，可使用晶元接合技术形成SOI结构310，其中，利用粘合剂、粘合聚合物或直接接合来形成接合的晶元对。
参考图4B。图案化SOI层316以形成垫322、324、326和328以及连接结构332和334。例如，可以通过使用诸如光刻和蚀刻的合适的工艺制造垫322、324、326和328以及连接结构332和334。连接结构332连接垫322和324。连接结构334连接垫326和328。也就是，连接结构332的至少一个可以具有位于连接结构332的相对侧上的分开的垫322和324，以及连接结构334的至少一个可以具有在连接结构334的相对两侧上的分开的垫326和328。
参考图4C。部分去除连接结构332和324以形成第一纳米线342和第二纳米线344。在一些实施例中，通过各向异性蚀刻工艺去除连接结构332和324的下部和BOX层314的下面的部分，使得第一纳米线342形成为悬置在垫322和324之间，以及第二纳米线344形成为悬置在垫326和328之间。各向同性蚀刻是不包括优选方向的蚀刻的形式。各向同性蚀刻的一个实例是湿蚀刻。各向同性蚀刻工艺形成底切区域，第一和第二纳米线342和344悬置在底切区域上方。在一些实施例中，可以使用稀释的氢氟(DHF)酸来实施各向同性蚀刻。各向同性蚀刻工艺之后，可以使第一和第二纳米线342和344平滑以形成椭圆形(以及，在一些情况下，圆柱形)结构。在一些实施例中，可以通过退火工艺来实施平滑工艺。示例性退火温度可以在从约600℃到约1000℃之间的范围内，以及退火工艺中的氢气压力在从约7托到约600托的范围内。
参考图4D。在伪栅极材料层362的相对侧壁上形成间隔件352，以及在伪栅极材料层364的相对侧壁上形成间隔件354。形成间隔件352和354的方法包括形成介电层，然后实施蚀刻工艺以去除介电层的部分。
形成间隔件352和354之后，可以将n型掺杂剂引至第一纳米线342的邻近间隔件352的暴露部分，从而形成n型源极/漏极延伸区。相似的，可以将p型掺杂剂引至第二纳米线344的邻近间隔件354的暴露部分，从而形成n型源极/漏极延伸区。p型掺杂剂的实例包括但不限于硼、铝、镓或铟。n型掺杂剂的实例包括但不限于锑、砷或磷。
在一些实施例中，使用原位掺杂外延生长工艺及随后的退火工艺以将掺杂剂从原位掺杂外延半导体材料驱动至第一纳米线342和第二纳米线344内以提供延伸区，以在第一纳米线342和第二纳米线344中形成源极/漏极延伸区。在一些实施例中，使用外延生长工艺来形成原位掺杂半导体材料。“原位掺杂”指的是在外延生长工艺期间将掺杂剂结合至原位掺杂的半导体材料内，外延生长工艺沉积原位掺杂的半导体材料的含半导体材料。当控制化学反应物时，沉积的原子到达第一和遮蔽的纳米线342和344以及垫322、324、326和328的表面处，沉积的原子具有足够的能量以在表面上移动以及和将其自身定向至沉积表面的原子的晶体排列。外延生长使垫322、324、326和328以及第一纳米线342和第二纳米线344的未被伪栅极材料层362和364以及间隔件352和354覆盖的部分变厚。
其后，对垫322、324、326和328实施离子注入以形成深源极和漏极区。可以使用离子注入形成深源极和漏极区。在提供深源极和漏极区的离子注入期间，可以通过诸如光刻胶掩模的掩模保护器件的不期望注入的部分。垫322和324中的深源极和漏极区具有与第一纳米线342中的源极和漏极区相同导电性的掺杂剂(诸如n型掺杂剂)，但是，垫322和324中的深源极和漏极区具有比第一纳米线342中的源极和漏极区更大的掺杂剂浓度。相似的，垫326和328中的深源极和漏极区具有与第二纳米线344中的源极和漏极区相同导电性的掺杂剂(诸如n型掺杂剂)，但是，垫326和328中的深源极和漏极区具有比第二纳米线344中的源极和漏极区更大的掺杂剂浓度。
参考图4E。形成层间介电(ILD)层370以覆盖伪栅极材料层362和364、第一纳米线342和第二纳米线344。层间介电(ILD)层370可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、低介电常数介电材料或它们的组合。可以通过诸如CVD工艺的沉积工艺形成层间介电(ILD)层370。随后，去除层间介电(ILD)层370以暴露伪栅极材料层的顶面。去除步骤包括实施化学机械抛光(CMP)工艺。通过诸如湿蚀刻的合适的工艺进一步去除伪栅极材料层。去除伪栅极材料层之后，在间隔件352之间形成第一沟槽382以及在间隔件354之间形成第二沟槽384，并且第一沟槽382和第二沟槽384通过间隔件352、354和ILD层370在空间上彼此隔离
参考图4F。栅极堆叠件390和392形成并填充沟槽382和384。栅极堆叠件390和392分别包括包裹纳米线的栅极介电质、包裹栅极介电质的栅电极和包裹栅电极的覆盖层。
在形成半导体器件300之后，在ILD层370中形成多个互连结构以连接至垫322、324、326和328。图4中示出了互连结构和垫的截面图。
如图5所示，互连结构400形成在ILD层370中并连接至垫320。垫320可以是垫322、324、326和328的任何一个。互连结构400包括金属层410、硅化物420、阻挡层430和导体440。制造互连结构400的细节与图2A至图2G中描述的方法基本相同。在ILD层370中形成开口之后，通过实施诸如溅射工艺的物理去除工艺以纹理化垫320的暴露的部分。诸如Ne、Ar、Kr、Xe的用于溅射工艺的一些反应离子412保留在垫320的表面中。在ILD层370的开口中沉积金属层410，金属层的底部与垫320反应并成为硅化物420。离子412留在硅化物420中。金属层410存在于阻挡层430和ILD层370的侧壁之间，并且不存在于阻挡层430和硅化物420之间。阻挡层430与硅化物层420直接接触。形成导体440并填充沟槽。
通过实施物理去除工艺以纹理化诸如外延结构和半导体垫的接触区的表面。用于物理去除工艺的一些离子保留在接触区中。接触区与沉积于其上的金属层反应从而在它们之间形成硅化物。由于接触区的表面被纹理化，因此由硅化物提供的接触面积相应的增加，从而降低了互连结构的电阻。
根据本发明的一些实施例，半导体器件包括：半导体衬底、存在于半导体衬底中的接触区和位于接触区上的硅化物。接触区包括纹理化的表面和多个存在于硅化物和接触区之间的溅射残留物。
根据本发明的一些实施例，互连结构包括：存在于接触区上的硅化物、存在于硅化物上的导体和存在于导体和硅化物之间的阻挡层。接触区和硅化物之间的界面被纹理化，以及多个溅射残留物存在于硅化物中。
根据本发明的一些其他实施例，制造互连结构的方法包括：在介电层中形成开口以暴露接触区的部分；实施物理去除工艺以纹理化接触区的表面；在接触区被纹理化的表面上形成金属层；在金属层上形成阻挡层；实施退火工艺，其中，金属层与接触区反应从而在接触区和阻挡层之间形成硅化物。
根据本发明的一个实施例，提供了一种半导体器件，包括：半导体衬底：接触区，存在于所述半导体衬底中，其中，所述接触区包括纹理化的表面；硅化物，位于所述接触区上；以及多个溅射残留物，存在于所述硅化物和所述接触区之间。
在上述半导体器件中，所述溅射残留物是氩离子、氖离子、氪离子或氙离子。
在上述半导体器件中，所述接触区是外延结构。
在上述半导体器件中，所述接触区是半导体垫。
在上述半导体器件中，所述硅化物和所述接触区之间的界面是不规则的。
在上述半导体器件中，还包括存在于所述半导体衬底上的介电层，所述介电层包括开口以暴露所述硅化物的部分。
在上述半导体器件中，还包括：填充所述开口的导体；以及阻挡层，位于所述开口的侧壁上和所述硅化物上。
在上述半导体器件中，还包括：金属层，存在于所述开口的所述侧壁和所述阻挡层之间，其中，所述金属层不存在于所述硅化物和所述阻挡层之间。
根据本发明的另一个实施例，还提供了一种互连结构，包括：硅化物，存在于接触区上，其中，纹理化所述接触区和所述硅化物之间的界面，以及多个溅射残留物存在于所述硅化物中；导体，存在于所述硅化物上；以及阻挡层，存在于所述导体和所述硅化物之间。
在上述互连结构中，所述溅射残留物包括氩离子、氖离子、氪离子或氙离子。
在上述互连结构中，还包括金属层，其中，所述金属层存在于所述阻挡层的侧壁上，并且不存在于所述硅化物和所述阻挡层之间。
在上述互连结构中，所述金属层由钛、钴、镍、铂或钨制成。
在上述互连结构中，所述阻挡层由钽、钛制成。
在上述互连结构中，所述导体由钨、铜或钴制成。
根据本发明的又另一实施例，还提供了一种制造互连结构的方法，所述方法包括：在介电层中形成开口以暴露接触区的部分；实施物理去除工艺以纹理化所述接触区的表面；在所述接触区的被纹理化的所述表面上形成金属层；在所述金属层上形成阻挡层；以及实施退火工艺，其中，所述金属层与所述接触区反应从而在所述接触区和所述阻挡层之间形成硅化物。
在上述方法中，所述物理去除工艺去除位于所述接触区的所述表面上的氧化物层的部分，以及所述方法还包括在所述物理去除工艺之后实施化学去除工艺以去除所述氧化物层的残留部分。
在上述方法中，所述物理去除工艺在所述接触区的所述表面上形成多个凹槽。
在上述方法中，所述物理去除工艺包括溅射工艺。
在上述方法中，在所述金属层上形成所述阻挡层之后，实施所述退火工艺。
在上述方法中，还包括：在所述阻挡层上形成导体并且所述导体填充所述开口。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本公开的各个方面。本领域技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
半导体衬底：
接触区，存在于所述半导体衬底中，其中，所述接触区包括纹理化的表面；
硅化物，位于所述接触区上；以及
多个溅射残留物，存在于所述硅化物和所述接触区之间。
2.根据权利要求1所述的半导体器件，其中，所述溅射残留物是氩离子、氖离子、氪离子或氙离子。
3.根据权利要求1所述的半导体器件，其中，所述接触区是外延结构。
4.根据权利要求1所述的半导体器件，其中，所述接触区是半导体垫。
5.根据权利要求1所述的半导体器件，其中，所述硅化物和所述接触区之间的界面是不规则的。
6.根据权利要求1所述的半导体器件，还包括存在于所述半导体衬底上的介电层，所述介电层包括开口以暴露所述硅化物的部分。
7.根据权利要求6所述的半导体器件，还包括：
填充所述开口的导体；以及
阻挡层，位于所述开口的侧壁上和所述硅化物上。
8.根据权利要求7所述的半导体器件，还包括：
金属层，存在于所述开口的所述侧壁和所述阻挡层之间，其中，所述金属层不存在于所述硅化物和所述阻挡层之间。
9.一种互连结构，包括：
硅化物，存在于接触区上，其中，纹理化所述接触区和所述硅化物之间的界面，以及多个溅射残留物存在于所述硅化物中；
导体，存在于所述硅化物上；以及
阻挡层，存在于所述导体和所述硅化物之间。
10.一种制造互连结构的方法，所述方法包括：
在介电层中形成开口以暴露接触区的部分；
实施物理去除工艺以纹理化所述接触区的表面；
在所述接触区的被纹理化的所述表面上形成金属层；
在所述金属层上形成阻挡层；以及
实施退火工艺，其中，所述金属层与所述接触区反应从而在所述接触区和所述阻挡层之间形成硅化物。
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CN113130636B (zh) * 2021-04-15 2022-06-17 长鑫存储技术有限公司 半导体器件的制造方法及其半导体器件

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US11749603B2 (en) 2023-09-05
US10297548B2 (en) 2019-05-21
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US20220344274A1 (en) 2022-10-27
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