CN106328692A - 鳍式场效应晶体管(finfet)器件结构及其形成方法 - Google Patents
鳍式场效应晶体管(finfet)器件结构及其形成方法 Download PDFInfo
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- CN106328692A CN106328692A CN201610516949.6A CN201610516949A CN106328692A CN 106328692 A CN106328692 A CN 106328692A CN 201610516949 A CN201610516949 A CN 201610516949A CN 106328692 A CN106328692 A CN 106328692A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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Abstract
本发明提供了鳍式场效应晶体管(FinFET)器件结构及其形成方法。鳍式场效应晶体管(FinFET)器件结构包括在衬底上方形成的鳍结构和横越在鳍结构上方的栅极结构。该栅极结构包括栅电极层,所述栅电极层包括鳍结构之上的上部和鳍结构之下的下部。该上部具有第一宽度的顶面,该下部具有第二宽度的底面,并且第一宽度大于第二宽度。
Description
相关申请的交叉引用
本申请要求2015年7月2日提交的标题为“鳍式场效应晶体管(FinFET)器件结构及其形成方法”的美国临时申请第62/188,028号的权益,其全部内容结合于此作为参考。本申请涉及以下共同未决共同受让的美国专利申请:2015年11月16日提交的标题为“鳍式场效应晶体管(FinFET)器件结构及其形成方法”的序列号为14/942,491的申请,其全部内容结合于此作为参考。
(申请人案卷号P20150484US00)
技术领域
本发明的实施例涉及集成电路器件,更具体地,涉及鳍式场效应晶体管(FinFET)器件结构及其形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在材料层上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造许多集成电路,并且通过沿着划线在集成电路之间锯切来分割晶圆上的单独的管芯。例如,通常以多管芯模块或其它类型的封装分别封装单独的管芯。
随着半导体工业在追求更高的器件密度、更好的性能和更低的成本的过程中进入纳米技术工艺节点,来自制造和设计问题的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET由从衬底延伸的薄且垂直的“鳍”(或鳍结构)制造。在这个垂直鳍中形成FinFET的沟道。在鳍上方提供栅极结构。FinFET的优势可以包括减小短沟道效应和提供更高的电流。
虽然现有的FinFET器件和制造FinFET器件的方法对于它们的预期目的通常已经足够,但是它们不是在所有方面都已完全令人满意。
发明内容
本发明的实施例提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;以及栅极结构,横越在所述鳍结构上方,其中,所述栅极结构包括栅电极层,所述栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有第一宽度的顶面,并且所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
本发明的另一实施例提供了一种鳍式场效应晶体管(FinFET)器件结构,包括:鳍结构,形成在衬底上方;隔离结构,形成在所述衬底上方,其中,部分所述鳍结构嵌入在所述隔离结构内;以及第一栅极结构,横越在所述鳍结构上方,其中,部分所述第一栅极结构形成在所述隔离结构上方,其中,所述第一栅极结构包括第一栅电极层,所述第一栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有垂直的侧壁,以及所述下部具有倾斜的侧壁。
本发明的又一实施例提供了一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法,包括:在衬底上方形成鳍结构;在所述衬底上方形成隔离结构,其中,部分所述鳍结构嵌入在所述隔离结构内;以及在所述鳍结构和所述隔离结构上方形成栅极结构,其中,所述栅极结构包括栅电极层,所述栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有第一宽度的顶面,所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构的立体表示。
图2A至图2M示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的各个阶段的截面表示。
图3示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构的顶视图。
图4A至图4F示出了根据一些实施例的形成FinFET器件结构的各个阶段的截面表示。
图4D’示出了根据本发明的一些实施例的图4D的区域A的放大表示。
图5A至图5C示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的各个阶段的截面表示。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
描述了实施例的一些变化。贯穿各个视图和示例性实施例,相同的参考标号用于指定相同的元件。应该理解,可以在方法之前、期间和之后提供额外的操作,并且对于方法的其它实施例,可以代替或消除所描述的一些操作。
提供了用于形成鳍式场效应晶体管(FinFET)器件结构的实施例。图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的立体表示。
参照图1,提供了衬底102。衬底102可以由硅或其它半导体材料制成。可选地或额外地,衬底102可以包括诸如锗的其它元素半导体材料。在一些实施例中,衬底102由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中,衬底102由诸如硅锗、碳化硅锗、磷砷化镓或磷化镓铟的合金半导体制成。在一些实施例中,衬底102包括外延层。例如,衬底102具有位于块状半导体上面的外延层。
FinFET器件结构100也包括从衬底102延伸的一个或多个鳍结构104(例如,Si鳍)。鳍结构104可以可选择地包括锗。可以通过使用诸如光刻和蚀刻工艺的合适的工艺形成鳍结构104。在一些实施例中,使用干蚀刻或等离子体工艺从衬底102蚀刻鳍结构104。
诸如浅沟槽隔离(STI)结构的隔离结构108形成为围绕鳍结构104。在一些实施例中,如图1所示,鳍结构104的下部由隔离结构108围绕,并且隔离结构104的上部突出于隔离结构108。换句话说,部分鳍结构104嵌入在隔离结构108内。隔离结构108防止了电干扰或电串扰。
FinFET器件结构100还包括栅极堆叠结构,该栅极堆叠结构包括栅电极层144和栅极介电层142。在鳍结构104的中心部分上方形成栅极堆叠结构。在一些实施例中,在鳍结构104上方形成多个栅极堆叠结构。例如,覆盖层、界面层、间隔件元件和/或其它合适的部件的许多其它的层也可以存在于栅极结构中。
栅极介电层142可以包括诸如氧化硅、氮化硅、氮氧化硅、具有高介电常数(高k)的介电材料或它们的组合的介电材料。高k介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆等或它们的组合。
栅电极层144可以包括多晶硅或金属。该金属包括氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、钼(Mo)、铜(Cu)、钨(W)、铝(Al)、钴(Co)、锆(Zr)、铂(Pt)或其它适用的材料。可以在后栅极工艺(或栅极置换工艺)中形成栅电极层144。在一些实施例中,栅极堆叠结构包括诸如界面层、覆盖层、扩散/阻挡层或其它适用的层的额外层。
鳍结构104包括由栅电极层144和栅极介电层142围绕或包裹的沟道区域114。鳍结构104可以是掺杂的以提供用于n-型FinFET(NMOS器件)或p-型FinFET(PMOS器件)的合适的沟道。鳍结构104可以使用诸如离子注入工艺、扩散工艺、退火工艺、其它适用的工艺或它们的组合的合适的工艺掺杂。鳍结构104包括位于源极区域112和漏极区域116之间的沟道区域114。FinFET器件100可以是包括在微处理器、存储单元(例如,静态随机存取存储器(SRAM))和/或其它集成电路中的器件。
图2A至图2M示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面表示。
参照图2A,在衬底102上形成介电层204和硬掩模层206,并且在硬掩模层206上形成光刻胶层208。通过图案化工艺图案化光刻胶层208。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺包括光刻胶涂布(例如,旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗和干燥(例如,硬烘烤)。蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。
介电层204是衬底102和硬掩模层206之间的缓冲层。此外,当去除硬掩模层206时,使用介电层204作为停止层。介电层204可以由氧化硅制成。硬掩模层206可以由氧化硅、氮化硅、氮氧化硅或另一适用的材料制成。在一些其它实施例中,在介电层204上形成多于一个的硬掩模层206。
通过诸如化学汽相沉积(CVD)、高密度等离子体化学汽相沉积(HDPCVD)工艺、旋涂工艺、溅射工艺或其它适用的工艺的沉积工艺形成介电层204和硬掩模层206。
根据一些实施例,如图2B所示,在图案化光刻胶层208之后,通过使用图案化的光刻胶层208作为掩模来图案化介电层204和硬掩模层206。因此,获得了图案化的介电层204和图案化的硬掩模层206。之后,去除图案化的光刻胶层208。
之后,通过使用图案化的介电层204和图案化的硬掩模层206作为掩模,对衬底102实施蚀刻工艺以形成鳍结构104。蚀刻工艺可以是干蚀刻工艺或湿蚀刻工艺。蚀刻工艺可以是时控工艺,并且持续至鳍结构104到达预定的高度。
应该注意,鳍结构104的数量可以根据实际应用调整,并且不限于一个鳍结构104。在一些实施例中,鳍结构104的宽度从上部至下部逐渐增加。
之后,根据一些实施例,如图2C所示,在鳍结构104上形成介电材料107。在一些实施例中,介电材料107由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)或其它低k介电材料制成。可以通过化学汽相沉积(CVD)工艺、旋涂玻璃工艺或其它适用的工艺沉积介电材料107。
之后,根据一些实施例,如图2D所示,削薄或平坦化介电材料107以形成隔离结构108。在一些实施例中,通过化学机械抛光(CMP)工艺削薄介电材料107。因此,暴露了鳍结构104的顶部,并且去除了介电层204和硬掩模层206。隔离结构108的顶面与鳍结构104的顶面齐平。
之后,根据一些实施例,如图2E所示,去除隔离结构108的顶部。因此,鳍结构104突出于隔离结构108。换句话说,鳍结构104的顶部高于隔离结构108。隔离结构108的顶部可以通过湿蚀刻工艺或干蚀刻工艺去除。剩余的隔离结构108被看作浅沟槽隔离(STI)结构。
之后,根据一些实施例,如图2F所示,在鳍结构104和隔离结构108上方形成伪栅电极层110。
在一些实施例中,伪栅电极层110由导电或非导电材料制成。在一些实施例中,伪栅电极层110由多晶硅制成。通过诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HPDCVD)、金属有机物CVD(MOCVD)或等离子体增强CVD(PECVD)的沉积工艺形成伪栅电极层110。
根据一些实施例,如图2G所示,在形成伪栅电极层110之后,在伪栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。在第二硬掩模层212b上方形成光刻胶层214。之后,图案化光刻胶层214以形成图案化的光刻胶层214。图案化的光刻胶层214用于保护下面的层免受随后的工艺期间的蚀刻的损害。
之后,根据一些实施例,如图2H所示,图案化第一硬掩模层212a和第二硬掩模层212b,并且去除部分伪栅电极层110以形成伪栅极结构110’。通过诸如湿蚀刻工艺或干蚀刻工艺的蚀刻工艺121去除部分伪栅电极层110。
伪栅极结构110’包括鳍结构104的顶面之上的上部110a和鳍结构104的顶面之下的下部110b。上部110a具有垂直的侧壁,以及下部110b具有倾斜的侧壁。下部110b具有梯形形状(如图4D’所示)。
上部110a具有第一宽度W1的顶面,并且下部110b具有第二宽度W2的底面。下部110b具有从下部的底面至下部的顶面逐渐变细的锥形宽度。
在上部110a和下部110b之间形成了虚拟界面。虚拟界面具有第三宽度W3。在一些实施例中,第一宽度W1大于第二宽度W2。在一些实施例中,第三宽度W3小于或等于第二宽度W2。在一些实施例中,第二宽度W2和第三宽度W3之间的差(ΔW=W2-W3)在从约0nm至约15nm的范围内。如果该差(ΔW)大于15nm,则栅电极层144(如图2M所示)可能难以填充至通过去除伪栅电极层110形成的沟槽138(如图2L所示)。如果该差小于0nm,则可能难以形成源极/漏极(S/D)结构116(如图2J所示)。
虚拟界面用于限定两部分并且在上部110a和下部110b之间没有形成真实的界面。该界面可以看作是上部110a的底面。此外,该界面可以看作是下部110b的顶面。在一些实施例中,虚拟界面与鳍结构104的顶面基本齐平。
如果伪栅极结构110’的上部具有在水平方向上延伸的部分,则当伪栅极结构110’由栅极结构代替时,栅极结构可以突出。突出的栅极结构可以与邻近于突出的栅极结构形成的接触结构接触。因此,可能产生电短路问题。更具体地,栅电极层144的突出问题可能降低FinFET器件结构100的性能。
衬底102是部分晶圆。在一些实施例中,该晶圆包括中心区域和边缘区域,并且与中心区域相比,在晶圆的边缘区域中加剧了突出问题。因此,应该良好地控制边缘区域中的蚀刻气体。
如图2H所示,为了解决突出问题,蚀刻伪栅极结构110’以形成垂直的上部110a和位于鳍结构104之下的有凹口的下部110b。换句话说,伪栅极结构110’的有凹口的下部110b具有凹进的侧壁部分。
上部110a具有第一高度H1,并且下部110b具有第二高度H2。在一些实施例中,第一高度H1大于第二高度H2。
根据一些实施例,如图2I所示,在形成伪栅极结构110’之后,在伪栅极结构110’的相对侧壁上形成间隔件212。在一些实施例中,间隔件212由氮化硅、碳化硅、氮氧化硅、硅碳、氧化硅、硅氢、其它适用的材料或它们的组合制成。
之后,根据一些实施例,如图2J所示,去除鳍结构104的顶部以形成凹槽(未示出),并且在凹槽中形成源极/漏极(S/D)结构116。
在一些实施例中,S/D结构116是应变的源极/漏极结构。在一些实施例中,通过外延(epi)工艺在鳍结构104的凹槽中生长应变材料形成S/D结构116。此外,应变材料的晶格常数与衬底102的晶格常数不同。
在一些实施例中,源极/漏极结构116包括Ge、SiGe、InAs、InGaAs、InSb、GaAs、GaSb、InAlP、InP或它们的组合。外延工艺可以包括选择性外延生长(SEG)工艺、CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延或其它合适的外延工艺。
在一些实施例中,在形成S/D结构116之后,在S/D结构116和伪栅极结构110’上形成接触蚀刻停止层(CESL)(未示出)。在一些实施例中,接触蚀刻停止层由氮化硅、氮氧化硅和/或其它适用的材料制成。可以通过等离子体增强CVD、低压CVD、ALD或其它适用的工艺形成接触蚀刻停止层。
之后,根据一些实施例,如图2K所示,在衬底102上方的鳍结构104上方形成层间介电(ILD)材料。在一些实施例中,层间介电(ILD)材料形成在隔离结构108上方并且之后平坦化以形成ILD结构136。
根据一些实施例,如图2L所示,在形成ILD结构136之后,通过在ILD结构136中形成沟槽138去除伪栅极结构110’。通过实施蚀刻工艺去除伪栅极结构110’。应该注意,没有去除鳍结构104,并且因此鳍结构104的中间部分由沟槽138暴露。
根据一些实施例,如图2M所示,在形成沟槽138之后,在沟槽138中依次形成栅极介电层142和栅电极层144。因此,获得了包括栅极介电层142和栅电极层144的栅极结构146。
栅极介电层142具有高于鳍结构104的顶面的上部和低于鳍结构104的顶面的下部。
在一些实施例中,栅极介电层142由高k介电材料制成。高k介电材料可以包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆等。
栅电极层144具有高于鳍结构104的顶面的上部和低于鳍结构104的顶面的下部。栅电极层144的上部具有恒定的宽度,以及栅电极层144的下部具有变化的宽度。
在一些实施例中,栅电极层144由金属材料制成。金属材料可以包括N功函金属或P功函金属。N功函金属包括钨(W)、铜(Cu)、钛(Ti)、银(Ag)、铝(Al)、钛铝合金(TiAl)、氮化钛铝(TiAlN)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、锰(Mn)、锆(Zr)或它们的组合。P功函金属包括氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)、钌(Ru)或它们的组合。
如图2M所示,栅电极层144具有上部144a和下部144b。上部144a具有垂直的侧壁,以及下部144b具有倾斜的侧壁。下部144b具有从下部144b的底面至下部144b的顶面逐渐变细的锥形宽度。应该注意,栅电极层144的上部144a具有垂直的侧壁以防止突出部分的产生。因此,改进了FinFET结构100的性能。
栅电极层144的上部144a具有第一高度,以及栅电极层144的下部144b具有第二高度。第一高度大于第二高度以在鳍结构104之上填充更多金属材料。
上部144a具有第一宽度的顶面,并且下部144b具有第二宽度的底面。第一宽度大于第二宽度。应该注意,当第一宽度大于第二宽度时,防止了漏致势垒降低(DIBL)效应的产生。此外,当第一宽度大于第二宽度时,防止了击穿电压(Vbd)的拖尾问题(在电压值的更宽范围传播Vbd)的产生。
图3示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的顶视图。FinFET器件结构100包括多个鳍结构104和多个栅极结构110。栅极结构110横越在鳍结构104上方。FinFET器件结构100由隔离结构108围绕。
如图3所示,鳍结构104可以基本彼此平行。栅极结构110也可以彼此平行并且基本垂直于鳍结构104。在一些实施例中,当从顶视图看时,栅极结构110也称为栅电极线。
在第一鳍结构104a上方形成第一栅极晶体管300a和第二栅极晶体管300b。在第二鳍结构104b上方形成第三栅极晶体管300c和第四栅极晶体管300d。
图4A至图4F示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面表示。图4A至图4F示出了沿着图3的AA’线的截面表示。
参照图4A,在第一鳍结构104a、第二鳍结构104b和隔离结构108上方形成栅电极层110。隔离结构108的顶面低于鳍结构104a、104b的顶面。之后,在栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。
根据本发明的一些实施例,如图4B所示,在形成第二硬掩模层212b之后,在第二硬掩模层212b上方形成光刻胶层214。之后,图案化光刻胶层214。
根据本发明的一些实施例,如图4C所示,在图案化光刻胶层214之后,图案化部分第一硬掩模层212a和部分第二硬掩模层212b以形成沟槽352。
根据本发明的一些实施例,如图4D所示,在形成沟槽352之后,通过使用第一硬掩模层212a和第二硬掩模层212b作为掩模来图案化部分栅电极层110。因此,在鳍结构104之上和栅电极层110中形成第一沟槽354。在隔离结构108之上和栅电极层110中形成第二沟槽356。
通过蚀刻工艺121去除部分栅电极层110。在一些实施例中,蚀刻工艺是等离子体工艺。等离子体工艺包括使用诸如HBr的蚀刻气体。在一些实施例中,氦(He)气和氧(O2)气也用于等离子体工艺中。蚀刻工艺中的蚀刻气体的流量在从约700sccm至约1000sccm的范围内。如果流量小于700sccm,则蚀刻选择性差。如果流量大于1000sccm,则可能难以控制蚀刻速率。
在一些实施例中,在从约350瓦至约1500瓦的范围内的功率下实施等离子体工艺。如果功率小于350W,则蚀刻选择性差。如果功率大于1500W,则可能难以控制蚀刻速率。在一些实施例中,在从约10托至约100托的范围内的压力下实施等离子体工艺。如果压力小于10托,则蚀刻选择性差。如果压力大于100托,则可能难以控制蚀刻速率。
应该注意,衬底102是部分晶圆,并且该晶圆包括中心区域和边缘区域。与晶圆的中心区域相比,更难以控制晶圆的边缘区域中的第二宽度W2的尺寸。在一些实施例中,为了使第二宽度W2大于或等于第三宽度W3,边缘区域中的蚀刻气体的量和整个区域中的蚀刻气体的量的体积比在从约10%至约50%的范围内。如果蚀刻气体的体积比小于10%或大于50%,则可能增加中心区域和边缘区域之间的负载效应,并且因此难以控制第一宽度W1或第二宽度W2的尺寸。
图4D’示出了根据本发明的一些实施例的图4D的区域A的放大表示。如图4D’所示,栅电极层110包括上部110a和下部110b。上部110a位于高于鳍结构104a、104b的顶面的位置处。下部110b位于低于鳍结构104a、104b的顶面的位置处。栅电极层110的上部110a具有垂直的侧壁以及栅电极层110的下部110b具有倾斜的侧壁。
在上部110a和下部110b之间形成界面。该界面不是真实的边界并且用于限定栅电极层110的形状。该界面可以看作是上部110a的底面。此外,该界面可以看作是下部110b的顶面。
上部110a具有均匀的宽度,以及下部110b具有变化的宽度。上部110a具有第一宽度W1,界面具有第三宽度W3。下部110b的底面具有第二宽度W2。在一些实施例中,第一宽度W1大于第二宽度W2,并且第二宽度W2大于第三宽度W3。在一些实施例中,第二宽度W2和第三宽度W3之间的差(ΔW=W2-W3)在从约0nm至约15nm的范围内。如果该差(ΔW)大于15nm,则栅电极层144可能难以填充至通过去除伪栅电极层110形成的沟槽138(如图2L所示)。如果该差小于0nm,则可能难以形成源极/漏极(S/D)结构116。
之后,去除第一硬掩模层212a和第二硬掩模层212b,并且在栅电极层110的相对侧壁上形成间隔件212。下一步,根据本发明的一些实施例,如图4E所示,介电材料填充至沟槽354、356中和作为掩模的栅电极层110上。
在填充介电材料之后,通过诸如化学机械抛光(CMP)工艺的平坦化工艺去除位于沟槽354、356之外的部分介电材料。因此,形成了ILD结构136。在两个邻近的栅电极层110之间形成ILD结构136,并且ILD结构136包括上部和下部,下部宽于上部。
之后,根据本发明的一些实施例,如图4F所示,去除栅电极层110以形成沟槽(未示出),并且在沟槽中依次形成栅极介电层142和栅电极144。在一些实施例中,栅极介电层142是高介电常数(高k)介电层,并且栅电极144是金属栅电极。换句话说,在鳍结构104上形成HK/MG堆叠结构。
如图4F所示,栅极介电层142和栅电极144被分为四个部分,并且分别形成第一晶体管300a、第二晶体管300b、第三晶体管300c和第四晶体管300d。每个第一晶体管300a、第二晶体管300b、第三晶体管300c和第四晶体管300d均由栅极介电层142和栅电极144构建。ILD结构136位于第一晶体管300a和第二晶体管300b之间。此外,ILD结构136位于第三晶体管300c和第四晶体管300d之间。
图5A至图5C示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面表示。图5A至图5C示出了沿着图3的BB’线的截面表示。
如图5A所示,在栅电极层110上方形成第一硬掩模层212a和第二硬掩模层212b。
之后,根据本发明的一些实施例,如图5B所示,图案化第一硬掩模层212a和第二硬掩模层212b以形成图案化的第一硬掩模层212a和图案化的第二硬掩模层212b。
之后,根据本发明的一些实施例,如图5C所示,通过使用图案化的第一硬掩模层212a和图案化的第二硬掩模层212b作为掩模蚀刻栅电极层110以形成上部110a和下部110b。上部110a位于鳍结构104的顶面之上,并且下部110b位于鳍结构104的顶面之下。上部110a具有垂直的侧壁以防止突出问题的产生。
上部110a具有第一宽度的顶面,并且下部110b具有第二宽度的底面。第一宽度大于第二宽度。应该注意,当第一宽度大于第二宽度时,防止了漏致势垒降低(DIBL)效应的产生。此外,当第一宽度大于第二宽度时,防止了击穿电压(Vbd)的拖尾问题(在电压值的更宽范围传播Vbd)的产生。
之后,如果栅电极层110由多晶硅制成,则将去除栅电极层110并且由金属栅电极层代替。
提供了形成半导体器件结构的实施例及其形成方法。FinFET器件结构包括在衬底上方形成的鳍结构和在鳍结构上方形成的栅极结构。该栅极结构包括上部和下部。该上部具有顶面并且该下部具有底面。该顶面宽于该底面。该上部具有垂直的侧壁以防止突出问题的产生。因此,改进了FinFET器件结构的性能和可靠性。
在一些实施例中,提供了鳍式场效应晶体管(FinFET)器件结构。该鳍式场效应晶体管(FinFET)器件结构包括在衬底上方形成的鳍结构和横越在鳍结构上方的栅极结构。该栅极结构包括栅电极层,该栅电极层包括鳍结构之上的上部和鳍结构之下的下部,该上部具有第一宽度的顶面,并且该下部具有第二宽度的底面,并且第一宽度大于第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,在所述上部和所述下部之间形成虚拟界面,并且所述虚拟界面具有第三宽度,并且所述第三宽度小于或等于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述虚拟界面与所述鳍结构的顶面基本齐平。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述栅电极层的所述上部具有垂直的侧壁。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述栅电极层的所述下部具有梯形形状。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述栅电极层的所述上部具有第一高度,并且所述栅电极层的所述下部具有第二高度,并且所述第一高度大于所述第二高度。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:隔离结构,形成在所述衬底上方,其中,部分所述栅极结构形成在所述隔离结构上方。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述下部具有从所述下部的所述底面至所述下部的顶面逐渐变细的锥形宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述栅电极层的所述下部具有倾斜的侧壁。
在一些实施例中,提供了鳍式场效应晶体管(FinFET)器件结构。该鳍式场效应晶体管(FinFET)器件结构包括在衬底上方形成的鳍结构和在衬底上方形成的隔离结构。部分鳍结构嵌入在隔离结构内。该鳍式场效应晶体管(FinFET)器件结构也包括横越在鳍结构上方的第一栅极结构,并且在隔离结构上方形成了部分第一栅极结构。第一栅极结构包括栅电极层,该栅电极层包括鳍结构之上的上部和鳍结构之下的下部,该上部具有垂直的侧壁,以及该下部具有倾斜的侧壁。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述第一栅电极层的所述上部具有第一高度,并且所述第一栅电极层的所述下部具有第二高度,并且所述第一高度大于所述第二高度。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述上部具有第一宽度的顶面,并且所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,其中,所述上部具有第一宽度的顶面,并且所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度,在所述上部和所述下部之间形成虚拟界面,并且所述虚拟界面具有第三宽度,并且所述第三宽度小于或等于所述第二宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:第二栅极结构,横越在所述鳍结构上方,其中,部分所述第二栅极结构形成在所述隔离结构上方;以及层间介电(ILD)结构,形成在所述第一栅极结构和所述第二栅极结构之间,其中,所述ILD结构包括上部和下部,并且所述下部宽于所述上部。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:第二栅极结构,横越在所述鳍结构上方,其中,部分所述第二栅极结构形成在所述隔离结构上方;以及层间介电(ILD)结构,形成在所述第一栅极结构和所述第二栅极结构之间,其中,所述ILD结构包括上部和下部,并且所述下部宽于所述上部,其中,所述ILD结构的所述上部具有恒定的宽度,以及所述ILD结构的所述下部具有变化的宽度。
在上述鳍式场效应晶体管(FinFET)器件结构中,还包括:第二栅极结构,横越在所述鳍结构上方,其中,部分所述第二栅极结构形成在所述隔离结构上方;以及层间介电(ILD)结构,形成在所述第一栅极结构和所述第二栅极结构之间,其中,所述ILD结构包括上部和下部,并且所述下部宽于所述上部,其中,所述ILD结构的所述上部具有恒定的宽度,以及所述ILD结构的所述下部具有变化的宽度,所述ILD结构的所述下部具有从所述下部的顶面至所述下部的底面逐渐变细的倾斜的侧壁。
在一些实施例中,提供了用于形成鳍式场效应晶体管(FinFET)器件结构的方法。该方法包括在衬底上方形成鳍结构以及在衬底上方形成隔离结构。部分鳍结构嵌入在隔离结构内。该方法包括在鳍结构和隔离结构上方形成栅极结构,并且该栅极结构包括栅电极层,该栅电极层包括鳍结构之上的上部和鳍结构之下的下部。该上部具有第一宽度的顶面,并且该下部具有第二宽度的底面,并且第一宽度大于第二宽度。
在上述方法中,其中,在所述鳍结构和所述隔离结构上方形成所述栅极结构包括:在所述鳍结构和所述隔离结构上方形成栅极材料;在所述栅极材料上方形成硬掩模层;图案化所述硬掩模层;通过使用所述硬掩模层作为掩模蚀刻所述栅极材料以形成所述栅极结构。
在上述方法中,其中,在所述鳍结构和所述隔离结构上方形成所述栅极结构包括:在所述鳍结构和所述隔离结构上方形成栅极材料;在所述栅极材料上方形成硬掩模层;图案化所述硬掩模层;通过使用所述硬掩模层作为掩模蚀刻所述栅极材料以形成所述栅极结构,蚀刻所述栅极材料包括使用蚀刻工艺,并且在约10托至约100托的范围内的压力下实施所述蚀刻工艺。
在上述方法中,其中,还包括:在所述衬底上方并且邻近于所述栅极结构形成层间介电(ILD)结构;去除所述栅极结构以在所述ILD结构中形成沟槽;以及在所述沟槽中填充栅极介电层和栅电极层。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种鳍式场效应晶体管(FinFET)器件结构,包括:
鳍结构,形成在衬底上方;以及
栅极结构,横越在所述鳍结构上方,其中,所述栅极结构包括栅电极层,所述栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有第一宽度的顶面,并且所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
2.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,在所述上部和所述下部之间形成虚拟界面,并且所述虚拟界面具有第三宽度,并且所述第三宽度小于或等于所述第二宽度。
3.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述虚拟界面与所述鳍结构的顶面基本齐平。
4.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的所述上部具有垂直的侧壁。
5.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的所述下部具有梯形形状。
6.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述栅电极层的所述上部具有第一高度,并且所述栅电极层的所述下部具有第二高度,并且所述第一高度大于所述第二高度。
7.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,还包括:
隔离结构,形成在所述衬底上方,其中,部分所述栅极结构形成在所述隔离结构上方。
8.根据权利要求1所述的鳍式场效应晶体管(FinFET)器件结构,其中,所述下部具有从所述下部的所述底面至所述下部的顶面逐渐变细的锥形宽度。
9.一种鳍式场效应晶体管(FinFET)器件结构,包括:
鳍结构,形成在衬底上方;
隔离结构,形成在所述衬底上方,其中,部分所述鳍结构嵌入在所述隔离结构内;以及
第一栅极结构,横越在所述鳍结构上方,其中,部分所述第一栅极结构形成在所述隔离结构上方,其中,所述第一栅极结构包括第一栅电极层,所述第一栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有垂直的侧壁,以及所述下部具有倾斜的侧壁。
10.一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法,包括:
在衬底上方形成鳍结构;
在所述衬底上方形成隔离结构,其中,部分所述鳍结构嵌入在所述隔离结构内;以及
在所述鳍结构和所述隔离结构上方形成栅极结构,其中,所述栅极结构包括栅电极层,所述栅电极层包括所述鳍结构之上的上部和所述鳍结构之下的下部,所述上部具有第一宽度的顶面,所述下部具有第二宽度的底面,并且所述第一宽度大于所述第二宽度。
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KR101833184B1 (ko) | 2018-02-27 |
US11854825B2 (en) | 2023-12-26 |
KR20170130327A (ko) | 2017-11-28 |
TWI647748B (zh) | 2019-01-11 |
DE102016100033B4 (de) | 2022-02-17 |
US20170005165A1 (en) | 2017-01-05 |
CN106328692B (zh) | 2020-04-17 |
US11309189B2 (en) | 2022-04-19 |
US10262870B2 (en) | 2019-04-16 |
US20200357655A1 (en) | 2020-11-12 |
US20190244830A1 (en) | 2019-08-08 |
DE102016100033A1 (de) | 2017-01-05 |
US10741408B2 (en) | 2020-08-11 |
TW201703122A (zh) | 2017-01-16 |
KR20170004828A (ko) | 2017-01-11 |
US20220246441A1 (en) | 2022-08-04 |
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