CN102437088B - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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CN102437088B
CN102437088B CN201010296962.8A CN201010296962A CN102437088B CN 102437088 B CN102437088 B CN 102437088B CN 201010296962 A CN201010296962 A CN 201010296962A CN 102437088 B CN102437088 B CN 102437088B
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source
drain region
layer
amorphous compound
contact hole
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CN102437088A (zh
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尹海洲
骆志炯
朱慧珑
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Institute of Microelectronics of CAS
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Priority to US13/380,654 priority patent/US8541280B2/en
Priority to PCT/CN2011/072912 priority patent/WO2012041056A1/zh
Priority to CN2011900000675U priority patent/CN202601575U/zh
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Abstract

本发明提供一种半导体结构的制造方法，该方法包括以下步骤：在半导体衬底(101)上沉积层间介质层(105)，以覆盖源/漏区(102)以及位于所述半导体衬底上的栅极堆叠；刻蚀所述层间介质层以及源/漏区形成到达源/漏区内部的接触孔(110)；在所述源/漏区的暴露区域上形成共形的非晶化物层(111)；在所述非晶化物层(111)表面形成金属硅化物层(113)；在接触孔(110)中填充接触金属(114)。相应地，本发明还提供一种半导体结构。本发明通过刻蚀源/漏区，使其暴露区域包括底部以及侧壁，增大了接触孔中接触金属和源/漏区的接触面积，从而减小了接触电阻；采用选择性沉积的方式形成非晶化物，有效地消除了由非晶化离子注入所引起的末端缺陷。

Description

一种半导体结构及其制造方法
技术领域
本发明涉及半导体制造技术，尤其涉及一种半导体结构及其制造方法。
背景技术
随着半导体行业的发展，具有更高性能和更强功能的集成电路要求更大的元件密度，而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小。相应地，源/漏区与金属电极相接触的面积也被缩小，由于在传统的源/漏区与金属电极接触面之间的接触电阻率较大，这种缩小的接触面积导致接触电阻的显著增加。
在现有技术美国专利申请US2010/010904A1中提出一种降低源/漏区接触电阻的方法，解决上述问题增加源/漏区的导电性该方法的步骤如下：
采用离子注入的方式，通过接触孔对源/漏区进行预非晶化处理，形成局部非晶硅区域；
用硼对源/漏区进行掺杂离子注入；
然后在接触孔底部非晶化的区域镀上一层金属；
执行退火使得金属与非晶硅接触的部分发生反应形成金属硅化物层，而金属硅化物下层还残余有未发生反应的非晶硅；
接着除去未发生硅化的多余的金属，并填充金属电极。
由于在源/漏区与金属电极之间存在金属硅化物与非晶硅层的过渡能够有效地降低源/漏区与金属电极之间的电阻率，进而减小接触电阻。
但是，上述方法虽然能降低源/漏区的接触电阻，但是在非晶化过程中采用离子注入的方式，然后进行退火，会导致较多缺陷，例如在再结晶退火结束时在紧邻位于再结晶层的下面区域中产生末端（End-of-Range, EOR）型缺陷。这些 EOR 缺陷是因为结晶缺陷产生的，其在非晶化步骤中出现并在再结晶步骤中发展。这些 EOR 缺陷严重恶化了电气性能，特别是衬底的载流子迁移率，从而使得这些衬底不适合用来制作电子元件。并且，现有技术工艺中仅仅在接触孔底部形成金属硅化物，随着器件尺寸减小，接触孔底部面积也减小，从而接触电阻增加。因此，在半导体器件尺寸变小的趋势下，如何有效地增大半导体的接触面积、减小接触电阻就成了亟待解决的问题。
发明内容
本发明的目的是提供一种半导体结构及其制造方法，利于减小接触电阻。
根据本发明的一个方面，提供一种半导体结构的制造方法，该方法包括以下步骤：
在半导体衬底上沉积层间介质层，以覆盖源/漏区以及位于所述半导体衬底上的栅极堆叠；
刻蚀所述层间介质层以及源/漏区，以暴露所述源/漏区中部分区域并形成到达源/漏区内部的接触孔；
在所述源/漏区的暴露区域上形成共形的非晶化物层；
在所述非晶化物层表面形成金属硅化物层；
在接触孔中填充接触金属。
本发明另一方面还提出一种半导体结构，包括：
半导体衬底；
栅极堆叠，其形成于所述半导体衬底上；
源/漏区，其形成于半导体衬底中；
层间介质层，其覆盖所述栅极堆叠和所述源/漏区；
接触孔，其贯穿所述层间介质层并延伸到所述源/漏区内部；
接触金属，其填充所述接触孔；
所述接触金属延伸入所述源/漏区内的部分与源/漏区之间在侧壁和底部存在共形的金属硅化物层。
与现有技术相比，本发明具有以下优点：
通过刻蚀源/漏区，使其暴露区域包括底部以及侧壁，增大了接触孔中接触金属和源/漏区的接触面积，从而减小了接触电阻；采用在所述源/漏区的暴露区域上形成共形的非晶化物层的方式代替非晶化离子注入形成非晶化物，利于减少由非晶化离子注入所引起的末端缺陷(EOR缺陷)，进而利于减少漏电流的产生。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为根据本发明的半导体结构制造方法的流程图；
图2A至图2E为根据本发明的一个优选实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
参考图1和图2A-2E，图2A为图1中所示的步骤开始之前已经形成的半导体结构的剖面示意图。所述半导体结构包括：半导体衬底101；在半导体衬底101上形成的栅极堆叠，栅极堆叠包括栅极介质层104和金属栅层103；在栅极堆叠侧壁上形成的侧墙106；以及在栅极堆叠的两侧的源/漏区102。接着，在图1的步骤S101中，在半导体衬底101上沉积层间介质层105，层间介质层105覆盖源/漏区102以及位于所述半导体衬底101上部的栅极堆叠(包括栅极介质层104和金属栅层103)，如图2A所示。在本实施例中，半导体衬底101包括硅衬底(例如晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底)，半导体衬底101可以包括各种掺杂配置。其他例子的半导体衬底101还可以包括其他基本半导体，例如锗。或者，半导体衬底101可以包括化合物半导体，例如碳化硅、砷化镓、砷化铟或者磷化铟。典型地，半导体衬底101可以是但不限于约几百微米，例如从400um-800um的厚度范围。
源/漏区102可以通过向半导体衬底101中注入P型或N型掺杂物或杂质而形成，例如，对于PMOS来说，源/漏区102可以是P型掺杂的SiGe，对于NMOS来说，源/漏区102可以是N型掺杂的Si。源/漏区102可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成，且可以先于栅极介质层形成。在本实施例中，源/漏区102可以是通过选择性生长所形成的提升的源漏极结构，其外延部分的顶部107高于栅极堆叠底部（本文件内，栅极堆叠底部意指栅极堆叠与半导体衬底101的交界线）。
栅极堆叠包括栅极介质层104以及金属栅层103。栅极介质层104位于半导体衬底101上，其可以是热氧化层，包括氧化硅、氮氧化硅，也可为高K介质，例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极介质层104的厚度可以为2nm -10nm，如5nm或8nm。而后在所述栅极介质层104上形成金属栅层103，例如通过沉积TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合来形成，厚度可以为10nm -80nm，如30nm或50nm。特别地，在栅极的两个侧壁上形成侧墙106，用于将栅极隔开。侧墙106可以由氮化硅、氧化硅、氮氧化硅、碳化硅、及其组合，和/或其他合适的材料形成。侧墙106可以具有多层结构。侧墙106可以通过包括沉积-刻蚀工艺形成，其厚度范围可以是10nm -100nm，如30nm、50nm或80nm。
层间介质层105可以通过化学气相沉积（CVD）、高密度等离子体CVD、旋涂或其他合适的方法形成在半导体衬底101上，覆盖提升的源/漏区102、栅极以及侧墙106。层间介质层105可以包括掺杂或未掺杂的氧化硅玻璃、氮氧化硅或者其他低k材料。层间介质层105的厚度范围可以是40nm -150nm，如80nm、100nm或120nm。
接着，执行步骤S102，刻蚀所述层间介质层105以及源/漏区102，以暴露所述源/漏区102中部分区域并形成到达源/漏区102内部的接触孔110，如图2B所示。形成层间介质层105后，刻蚀部分层间介质层105以及部分源/漏区102，以形成一接触孔开口110。对于采用提升源/漏区的情况，可以只刻蚀到源/漏区的提升部分，即刻蚀到源/漏区内部的深度控制到与栅极堆叠底部齐平为止（本文件内，术语“齐平”意指两者之间的高度差在工艺误差允许的范围内），对于采用提升的源漏区以改善器件沟道区应力的方案，利于在减小接触电阻的同时，使刻蚀源漏区的操作造成的应力损失尽量小。在其他实施例中，也可以刻蚀到暴露的源/漏区表面位于栅极堆叠底部上方或下方。为了准确地控制刻蚀源/漏区的深度，可以在形成源/漏区的提升部分之前，在源/漏区中与栅极堆叠底部齐平的位置上形成蚀刻阻挡层（例如，5nm厚的硅），然后在该蚀刻阻挡层上形成源/漏区的提升部分。对于PMOS来说，源/漏区中低于栅极堆叠的部分可以为SiGe、蚀刻阻挡层可以为硅层、源/漏区的提升部分可以是SiGe，并且各部分都是P型掺杂；对于NMOS来说，源/漏区中低于栅极堆叠的部分可以硅或SiC、蚀刻阻挡层可以是硅层、源/漏区的外延部分可以是SiGe，并且各部分都是N型掺杂。
刻蚀后形成的接触孔110可以具有上大下小的锥形结构，该接触孔110暴露的源/漏区102包括接触孔110的底部108和由所述底部延伸的部分侧壁109。对于提升源/漏区的情况来说，其底部108与栅极介质层104的底部可在同一水平面内。刻蚀提升源/漏区102的提升部分，将有效地增大了提升源/漏区102暴露区域与金属硅化物的接触面积，从而减小接触电阻。在接触孔的刻蚀中，一般采用干式刻蚀来进行。
对于非提升的源/漏区102，其顶部与栅极介质层在同一水平面内，亦可以采用上述方式对源/漏区进行刻蚀，形成具有底部和侧壁结构的暴露区域，增大接触面积。再以上述提升的源/漏区102中描述的方法形成非晶化物层111，并对所述非晶化物层111进行掺杂，可构成本发明方法的其他实施例。
在步骤S103中，选择性沉积非晶化物至所述源/漏区102的暴露区域，形成共形的非晶化物层111，如图2C所示。根据具体应用情况，该非晶化物层111可以是非晶化硅、非晶化SiGe或者非晶化SiC。通常来说，如果源/漏区102的材料是硅、SiGe或SiC，则相应选择沉积的非晶化物为非晶化硅、非晶化SiGe或者非晶化SiC。所述沉积方法可以是PVD（物理气相沉积）、CVD（化学气相沉积）、ALD（原子层沉积）等等，选择性沉积非晶化物，在源/漏区102暴露的底部108和侧壁109形成非晶化物层111。在此采用沉积方法而不是离子注入方法来形成非晶化物层111的优点在于，沉积方法可在接触孔底部和侧壁均匀地形成共形的非晶化物层111；而离子注入方法通常具有方向性，只能在接触孔110底部形成非晶化物层111，或者底部形成的非晶化物层111比侧壁上形成的非晶化物层更厚。另外，如上文所述，用离子注入来形成非晶化物层111会导致较多的缺陷。因此，在本发明中优先采用沉积方法来形成非晶化物层111。
在此所述的“共形”是指非晶化物层111厚度均匀并与接触孔110底部和侧壁的形状一致。该非晶化物层111的厚度通常为10nm -30nm，如15nm、20nm或25nm。
除了采用沉积工艺形成非晶化物层111之外，可选地，还可以通过外延生长工艺在所述提升源/漏区102暴露区域的底部和侧壁形成共形非晶化物层111。具体地，在外延生长的同时，可在气体源中掺入含有砷、硼、碳或磷等掺杂元素的气体，利于减小非晶化物层111的电阻率，进而在其上形成接触孔，并以金属填充所述接触孔以形成接触塞时，利于减小所述接触塞与源/漏区102间的接触电阻。
在执行完步骤S103后，可选地，从接触孔开口110对非晶化物层111进行掺杂离子注入112。具体地，对于N型半导体器件，使用III族元素进行离子注入，例如硼和铟；对于P型半导体器件，使用V族元素进行例子注入，例如，砷和磷。可以采用的离子注入能量的范围大约为3keV -25keV，剂量大约为1e14-2e15，注入的深度范围大约为10nm -30nm。其中，执行离子注入操作时的各工艺参数与所述非晶化物层111的厚度及注入离子的种类相关，本领域技术人员可根据上述教导灵活选取适合的工艺参数。
特别地，对于非提升的源/漏区，在形成层间介质层105之前，也可在所述源/漏区上沉积非晶化物层111，可以PVD、CVD或ALD工艺执行所述沉积操作，也可外延生长所述非晶化物层111，则在形成接触孔后，所述接触孔可嵌于所述非晶化物层111中，通过在所述接触孔和所述源/漏区之间形成所述非晶化物层111作为过渡层，利于减小所述接触塞与源/漏区间的接触电阻。其中，所述非晶化物层111的成分及厚度与前述实施例中相同，不再赘述。 
最后，执行步骤S104，在所述非晶化物层111表面沉积金属层，退火后形成金属硅化物113。如图2D所示。首先，利用金属溅镀方式或化学气相沉积法，在非晶化物层111的底部和侧壁上形成均匀的金属层，该金属可以是镍，或者其他可行的金属，例如Ti、Co或Cu等。然后，对半导体结构进行退火，在其他的实施例中可以采用其他的退火工艺，如快速热退火、尖峰退火等。根据本发明的实施例，通常采用瞬间退火工艺对器件进行退火，例如在大约1000℃以上的温度进行微秒级激光退火，使沉积的金属层与非晶化物层111相接触的部分形成金属硅化物113，其中非晶化物层111的厚度大于形成金属硅化物113所消耗的非晶化硅的厚度，亦即，金属硅化物113完全在非晶化物层111中形成，且在所述金属硅化物113和所述源/漏区102之间还残留有所述非晶化物层111作为过渡层，利于减小所述接触塞与源/漏区102间的接触电阻。接着，通过选择性蚀刻方式去除未参加反应形成金属硅化物的残留的金属。
最后，如图2E所示，在步骤S106中，在接触孔110内通过沉积形成接触金属114，填充该接触孔110。所述接触金属的材料可以是W、TiAl、Al等金属或合金。在形成接触金属之前，可以通过ALD、CVD、PVD等沉积工艺先在接触孔110整个内壁和底部沉积一层衬层，该衬层的材料可以是Ti、TiN、Ta、TiN或其任意组合。该衬层的厚度可以是5nm-20nm，如10nm或15nm。
随后按照常规半导体制造工艺的步骤完成该半导体器件的制造。
在上述步骤完成后，接触金属114经过金属硅化物113层和非晶硅、非晶硅碳或非晶硅锗与源/漏区连接，降低了界面的接触电阻率；并且由于与源/漏区的接触面积不仅包括接触孔110底部还包括部分侧壁面积，因此接触面积增加，从而整体减小了接触金属与源/漏区之间的电阻，利于提高半导体器件的性能。另外，在形成非晶化物层111时采用沉积工艺有效地减少了EOR缺陷的产生。
为了更清楚地理解根据上述半导体结构的制造方法所形成的半导体结构，下面结合图2D对图2E进行说明，其中，图2D为在接触孔110中填充接触金属前的半导体结构的剖面示意图。
请参考图2E，图2E为完成图1中所示的步骤后最终形成的半导体结构的剖面示意图。所述半导体结构包括：半导体衬底101；栅极堆叠，形成于半导体衬底101上，所述栅极堆叠包括栅极介质层104和金属栅层103；侧墙106，形成于栅极堆叠的侧壁上；源/漏区102，形成于栅极堆叠的两侧；层间介质层105，覆盖所述栅极堆叠和所述源/漏区102；接触孔110，贯穿所述层间介质层105并延伸到所述源/漏区102内部；所述接触孔110中填充接触金属114，其延伸入所述源/漏区102内的部分与源/漏区102之间在部分侧壁109和底部108存在共形的金属硅化物层113。
在一个实施例中，源/漏区102可以是提升的源漏极结构，即，源/漏区102的顶部高于栅极堆叠的底部，在这种情况下，接触孔110的底部108与栅极堆叠底部齐平。
所述金属硅化物层113与所述源/漏区102之间存在共形的非晶化物层111，其中，所述金属硅化物层113通过金属与所述非晶化物层111发生反应而形成。所述非晶化物层111可以通过选择性沉积工艺或外延生长工艺而形成。并且所述非晶化物层111可以由非晶硅、非晶化硅锗或者非晶化硅碳中的一种或其组合所构成。所述接触金属114的材料可以是W、TiAl合金、Al或其组合。
为了控制接触孔110在所述源/漏区102内的深度，在形成所述源/漏区102是可以预留蚀刻阻挡层，所述蚀刻阻挡层的材料与源/漏区102中其他部分不同，当通过刻蚀形成接触孔110时，接触孔110的深度停止于所述蚀刻阻挡层处。
当源/漏区102采用提升源漏极结构时，所述蚀刻阻挡层的位置优选与栅极堆叠的底部齐平。优选地，所述蚀刻阻挡层的材料为硅；源/漏区(102)中位于所述蚀刻阻挡层上方部分的材料为SiGe。
其中，对半导体器件各实施例中各部分的结构组成、材料及形成方法等均可与前述半导体器件形成方法实施例中描述的相同，不再赘述。虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (12)

1.一种半导体结构的制造方法，该方法包括以下步骤：
在半导体衬底(101)上沉积层间介质层(105)，以覆盖源/漏区(102)以及位于所述半导体衬底(101)上的栅极堆叠，所述源/漏区(102)为提升的源/漏区；
所述源/漏区内部包括蚀刻阻挡层，所述蚀刻阻挡层的材料与源/漏区中其他部分不同，所述蚀刻阻挡层的位置与栅极堆叠的底部齐平；
刻蚀所述层间介质层(105)以及源/漏区(102)，以暴露所述源/漏区(102)中部分区域并形成到达源/漏区(102)内部并停止于所述蚀刻阻挡层的接触孔(110)；
在所述源/漏区(102)的暴露区域上在接触孔底部和侧壁均匀地形成共形的非晶化物层(111)；
在所述非晶化物层(111)表面形成金属硅化物层(113)；
在接触孔(110)中填充接触金属(114)。
2.根据权利要求1所述的方法，其中：
通过选择性沉积工艺或外延生长工艺形成所述共形的非晶化物层(111)。
3.根据权利要求1所述的方法，其中：
所述非晶化物层(111)的厚度大于形成所述金属硅化物所消耗的非晶化物的厚度。
4.根据权利要求1至3中的任何一项所述的方法，其中所述非晶化物为非晶硅、非晶化硅锗或者非晶化硅碳中的一种。
5.根据权利要求1至3中的任何一项所述的方法，在所述形成共形的非晶化物层(111)的步骤之后，进一步包括向所述共形的非晶化物层(111)进行掺杂离子注入。
6.根据权利要求1至3中的任何一项所述的方法，其中所述源/漏区(102)的暴露区域包括接触孔(110)的底部和由所述底部延伸的部分侧壁。
7.根据权利要求1.3中的任何一项所述的方法，其中所述接触金属(114)的材料是W、TiA1合金、A1或其组合。
8.根据权利要求1所述的方法，其中：
所述蚀刻阻挡层的材料为硅；
源/漏区中位于所述蚀刻阻挡层上方部分的材料为SiGe。
9.一种半导体结构，包括：
半导体衬底(101)；
栅极堆叠，其形成于所述半导体衬底(101)上；
源/漏区(102)，其形成于半导体衬底(101)中，所述源/漏区(102)为提升的源/漏区，所述源/漏区(102)内部包括蚀刻阻挡层，所述蚀刻阻挡层的材料与源/漏区(102)中其他部分不同，所述蚀刻阻挡层的位置与栅极堆叠的底部齐平；
层间介质层(105)，其覆盖所述栅极堆叠和所述源/漏区(102)；
接触孔(110)，其贯穿所述层间介质层(105)，延伸到所述源/漏区(102)内部并停止于所述蚀刻阻挡层，在接触孔底部和侧壁均匀地形成共形的非晶化物层(111)；
接触金属(114)，其填充所述接触孔(110)；
其特征在于，
所述接触金属(114)延伸入所述源/漏区(102)内的部分与源/漏区(102)之间在侧壁和底部存在共形的金属硅化物层(113)。
10.根据权利要求9所述的半导体结构，其中所述非晶化物层(111)由非晶硅、非晶化硅锗或者非晶化硅碳中的一种或其组合所构成。
11.根据权利要求9所述的半导体结构，其中所述接触金属(114)的材料是W、TiA1合金、A1或其组合。
12.根据权利要求9所述的半导体结构，其中：
所述蚀刻阻挡层的材料为硅；
源/漏区(102)中位于所述蚀刻阻挡层上方部分的材料为SiGe。
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