TWI718304B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI718304B
TWI718304B TW106117321A TW106117321A TWI718304B TW I718304 B TWI718304 B TW I718304B TW 106117321 A TW106117321 A TW 106117321A TW 106117321 A TW106117321 A TW 106117321A TW I718304 B TWI718304 B TW I718304B
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fet
conductive material
dielectric layer
method described
layer
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TW106117321A
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TW201901810A (zh
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陳紹平
馬煥淇
游建文
洪國欽
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聯華電子股份有限公司
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Priority to US15/636,632 priority patent/US10388788B2/en
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Abstract

一種半導體元件的製作方法，包含於半導體基底上形成P型場效電晶體(p-type field-effect transistor,p-FET)，然後形成介電層覆蓋該p-FET，接著於介電層中形成開口，暴露出p-FET的源/汲區，再形成導電材料填充該開口。導電材料包含一應力，其對於該半導體基底是一種伸張應力(tensile stress)，介於400至800兆帕(MPa)之間。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件及其製作方法，特別是關於一種包含伸張應力(tensile stress)的P型場效電晶體(p-type field-effect transistor,p-FET)的接觸插塞(contact plug)及其製作方法。
隨著半導體元件尺寸的微縮，閘極介電層厚度隨著每個新的技術世代演進而持續縮減，主要可減少短通道效應(short channel effects)的影響，並獲得較高的電流驅動能力(driving capability)。當閘極介電層厚度變薄，對於閘極介電層可靠度的需求也越來越高。近年來發現，半導體元件的使用期限(lifetime)特別與P型通道元件的負偏壓溫度不穩定性(Negative Bias Temperature Instability,NBTI)特性相關。因此，如何改善NBTI問題也就成為現今積體電路技術發展中重要的課題。
本發明目的在於提供一種半導體元件的製作方法，可改善P型場效電晶體(p-FET)的NBTI特性。
本發明一方面提供一種半導體元件的製作方法。首先，於一半導體基底上形成一P型場效電晶體(p-type field-effect transistor,p-FET)，然後於該半導 體基底上形成一介電層，覆蓋該p-FET，接著於該介電層中形成一開口並且暴露出該p-FET的一源/汲區，後續形成一導電材料填充該開口，其中該導電材料包含一應力。較佳者，該應力對於該半導體基底是一種伸張應力(tensile stress)，介於400至800兆帕(MPa)之間。
本發明另一方面提供一種半導體元件，包含一半導體基底，一P型場效電晶體(p-type field-effect transistor,p-FET)設於該半導體基底上，一介電層位於該半導體基底上並且覆蓋該p-FET，一接觸插塞形成於該介電層中並且與該PFET的一源/汲區接觸，其中該接觸插塞是由包含一應力的一導電材料填充。較佳者，該應力對於該半導體基底是一種伸張應力(tensile stress)，介於400至800兆帕(MPa)之間。
10:基底
10a:主動區
12:絕緣結構
14:源/汲區
16:第一層間介電層
16a:接觸蝕刻停止層
18:第二層間介電層
42:開口
44:開口
46,52a:襯層
48,54:金屬矽化物
52:導電材料
42a,42b,42c:源/汲接觸插塞
44a,44b,44c:閘極接觸插塞
18a:緩衝層
20:閘極結構
30:虛設閘極結構
22,32:閘極介電層
24,34:閘極電極
26,36:蓋層
28,38:側壁子
P1:快速熱退火製程
P2:快速熱退火製程
100:半導體元件
200:半導體元件
101:關係曲線
201:關係曲線
第1圖至第4圖為本發明一較佳實施例製作一半導體元件的步驟示意圖。
第5圖至第6圖為本發明一較佳實施例的半導體元件的實驗量測結果。
第7圖至第8圖為第1圖至第4圖所述較佳實施例之一變化型。
第9圖至第10圖為第1圖至第4圖所述較佳實施例之另一變化型。
請參考第1圖至第4圖。第1圖至第4圖為本發明一較佳實施例之製作一半導體元件的步驟示意圖。如第1圖所示，首先提供一基底10，可以是矽基底、磊晶矽基底、矽鍺基底、碳化矽基底或矽覆絕緣基底(silicon-on-insulator，SOI) 等半導體基底，但不限於此。基底10包含絕緣結構12以及藉由絕緣結構12定義的至少一主動區10a。至少一閘極結構20設在主動區10a上並且沿著第1圖深度方向橫跨過主動區10a。源/汲區14設在基底10中鄰近閘極結構20兩側的位置。基底10、閘極結構20及其兩側的源/汲區14共同構成一電晶體，可以是平面式(planar)場效電晶體或者是鰭式場效電晶體(finFET)。所述較佳實施例是形成p型鰭式場效電晶體(p-FET)，形成閘極結構20之前須先將絕緣結構12凹陷至低於主動區10a上表面的高度，使得閘極結構20橫跨過主動區10a時會覆蓋住主動區10a的上表面和部分側壁(圖未示)。如第1圖所示，閘極結構20包含閘極電極24，設於基底10上、側壁子28，設於閘極電極24兩相對側壁上，以及閘極介電層22，至少介於閘極電極24以及基底10之間。閘極電極24可以是習知的多晶矽閘極，或者是在形成第一層間介電層16(例如以HDP製程製作氧化矽)後以金屬閘極置換(replacement metal gate)製程形成的金屬閘極。若以金屬閘極置換製程形成閘極電極24，較佳是結合後高介電常數介電層(high-k last)製程，形成如第1圖所示具有U型剖面形狀的閘極介電層22，其夾設在閘極電極24、側壁子28和基底10之間。閘極電極24包含至少一層的p型功函數金屬層，例如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不限於此。功函數金屬層可沿著閘極介電層22上設置，同樣具有U型剖面形狀。閘極電極24還可包含一填充金屬(例如鎢)，填滿U型功函數金屬層的中央凹陷區域。閘極結構20還包含一蓋層26，設在閘極電極24的正上方。閘極介電層22可以是由氧化矽、氮化矽或其他高介電常數材料構成。側壁子28可以是由氧化矽或氮化矽構成的單層或多層結構。在其他實施例中，側壁子28也可以是由更多層的介電材料構成。源/汲區14可以是利用離子植入製程將p型摻雜(dopant)植入至基底10而形成的摻雜區，或者是利用磊晶成長製程形成的磊晶層(epitaxial layer)，例如是矽鍺(SiGe)層。若是要用磊晶成長製程製作源/汲區14，在形成閘極結構20時較佳同時在主動區10a兩端各形成一虛設閘 極結構(dummy gate structure)30，完全覆蓋住主動區10a的端點。藉由虛設閘極結構30，可實現自對準磊晶成長製作源/汲區14，還可減少源/汲區14中的缺陷。
請繼續參考第1圖。接著形成一第二層間介電層18(例如以TEOS-CVD製作的氧化矽)，完全覆蓋閘極結構20和第一層間介電層16。可根據需求選擇性的在第一層間介電層16和第二層間介電層18之間設置一緩衝層18a，例如氧化矽或氮化矽。第一層間介電層16和基底10之間較佳設有一接觸蝕刻停止層(CESL)16a，以作為形成開口42的蝕刻停止層。
請參考第2圖。接著，以至少一次的圖案化製程定義出開口42，其貫穿第一層間介電層16和第二層間介電層18(及緩衝層18a)，暴露出電晶體的源/汲區14。較佳者，開口42是對準在閘極結構20和虛設閘極結構30之間，在緊密佈局的情況下，開口42可與閘極結構20和虛設閘極結構30比鄰而設，暴露出覆蓋在側壁子28和側壁子38上的接觸蝕刻停止層16a，甚至暴露出側壁子28和側壁子38，但不暴露出閘極電極24的任何部分。第2圖中至少一次的圖案化製程也包含定義開口44，其對準在閘極電極24正上方並貫穿第二層間介電層18(及緩衝層18a)和蓋層26，暴露出閘極電極24。應可理解的是，在其他實施例中，電晶體閘極接觸插塞的開口44和源/汲接觸插塞的開口42是在不同製程階段定義並且以不同導電材料填充，也就是說第2圖中僅形成開口42，未形成開口44。
請參考第3圖。接著全面性的形成一襯層46，共型的沿著開口42和開口44覆蓋，並且與暴露出來的源/汲區14和閘極電極24直接接觸。接著，進行一快速熱退火製程(RTP)P1，使襯層46中的金屬材質與源/汲區14反應，形成一金屬矽化物48。本實施例的襯層46是由一鈦(Ti)層以及其上方的一氮化鈦(TiN)層共同 構成，快速熱退火製程P1會使鈦層與直接接觸的源/汲區14中的矽反應，形成矽化鈦(TiSi)。在其他實施例中，襯層46也可僅包含一鈦層。
請參考第4圖。接著，於基底10上沉積一導電材料52，填滿開口42和開口44，然後移除開口42和開口44外多餘的導電材料52，分別得到源/汲接觸插塞(S/D contact plug)42a和閘極接觸插塞(gate contact plug)44a。導電材料52可選自由鈷(Co)、銅(Cu)、鋁(Al)、鎢(W)、鎳(Ni)、鉑(Pt)、鉭(Ta)、鈦(Ti)等半導體製程常用的金屬及其組合(combination)所構成的群組，但不限於此。較佳者，導電材料52是利用原子層沉積(ALD)製程形成的鈷金屬。與習知以鎢金屬填充形成的源/汲接觸插塞和閘極接觸插塞相比，本發明以鈷金屬填充接觸插塞開口的方法不僅具有較好的填充能力，在小尺寸的情況下(例如開口寬度小於15奈米)還具有明顯較低的阻值。另外，材質為鈷金屬的導電材料52對於基底10具有一應力，具體來說是一種伸張(tensile)應力。根據實驗量測鈷金屬薄膜和鎢金屬薄膜對半導體基底的應力，分別是介於400至800兆帕(MPa)之間和約1600兆帕。也就是說，以鈷金屬填充形成的接觸插塞相較於以鎢金屬填充形成的接觸插塞，對於半導體基底10具有較小的伸張應力。
第5圖和第6圖是本發明之較佳實施例形成的半導體元件的負偏壓溫度不穩定性(NBTI)實驗量測結果。第5圖和第6圖中的半導體元件100和半導體元件200是製作在晶圓上，特別用來進行NBTI量測的一種測試鍵(testkey)結構，較佳是根據該製程世代最小設計規範(minimum rule)製作的p型場效電晶體(p-FET)，以模擬出最嚴苛情況下的NBTI結果並得到較準確的預測使用期限(lifetime)。第5圖和第6圖中的半導體元件100和半導體元件200差異在於，半導體元件100的接觸插塞(contact plug)是前文所述之較佳實施例用鈷金屬填充形成。 半導體元件200的接觸插塞是習知的鎢金屬填充形成。其他如尺寸和結構，兩者相同。
請參考第5圖。第5圖是以習知的NBTI量測方法得到的閘極電壓(Vg)與使用期限(life time)的關係圖。習知NBTI量測方法例如先提供一待測半導體元件，在施加應力(stress)前先量測該半導體元件的I-V特性，以作為比較用的對照組，然後開始施加應力，例如在一強制溫度(stress temperature)的環境下同時對該半導體元件施加一強制閘極電壓(stress gate voltage,Vg)，並且在施加應力的過程中週期性的量測該半導體元件的臨界電壓(threshold voltage,Vth)，並與對照組比較，得到臨界電壓偏移量(△Vth)。第5圖是在強制溫度攝氏125度下各自對半導體元件100和半導體元件200施加三種強制電壓(1.7V、1.8V和1.9V)，然後量測臨界電壓偏移量，再將上述實驗數據帶入一臨界電壓偏移量與時間之關係模型，利用曲線擬合(curve fitting)的方法描繪出預測的閘極電壓(Vg)與使用期限(life time)的關係曲線101和201。根據關係曲線101和201，在相同強制電壓(即相同閘極電壓)下，半導體元件100(以鈷金屬填充形成接觸插塞)的使用期限明顯大於半導體元件200(以鎢金屬填充形成接觸插塞)的使用期限。也就是說，半導體元件100具有較好的NBTI可靠度表現。換個角度來看，在一可靠度規範的條件下，例如第5圖5年規範線代表在臨界電壓偏移量不大於56mV的限制條件下，在攝氏125度環境可達到5年的使用期限，半導體元件100可承受的閘極電壓相較於半導體元件200高出18mV，代表半導體元件100具有較大的閘極電壓偏移容忍度，較不易由於操作電壓的偏移而導致NBTI惡化。
請參考第6圖。第6圖左邊提供了半導體元件100(以鈷金屬填充形成接觸插塞)和半導體元件200(以鎢金屬填充形成接觸插塞)於NBTI量測時，掃描 閘極電壓(Vg)與測得的閘極電流(Ig)的關係圖，右邊特別放大顯示掃描閘極電壓介於1.8V至2.5V之間的曲線。NBTI現象背後的物理機制至今仍存在爭議，最被普遍接受的說法是反應-擴散模型(reaction-diffusion model)，即當p-FET在高溫下受到負閘極電壓時，存在基底的電洞(hole)容易受到熱激發而注入到矽-閘極介電層(例如二氧化矽)介面，打斷介面的矽-氫鍵，產生氫原子或氫氣往閘極介電層擴散，並且留下矽懸鍵(dangling bond)因此造成臨界電壓偏移。值得注意的是，本發明發現額外的伸張應力(tensile stress)使得p-FET的矽-閘極介電層的能階差降低，增加電洞注入至矽-閘極介電層介面的機會，因而使NBTI惡化。在NBTI測試下，被熱激發的電洞和擴散的氫原子可能在負閘極電壓的吸引下進一步穿隧過閘極介電層，因此會反應出較大的閘極電流(Ig)。第6圖的結果顯示，在閘極電壓(Vg)的掃描區間內，半導體元件100的閘極電流明顯小於半導體元件200的閘極電流。如前所述，半導體元件100是以鈷金屬填充形成接觸插塞，比起半導體元件200以鎢金屬填充形成接觸插塞，半導體元件100具有相對較低的伸張應力，因而具有相對較大的矽-閘極介電層能階差，減少電洞注入到矽-閘極介電層介面的機會。因此半導體元件100(以鈷金屬填充形成接觸插塞)比起半導體元件200(以鎢金屬填充形成接觸插塞)，具有較少的矽懸鍵、較穩定的臨界電壓因而較好的NBTI可靠度表現。
請參考第7圖和第8圖，為第1圖至第4圖所述較佳實施例的一變化型，其中第3圖的快速熱退火製程P1形成金屬矽化物48後，移除剩餘的襯層46，如第7圖所示。後續形成導電材料52填充開口42和開口44並移除多餘的導電材料後，得到如第8圖所示的源/汲接觸插塞42b和閘極接觸插塞44b。本變化型中，導電材料52與金屬矽化物48、側壁子28和側壁子38(或第一介電層16和第二介電層18)直接接觸。藉由移除剩餘的襯層46，可使得導電材料52更容易填滿開口42和 開口44。在某些情況下，為了增加導電材料52的附著性，如第7圖所示移除襯層46後，可另形成一黏著層(圖未示)覆蓋開口42和44，再沉積導電材料52。
請參考第9圖和第10圖，為前文所述較佳實施例的另一變化型，其中定義出開口42和開口44後，形成是鈷金屬的襯層52a，因此後續快速熱退火製程P2後形成的金屬矽化物54為矽化鈷(CoSi)。後續，形成包含鈷金屬的導電材料52填充開口42和44並除多餘的導電材料52後，得到如第10圖所示的源/汲接觸插塞42c和閘極接觸插塞44c。較佳者，導電材料52為原子層沉積製程形成的鈷金屬層，可以先直接以該原子層沉積製程進行幾個循環沿著開口沉積一預定厚度的鈷金屬層作為襯層52a，然後進行快速熱退火製程P2使該襯層52a與源/汲區14反應形成金屬矽化物54，再繼續進行更多個鈷金屬的原子層沉積循環形成導電材料52直到填滿開口，達到簡化製程的目的。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100:半導體元件
200:半導體元件
101:關係曲線
201:關係曲線

Claims (14)

  1. 一種半導體元件的製作方法，包含：於一半導體基底上形成一P型場效電晶體(p-type field-effect transistor,p-FET)；於該半導體基底上形成一介電層，覆蓋該p-FET；於該介電層中形成至少一開口，暴露出該p-FET的一源/汲區；形成一襯層共型地覆蓋開口；以及形成一導電材料於該襯層上並完全填充該開口，其中該導電材料包含鈷並且對於該p-FET包含一應力，以獲得該p-FET的一改善的負偏壓溫度不穩定性(NBTI)。
  2. 如申請專利範圍第1項所述之方法，其中該導電材料是由原子層沉積法(ALD)形成。
  3. 如申請專利範圍第1項所述之方法，其中另包含進行一快速熱退火製程(rapid thermal process,RTP)以於該源/汲區形成一金屬矽化物。
  4. 如申請專利範圍第1項所述之方法，其中該襯層是在進行該快速熱退火製程之前形成。
  5. 如申請專利範圍第1項所述之方法，其中該襯層包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(Ta)或其組合。
  6. 如申請專利範圍第5項所述之方法，其中該金屬矽化物包含矽化鈦。
  7. 如申請專利範圍第5項所述之方法，其中該金屬矽化物包含矽化鈷。
  8. 如申請專利範圍第1項所述之方法，其中該應力是一種伸張應力(tensile stress)，介於400至800兆帕(MPa)之間。
  9. 一種半導體元件，包含：一半導體基底；一P型場效電晶體(p-type field-effect transistor,p-FET)設於該半導體基底上；一介電層位於該半導體基底上並且覆蓋該p-FET；以及一接觸插塞形成於該介電層中並且與該PFET的一源/汲區接觸，其中該接觸插塞是由一導電材料填滿並且包括一襯層介於該導電材料與該介電層和該p-FET的該源/汲區之間，其中該導電材料包含鈷並且對於該p-FET包含一應力，以獲得該p-FET的一改善的負偏壓溫度不穩定性(NBTI)。
  10. 如申請專利範圍第9項所述之方法，其中另包含一金屬矽化物，位於該接觸插塞與該源/汲區之間。
  11. 如申請專利範圍第9項所述之方法，其中該襯層包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(Ta)或其組合。
  12. 如申請專利範圍第10項所述之方法，其中該金屬矽化物包含矽化鈦(TiSi)。
  13. 如申請專利範圍第10項所述之方法，其中該金屬矽化物包含矽化鈷(CoSi)。
  14. 如申請專利範圍第14項所述之方法，其中該應力是一種伸張應力(tensile stress)，介於400至800兆帕(MPa)之間。
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US10950728B2 (en) * 2017-11-16 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same
US10644156B2 (en) * 2018-03-12 2020-05-05 Globalfoundries Inc. Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices
US11062946B2 (en) * 2018-11-08 2021-07-13 International Business Machines Corporation Self-aligned contact on a semiconductor device
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001555A1 (en) * 2010-09-29 2013-01-03 Haizhou Yin Semiconductor structure and method for manufacturing the same
US20160071800A1 (en) * 2014-09-05 2016-03-10 United Microelectronics Corp. Semiconductor structure and process thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100458086B1 (ko) * 2002-09-24 2004-11-26 주식회사 하이닉스반도체 반도체소자의 콘택 형성 방법 및 그를 이용한 피모스소자의 제조 방법
US7968952B2 (en) * 2006-12-29 2011-06-28 Intel Corporation Stressed barrier plug slot contact structure for transistor performance enhancement
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KR101669470B1 (ko) * 2009-10-14 2016-10-26 삼성전자주식회사 금속 실리사이드층을 포함하는 반도체 소자
US9006072B2 (en) * 2013-03-14 2015-04-14 United Microelectronics Corp. Method of forming metal silicide layer
US9029920B2 (en) 2013-06-04 2015-05-12 Globalfoundries Inc. Semiconductor devices and methods of fabrication with reduced gate and contact resistances
KR102467848B1 (ko) * 2015-10-12 2022-11-16 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001555A1 (en) * 2010-09-29 2013-01-03 Haizhou Yin Semiconductor structure and method for manufacturing the same
US20160071800A1 (en) * 2014-09-05 2016-03-10 United Microelectronics Corp. Semiconductor structure and process thereof

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