CN103137488A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN103137488A
CN103137488A CN2011103940142A CN201110394014A CN103137488A CN 103137488 A CN103137488 A CN 103137488A CN 2011103940142 A CN2011103940142 A CN 2011103940142A CN 201110394014 A CN201110394014 A CN 201110394014A CN 103137488 A CN103137488 A CN 103137488A
Authority
CN
China
Prior art keywords
layer
semiconductor device
dielectric layer
interlayer dielectric
channel region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103940142A
Other languages
English (en)
Other versions
CN103137488B (zh
Inventor
王桂磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201110394014.2A priority Critical patent/CN103137488B/zh
Priority to US14/361,692 priority patent/US20150035055A1/en
Priority to PCT/CN2012/079691 priority patent/WO2013078882A1/zh
Publication of CN103137488A publication Critical patent/CN103137488A/zh
Application granted granted Critical
Publication of CN103137488B publication Critical patent/CN103137488B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供一种半导体器件及其制造方法，该制造方法包括以下步骤：提供衬底(100)，在所述衬底(100)之上形成伪栅堆叠和侧墙(230)，在伪栅堆叠的两侧形成源/漏区(110)，并形成覆盖整个半导体器件的停止层(240)以及第一层间介质层(300)；去除所述停止层(240)的一部分以暴露所述伪栅堆叠，继续去除所述伪栅堆叠，暴露沟道区；刻蚀所述沟道区，形成凹槽结构；在凹槽结构中形成新沟道区，与所述衬底(100)的上表面齐平，所述新沟道区从与衬底的交界面开始依次包括缓冲层、Ge层(120)和Si帽层；形成栅极堆叠。相应地，本发明还提供一种半导体器件。本发明通过使用Ge来代替Si形成新的沟道区，有效提高了载流子迁移率，提高了半导体器件的性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
随着半导体行业的发展，具有更高性能和更强功能的集成电路要求更大的元件密度，而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小(目前已经达到纳米级)，因此半导体器件制造过程中对工艺控制的要求较高。
限制金属氧化物半导体(MOS)晶体管尺寸进一步缩小的主要问题是短沟道效应(SCE)，且该现象主要发生在沟道长度小于0.1微米时。器件失效包括但不仅限于DIBL(漏极感应载流子势垒降低，即低的源漏极击穿电压)，亚阈值泄露，和阈值不稳定等。这些问题统称为短沟道效应，主要与界面层的等效氧化层厚度(Equivalent Oxide Thickness，EOT)有关。
因此，随着器件尺寸的进一步缩小，增加载流子迁移率就成了至关重要的一环。现有技术中，通常采用材料硅作为各种半导体器件的衬底，其中沟道区即为硅材料。如果能够将沟道区的材料换成具有更高载流子迁移率的材料，且这种材料又能和硅衬底很好地结合，那么半导体器件的性能将会有大幅度提高。
发明内容
本发明提供一种目的在于提供一种半导体器件及其制造方法，用于改善沟道区载流子迁移率，提高器件的性能。
根据本发明的一个方面，提供一种半导体器件的制造方法，其特征在于，包括以下步骤：
a)提供衬底(100)，在所述衬底(100)之上形成伪栅堆叠和侧墙(230)，在伪栅堆叠的两侧形成源/漏区(110)，并形成覆盖整个半导体器件的停止层(240)以及第一层间介质层(300)；
b)去除所述停止层(240)的一部分以暴露所述伪栅堆叠，继续去除所述伪栅堆叠，暴露沟道区；
c)刻蚀所述沟道区，形成凹槽结构；
d)在凹槽结构中形成新沟道区，与所述衬底(100)的上表面齐平，所述新沟道区从与衬底的交界面开始依次包括缓冲层、Ge层(120)和Si帽层；
e)形成栅极堆叠。
根据本发明的另一个方面，提供一种半导体器件，包括：
衬底(100)，形成有沟道区凹槽，该凹槽中填充了缓冲层、Ge层(120)和Si帽层；
栅极堆叠，形成于Si帽层之上；
侧墙(230)，形成于栅极堆叠两侧；
在所述沟道区凹槽的两侧形成于所述衬底(100)之中的源/漏区(110)。
本发明提供的半导体器件的制造方法及其结构，通过在沟道区外延生长Ge代替传统的Si，提高了载流子的迁移率。如下表所示：
Figure BDA0000115139890000021
在几种常用的材料中，Ge具有最高的空穴迁移率和较高的电子迁移率，因此采用Ge材料两者的迁移率都会有所提高；载流子迁移率越高，LSIC(Large-Scaled Integrate circuits，大规模集成电路)的工作速度越快。进一步地，由于Ge和Si具有相似的晶格常数，因此Ge可以很容易地集成在Si衬底上。对于NMOS器件，在Ge上原位掺杂硼或者铟；而对于PMOS器件，原位掺杂砷或者磷，能够进一步调节沟道区的应力，且采用原位掺杂的方法能够有效减小采用离子注入方法产生的损伤。另外，对Ge掺杂会形成非常陡峭的掺杂轮廓，从而改进短沟道效应。
因此，沟道区采用Ge代替Si能够有效提高沟道区载流子迁移率，提高器件的整体性能，且该方法在工艺上易于实现。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为根据本发明的一种半导体器件的制造方法的一个具体实施方式的流程示意图；
图2～图13为根据本发明的上述实施方式的半导体器件的制造方法的各个步骤的剖面示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。应当注意，在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
由于本发明提供的半导体器件有多种结构，下面对本发明的一种优选结构进行概述。
该半导体器件包括：衬底100，形成有沟道区凹槽，该凹槽中填充了缓冲层、Ge层120和Si帽层；栅极堆叠，形成于Si帽层之上；侧墙230，形成于栅极堆叠两侧；在所述沟道区凹槽的两侧形成于所述衬底100之中的源/漏区110；覆盖所述源/漏区110和所述侧墙230的停止层240；覆盖所述停止层240的第一层间介质层300。其中，停止层240的厚度为10nm～20nm，例如10nm、15nm或20nm。缓冲层为SixGe1-x，0＜x＜1。根据不同的器件类型，Ge层120可以采用不同的掺杂，例如：对于NMOS器件，原位掺杂硼或者铟；而对于PMOS器件，原位掺杂砷或者磷。
所述栅极堆叠包括：介质层410、高k介质层420以及金属栅极430。其中，高k介质层420的厚度为1nm～3nm，例如1nm、2nm或3nm。
可选的，还可以包括第二层间介质层500和接触塞620。第二层间介质层500覆盖所述第一层间介质层300和栅极堆叠；接触塞620贯穿第二层间介质层500、所述第一层间介质层300和所述停止层240，与源/漏区110相连接。第二层间介质层500的厚度为10nm～50nm，例如10nm、20nm或50nm。
优选的，在接触塞620和源/漏区110之间还包括金属硅化物600。金属硅化物600的厚度为1nm～7nm，例如1nm、4nm或7nm。
下文中将结合本发明提供的半导体器件的制造方法对上述实施例进行进一步的阐述。
参考图1，图1是根据本发明的半导体器件的制造方法的一个具体实施方式的流程图，该方法包括：
步骤S101，提供衬底100，在所述衬底100之上形成伪栅堆叠和侧墙230，在伪栅堆叠的两侧形成源/漏区110，并形成覆盖整个半导体器件的停止层240以及第一层间介质层300；
步骤S102，去除所述停止层240的一部分以暴露所述伪栅堆叠，继续去除所述伪栅堆叠，暴露沟道区；
步骤S103，刻蚀所述沟道区，形成凹槽结构；
步骤S104，在凹槽结构中形成新沟道区，与所述衬底100的上表面齐平，所述新沟道区从与衬底的交界面开始依次包括缓冲层、Ge层120和Si帽层；
步骤S105，形成栅极堆叠。
下面结合图2至图13对步骤S101至步骤S105进行阐释。图2至图13是根据本发明的多个具体实施方式按照图1示出的流程制造半导体器件过程中该半导体器件各个制造阶段的示意图。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
如图2所示，执行步骤S101，提供衬底100，在所述衬底100之上形成伪栅堆叠和侧墙230，在伪栅堆叠的两侧形成源/漏区110，并形成覆盖整个半导体器件的停止层240以及第一层间介质层300。
在本实施例中，衬底100包括硅衬底(例如硅晶片)。根据现有技术公知的设计要求(例如P型衬底或者N型衬底)，衬底100可以包括各种掺杂配置，也可以是未掺杂的本征半导体。其他实施例中衬底100还可以包括其他基本半导体，例如锗。或者，衬底100可以包括化合物半导体，例如碳化硅、砷化镓、砷化铟或者磷化铟。典型地，衬底100可以具有但不限于约几百微米的厚度，例如可以在400μm～800μm的厚度范围内。
在衬底100上形成包括伪栅极220和栅极介质层210的伪栅堆叠。栅极介质层210的材料包括但不限于热氧化层，包括氧化硅或氮氧化硅。伪栅极220可以聚合物材料形成。所述聚合物材料包括聚甲基丙烯酸、聚碳酸酯、SU-8、聚二甲基硅氧烷、聚酰亚胺、聚对二甲苯中的一种或其任意组合。其形成方法可以采用沉积、CVD等。例如，如果采用SU-8来制造伪栅极220，即采用沉积的方式；由于聚酰亚胺是光刻胶，如果用其来制造伪栅极220，则可采用旋涂、曝光显影的方式。优选的，采用非晶硅材料形成伪栅极220。
在本实施例中，在形成侧墙230之前，对伪栅堆叠两侧的衬底100进行浅掺杂，以形成源/漏延伸区。可选的，还可以进行Halo注入，以形成Halo注入区。其中浅掺杂的杂质类型与器件类型一致，Halo注入的杂质类型与器件类型相反。
进一步地，在所述伪栅堆叠的侧壁上形成侧墙230，用于将栅极隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙230可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm～100nm，如30nm、50nm或80nm。
之后，可以通过向衬底100中注入P型或N型掺杂物或杂质而形成源/漏区110。例如，对于PMOS来说，源/漏区110可以是P型掺杂的SiGe，对于NMOS来说，源/漏区110可以是N型掺杂的Si。源/漏区110可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成。在本实施例中，源/漏区110在衬底100内部，在其他一些实施例中，源/漏区110可以是通过选择性外延生长所形成的提升的源漏极结构，其外延部分的顶部高于伪栅堆叠底部(本说明书中所指的伪栅堆叠底部意指伪栅堆叠与半导体衬底100的交界线)。
参考图3，形成停止层240，覆盖源/漏区110、源/漏延伸区、伪栅堆叠和侧墙230。停止层240可以包括Si3N4、氮氧化硅、碳化硅和/或其他合适的材料制成。停止层240可以采用例如CVD、物理气相沉积(PVD)、ALD和/或其他合适的工艺制成。在一个实施例中，停止层240的厚度范围为10nm～20nm，例如10nm、15nm或20nm。该停止层240除了作为后续CMP步骤的停止层，还作为一种应力层。优选的，在NMOS器件中，采用具有拉应力的材料制作停止层240；在PMOS器件中，采用具有压应力的材料制作停止层240。
形成覆盖停止层240的第一层间介质层300。第一层间介质层300可以通过CVD、高密度等离子体CVD、旋涂或其他合适的方法形成在停止层240上。第一层间介质层300的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。第一层间介质层300的厚度范围可以是40nm～150nm，如40nm、100nm或150nm。如图4所示，执行平坦化处理，使伪栅堆叠上的停止层240暴露出来，并与第一层间介质层300齐平(本发明中的术语“齐平”指的是两者之间的高度差在工艺误差允许的范围内)。
执行步骤S102，参考图5和图6，去除所述停止层240的一部分以暴露所述伪栅堆叠，继续去除所述伪栅堆叠，暴露沟道区。去除伪栅极220，停止于栅极介质层210，形成一个凹槽。由于TMAH溶液在非晶硅材料和氧化硅材料之间具有较高的选择性，因此优选采用TMAH溶液进行湿法刻蚀去除伪栅极220，参考图6。
接下来，参考图7，去除栅极介质层210，停止于衬底100，暴露沟道区。可采用干刻或者湿刻工艺。湿刻工艺包括采用HF基湿法刻蚀液，例如稀释HF酸(DHF)或缓释刻蚀液(BOE，HF与NH4F的混合物)或其他合适的刻蚀剂溶液。所述干刻方法包括等离子体刻蚀、离子铣、反溅射、反应离子刻蚀。
进一步地，执行步骤S103，沿步骤S102中形成的凹槽继续向下刻蚀，刻蚀衬底100中的沟道区，形成沟道区凹槽，如图8所示。刻蚀方法例如采用TMAH湿法刻蚀或等离子体干法刻蚀，刻蚀衬底达到一定深度。可从本说明书的上述部分找到说明，在此不再赘述。沟道区凹槽的深度依照器件电性性能需要而定，例如当器件沟道区厚度需要50nm时，沟道区凹槽的深度大于等于50nm。
参考图9，执行步骤S104，在沟道区凹槽中形成新的沟道区。首先在衬底100上的凹槽内沉积SixGe1-x材料，形成缓冲层。其中，x的取值范围可为0～1，可以根据工艺需要灵活条件。沉积可以采用超高压化学气相沉积(UHV/CVD)、分子束外延(MBE)、减压化学气相沉积(RPCVD)或者金属有机气相沉积(MOCVD)等方法进行。接下来，在缓冲层上外延生长材料Ge，形成Ge层120。根据器件类型的不同，在生长过程中，进行不同离子的原位掺杂。对于NMOS器件，掺杂硼或者铟；而对于PMOS器件，掺杂砷或者磷。最后在Ge层120上形成Si帽层，所述Si帽层的上表面与源/漏区110的上表面齐平。由于Ge的电子迁移率和空穴迁移率都明显高于Si，且Ge的晶格常数与Si相似，能够很容易在硅衬底100上进行沉积。因此采用Ge离子新生成的沟道区可进一步调节沟道区内的应力，以提高沟道区内载流子的迁移率。
最后，执行步骤S105，形成栅极堆叠。可选的，在沟道区上方形成衬垫介质层410。衬垫介质层410的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。优选采用氧化物，其厚度小于1nm。
在介质层410和凹槽侧壁上形成高k介质层420。高k介质层420的材料包括HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合。优选为HfO2或La2O3。高k介质层420的厚度为1nm～3nm，例如1nm、2nm或3nm。
进一步，形成金属栅极430。可选的，金属栅极430可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-80nm，如10nm、30nm或80nm。
可选的，金属栅极430还可以包括以功函数金属层，功函数金属栅层可以采用TiN、TiAlN、TaN或TaAlN等材料制成。功函数金属层位于金属栅极430的底部与高k介质层420向接触。
参考图10，对高k介质层420和金属栅极430进行平坦化处理，使两者刚好填充侧墙230构成的凹槽，两者的上表面与侧墙上表面齐平。
可选的，在步骤S105中形成的半导体器件上形成接触塞。首先形成第二层间介质层500，以覆盖上述步骤中形成的半导体器件。第二层间介质层500可以通过化学气相沉积(Chemical vapor deposition，CVD)、高密度等离子体CVD、旋涂或其他合适的方法形成。第二层间介质层500的材料可以采用包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。第二层间介质层500的厚度范围可以是10nm～50nm，如10nm、30nm或50nm。
接下来，参考图11，刻蚀部分第二层间介质层500、第一层间介质层300和停止层240，形成使源/漏区110部分暴露的接触孔孔。具体地，可以使用干法刻蚀、湿法刻蚀或其他合适的刻蚀方式进行刻蚀以形成接触孔。由于栅极堆叠被侧墙230所保护，因此即使在形成接触孔时进行过刻蚀也不会导致金属栅极430与源/漏区110的短路。
如果源/漏区110是通过选择性外延生长所形成的提升的源/漏结构，其外延部分的顶部高于栅极堆叠底部，则接触孔可以形成到源/漏区110内部与栅极堆叠底部齐平的位置为止，这样当在接触孔内填充接触金属以形成接触塞620时，该接触金属可以通过接触孔的部分侧壁和底部与源/漏区110接触，从而进一步增加接触面积并降低接触电阻。
可选的，在接触孔下部暴露的源/漏区110上沉积金属，进行退火处理后形成金属硅化物600。具体地，首先，通过接触孔采用离子注入、沉积非晶化物或者选择性生长的方式，对暴露的源/漏区110进行预非晶化处理，形成局部非晶硅区域；然后利用金属溅镀方式或化学气相沉积法，在该源/漏区110上形成均匀的金属层，优选地，该金属可以是镍。当然该金属也可以是其他可行的金属，例如Ti、Co或Cu等。随后对该半导体器件进行退火，在其他的实施例中可以采用其他的退火工艺，如快速热退火、尖峰退火等。根据本发明的实施例，通常采用瞬间退火工艺对器件进行退火，例如在大约1000℃以上的温度进行微秒级激光退火，使所述沉积的金属与该源/漏区110内形成的非晶化物发生反应形成金属硅化物600，最后可以选用化学刻蚀的方法除去未反应的沉积的所述金属。所述非晶化物可以是非晶硅、非晶化硅锗或者非晶化硅碳中的一种。在本实施例中，金属硅化物600的厚度为1nm～7nm，例如1nm、2nm或7nm。形成金属硅化物600的好处是可以减小接触塞620中的接触金属与源/漏区110之间的电阻率，进一步降低接触电阻。
如图13所示，在接触孔内通过沉积的方法填充接触金属形成接触塞620。该接触金属具有与衬底100中暴露的源/漏区110进行电连接的下部分(所述“电连接”指的是接触金属的下部分可能直接与衬底100中暴露的源/漏区110接触，也可能通过衬底100中暴露的源/漏区100上形成的金属硅化物600与衬底100中暴露的源/漏区110形成实质上的电连通)，该接触金属经过接触孔贯穿停止层240、第一层间介质层300和第二介质层500，并露出其顶部。
优选地，接触金属的材料为W。当然根据半导体的制造需要，接触金属的材料包括但不限于W、Al、TiAl合金中任一种或其组合。可选地，在填充接触金属之前，可以选择在接触孔的内壁以及底部形成衬层610。该衬层610可以通过ALD、CVD、PVD等沉积工艺沉积在接触孔的内壁以及底部，该衬层610的材料可以是Ti、TiN、Ta、TaN、Ru或其组合。
采用本发明提供的半导体器件的制造方法，通过采用Ge材料代替Si材料形成新的沟道区，有效提高了沟道区的载流子迁移率，进而提高了半导体器件的性能。且采用原位掺杂的方法能够有效减小采用离子注入方法产生的损伤。另外，对Ge掺杂会形成非常陡峭的掺杂轮廓，从而改进短沟道效应。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (20)

1.一种半导体器件的制造方法，其特征在于，包括以下步骤：
a)提供衬底(100)，在所述衬底(100)之上形成伪栅堆叠和侧墙(230)，在伪栅堆叠的两侧形成源/漏区(110)，并形成覆盖整个半导体器件的停止层(240)以及第一层间介质层(300)；
b)去除所述停止层(240)的一部分以暴露所述伪栅堆叠，继续去除所述伪栅堆叠，暴露沟道区；
c)刻蚀所述沟道区，形成凹槽结构；
d)在凹槽结构中形成新沟道区，与所述衬底(100)的上表面齐平，所述新沟道区从与衬底的交界面开始依次包括缓冲层、Ge层(120)和Si帽层；
e)形成栅极堆叠。
2.根据权利要求1所述的方法，其特征在于，所述步骤a)之后包括：
对所述第一层间介质层(300)进行平坦化处理。
3.根据权利要求1所述的方法，其特征在于，所述步骤e)包括：
在所述新沟道区上形成介质层(410)；
在所述介质层(410)上以及所述侧墙(230)的内壁上形成高k介质层(420)；
形成金属栅极(430)。
4.根据权利要求3所述的方法，其特征在于，所述高k介质层(420)的厚度为1nm～3nm。
5.根据权利要求1所述的方法，其特征在于，在所述步骤e)之后还包括步骤：
f)形成接触塞(620)。
6.根据权利要求5所述的方法，其特征在于，所述步骤f)进一步包括：
形成覆盖整个半导体器件的第二层间介质层(500)；
刻蚀去除所述第二层间介质层(500)、所述第一层间介质层(300)和所述停止层(240)的一部分形成使所述源/漏区(110)部分暴露的接触孔；
在所述接触孔中填充金属材料，以形成接触塞(620)。
7.根据权利要求6所述的方法，其特征在于，所述第二层间介质层(500)的厚度为10nm～50nm。
8.根据权利要求6所述的方法，其特征在于，在所述接触孔中填充金属材料之前，先形成金属硅化物(600)。
9.根据权利要求1所述的方法，其特征在于，还包括在形成所述新沟道区时，对Ge层进行原位掺杂。
10.根据权利要求1所述的方法，其特征在于，所述缓冲层为SixGe1-x，0＜x＜1。
11.根据权利要求1所述的方法，其特征在于，所述停止层(240)的厚度为10nm～20nm。
12.一种半导体器件，包括：
衬底(100)，形成有沟道区凹槽，该凹槽中填充了缓冲层、Ge层(120)和Si帽层；
栅极堆叠，形成于Si帽层之上；
侧墙(230)，形成于栅极堆叠两侧；
在所述沟道区凹槽的两侧形成于所述衬底(100)之中的源/漏区(110)。
13.根据权利要求12所述的半导体器件，其特征在于，还包括覆盖所述源/漏区(110)和所述侧墙(230)的停止层(240)；覆盖所述停止层(240)的第一层间介质层(300)。
14.根据权利要求12所述的半导体器件，其特征在于，所述缓冲层为SixGe1-x，0＜x＜1。
15.根据权利要求12所述的半导体器件，其特征在于，所述栅极堆叠包括：介质层(410)、高k介质层(420)和金属栅极(430)。
16.根据权利要求15所述的半导体器件，其特征在于，所述高k介质层(420)的厚度为1nm～3nm。
17.根据权利要求12所述的半导体器件，还包括：第二层间介质层(500)和接触塞(620)，其中：
所述第二层间介质层(500)覆盖所述第一层间介质层(300)和所述栅极堆叠；
接触塞(620)贯穿所述第二层间介质层(500)、所述第一层间介质层(300)和所述停止层(240)，与源/漏区(110)相连接。
18.根据权利要求17所述的半导体器件，其特征在于，所述第二层间介质层(500)的厚度为10nm～50nm。
19.根据权利要求17所述的半导体器件，其特征在于，在所述接触塞(620)与源/漏区(110)之间还包括金属硅化物(600)。
20.根据权利要求20所述的半导体器件，其特征在于，所述Ge层(120)经过原位掺杂。
CN201110394014.2A 2011-12-01 2011-12-01 半导体器件及其制造方法 Active CN103137488B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201110394014.2A CN103137488B (zh) 2011-12-01 2011-12-01 半导体器件及其制造方法
US14/361,692 US20150035055A1 (en) 2011-12-01 2012-08-03 Semiconductor device and manufacturing method therefor
PCT/CN2012/079691 WO2013078882A1 (zh) 2011-12-01 2012-08-03 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110394014.2A CN103137488B (zh) 2011-12-01 2011-12-01 半导体器件及其制造方法

Publications (2)

Publication Number Publication Date
CN103137488A true CN103137488A (zh) 2013-06-05
CN103137488B CN103137488B (zh) 2015-09-30

Family

ID=48497137

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110394014.2A Active CN103137488B (zh) 2011-12-01 2011-12-01 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US20150035055A1 (zh)
CN (1) CN103137488B (zh)
WO (1) WO2013078882A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752202A (zh) * 2013-12-26 2015-07-01 中国科学院微电子研究所 一种半导体器件的制造方法
CN105097538A (zh) * 2014-05-13 2015-11-25 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN106910671A (zh) * 2015-12-23 2017-06-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN107112354A (zh) * 2014-11-25 2017-08-29 阿托梅拉公司 包括超晶格和替换金属栅极结构的半导体装置和相关方法
CN109841563A (zh) * 2017-11-28 2019-06-04 台湾积体电路制造股份有限公司 选择性覆盖工艺和由此形成的结构

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795441A (zh) * 2014-01-20 2015-07-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US9466670B2 (en) 2014-03-12 2016-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Sandwich epi channel for device enhancement
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US20150372099A1 (en) * 2014-06-19 2015-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide formation using a spike annealing process
US9577067B2 (en) * 2014-08-20 2017-02-21 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate and manufuacturing process thereof
TWI610435B (zh) * 2014-11-17 2018-01-01 聯華電子股份有限公司 具有橫向擴散金屬氧化物半導體結構之高壓鰭式場效電晶體元件及其製造方法
US10516816B2 (en) * 2014-11-19 2019-12-24 Lenovo (Singapore) Pte. Ltd. Enhanced information handling device cover
US9799654B2 (en) * 2015-06-18 2017-10-24 International Business Machines Corporation FET trench dipole formation
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108574013B (zh) * 2017-03-13 2021-07-30 中芯国际集成电路制造(上海)有限公司 半导体装置及其操作方法
CN108962817B (zh) * 2017-05-22 2020-11-27 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
TWI673870B (zh) * 2018-10-09 2019-10-01 立錡科技股份有限公司 高壓元件及其製造方法
CN111435684B (zh) * 2019-01-14 2023-05-23 联华电子股份有限公司 具有应变通道的晶体管及其制作方法
CN111755403B (zh) * 2020-07-16 2022-09-20 福建省晋华集成电路有限公司 接触插塞结构、其制作方法及半导体器件的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060166417A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation Transistor having high mobility channel and methods
CN101006569A (zh) * 2004-08-25 2007-07-25 英特尔公司 形成突变的源漏金属栅晶体管
CN101847582A (zh) * 2010-04-16 2010-09-29 清华大学 半导体结构的形成方法
CN102117750A (zh) * 2009-12-30 2011-07-06 中国科学院微电子研究所 Mosfet结构及其制作方法
CN102194747A (zh) * 2010-03-03 2011-09-21 中国科学院微电子研究所 形成沟道材料的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338942A (en) * 1992-01-16 1994-08-16 Hitachi, Ltd. Semiconductor projections having layers with different lattice constants
KR100385857B1 (ko) * 2000-12-27 2003-06-02 한국전자통신연구원 SiGe MODFET 소자 제조방법
JP4002219B2 (ja) * 2003-07-16 2007-10-31 株式会社ルネサステクノロジ 半導体装置及び半導体装置の製造方法
US7569443B2 (en) * 2005-06-21 2009-08-04 Intel Corporation Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US7888195B2 (en) * 2008-08-26 2011-02-15 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US8084824B2 (en) * 2008-09-11 2011-12-27 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US8685847B2 (en) * 2010-10-27 2014-04-01 International Business Machines Corporation Semiconductor device having localized extremely thin silicon on insulator channel region
US8084311B1 (en) * 2010-11-17 2011-12-27 International Business Machines Corporation Method of forming replacement metal gate with borderless contact and structure thereof
CN103107091B (zh) * 2011-11-15 2016-06-22 中国科学院微电子研究所 一种半导体结构及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101006569A (zh) * 2004-08-25 2007-07-25 英特尔公司 形成突变的源漏金属栅晶体管
US20060166417A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation Transistor having high mobility channel and methods
CN102117750A (zh) * 2009-12-30 2011-07-06 中国科学院微电子研究所 Mosfet结构及其制作方法
CN102194747A (zh) * 2010-03-03 2011-09-21 中国科学院微电子研究所 形成沟道材料的方法
CN101847582A (zh) * 2010-04-16 2010-09-29 清华大学 半导体结构的形成方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752202A (zh) * 2013-12-26 2015-07-01 中国科学院微电子研究所 一种半导体器件的制造方法
CN104752202B (zh) * 2013-12-26 2018-01-02 中国科学院微电子研究所 一种半导体器件的制造方法
CN105097538A (zh) * 2014-05-13 2015-11-25 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN105097538B (zh) * 2014-05-13 2018-07-10 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
CN107112354A (zh) * 2014-11-25 2017-08-29 阿托梅拉公司 包括超晶格和替换金属栅极结构的半导体装置和相关方法
CN106910671A (zh) * 2015-12-23 2017-06-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN109841563A (zh) * 2017-11-28 2019-06-04 台湾积体电路制造股份有限公司 选择性覆盖工艺和由此形成的结构
CN109841563B (zh) * 2017-11-28 2022-04-01 台湾积体电路制造股份有限公司 选择性覆盖工艺和由此形成的结构
US11380542B2 (en) 2017-11-28 2022-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Selective capping processes and structures formed thereby
US11830742B2 (en) 2017-11-28 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Selective capping processes and structures formed thereby

Also Published As

Publication number Publication date
CN103137488B (zh) 2015-09-30
WO2013078882A1 (zh) 2013-06-06
US20150035055A1 (en) 2015-02-05

Similar Documents

Publication Publication Date Title
CN103137488B (zh) 半导体器件及其制造方法
CN109727916B (zh) 半导体装置的制造方法
JP6329294B2 (ja) ホウ素ドープゲルマニウムの濃度が高いトランジスタ
US8497177B1 (en) Method of making a FinFET device
US10431584B2 (en) Semiconductor device including fin structures and manufacturing method thereof
US8999794B2 (en) Self-aligned source and drain structures and method of manufacturing same
US11038055B2 (en) Method and structure of improving contact resistance for passive and long channel devices
US7652336B2 (en) Semiconductor devices and methods of manufacture thereof
KR20190024625A (ko) 반도체 디바이스 및 방법
US10411114B2 (en) Air gap spacer with wrap-around etch stop layer under gate spacer
US9406791B2 (en) Transistors, semiconductor devices, and methods of manufacture thereof
KR102249703B1 (ko) 핀 버클링이 감소된 FinFET 구조물 및 방법
CN109427901B (zh) 半导体器件和方法
US20150380297A1 (en) Method for manufacturing mosfet
WO2012119336A1 (zh) 一种半导体结构及其制造方法
CN113130655B (zh) 半导体器件及其制造方法
CN104465377A (zh) Pmos晶体管及其形成方法
WO2015054915A1 (zh) 一种非对称超薄soimos晶体管结构及其制造方法
US9443977B1 (en) FinFET with reduced source and drain resistance
CN102856206A (zh) 一种半导体结构及其制造方法
CN102800578A (zh) 一种半导体结构的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant