CN102194747A - 形成沟道材料的方法 - Google Patents

形成沟道材料的方法 Download PDF

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CN102194747A
CN102194747A CN2010101181947A CN201010118194A CN102194747A CN 102194747 A CN102194747 A CN 102194747A CN 2010101181947 A CN2010101181947 A CN 2010101181947A CN 201010118194 A CN201010118194 A CN 201010118194A CN 102194747 A CN102194747 A CN 102194747A
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channel material
threshold voltage
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raceway groove
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骆志炯
朱慧珑
尹海洲
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Institute of Microelectronics of CAS
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Priority to PCT/CN2010/077272 priority patent/WO2011106973A1/zh
Priority to US12/999,380 priority patent/US20120126310A1/en
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Abstract

本发明提出一种形成沟道材料的方法，包括以下步骤：形成衬底；在所述衬底之上形成具有伪栅堆叠的MOS器件；去除所述伪栅堆叠；在所述伪栅堆叠的下部沟道处形成沟道沟槽；用沟道材料填充所述沟道沟槽；形成栅堆叠。本发明实施例通过替换栅工艺在高温退火等高温工艺结束之后形成沟道材料，从而能够有效地避免由于高温工艺对形成的沟道材料构成的不良影响。

Description

形成沟道材料的方法
技术领域
本发明涉及半导体设计及制造技术领域，特别涉及一种形成沟道材料的方法。
背景技术
目前，随着CMOS器件特征尺寸的不断缩小，沟道材料的选择对于CMOS器件来说变得越来越重要。现有技术存在的缺点是，目前大部分的沟道材料均不适合高温工艺，如后续的退火等高温工艺将会严重影响沟道材料的性能，因此需要改进。
发明内容
本发明的目的旨在至少解决上述技术缺陷之一，特别是解决由于后续退火等高温工艺对沟道材料的影响问题。
为达到上述目的，本发明一方面提出一种形成沟道材料的方法，包括以下步骤：形成衬底；在所述衬底之上形成具有伪栅堆叠的MOS器件；去除所述伪栅堆叠；在所述伪栅堆叠的下部沟道处形成沟道沟槽；用沟道材料填充所述沟道沟槽；形成栅堆叠。
在本发明的一个实施例中，所述沟道材料包括Ge、InGaAs、GaAs、GaN或其组合。
在本发明的一个实施例中，填充有所述沟道材料的所述沟道沟槽的厚度约为
Figure GSA00000038289600011
，优选为
Figure GSA00000038289600012
。
在本发明的一个实施例中，在形成所述栅堆叠的时候，还包括：淀积并形成阈值电压调节层。其中，所述阈值电压调节层包括：Ta、Al、Ti、TiN、TiAl、TiAlN、TaN或其组合。在本发明的一个实施例中，所述阈值电压调节层的厚度约为3-7nm。
在本发明的一个实施例中，形成栅堆叠包括：在所述填充有所述沟道材料的所述沟道沟槽之上形成一层或多层栅介质层；淀积并形成阈值电压调节层；淀积并形成金属栅极。在本发明的一个实施例中，淀积并形成阈值电压调节层之后，还包括：进行低温退火。
本发明另一方面还提出了一种半导体结构，包括：衬底；形成在所述衬底之上的具有栅堆叠的MOS器件；和形成在所述栅堆叠之下的沟道沟槽，所述沟道沟槽中填充的沟道材料是通过替换栅工艺形成的。
在本发明的一个实施例中，所述沟道材料包括Ge、InGaAs、GaAs、GaN或其组合。
在本发明的一个实施例中，所述沟道沟槽的厚度约为
Figure GSA00000038289600021
，优选为
Figure GSA00000038289600022
。
在本发明的一个实施例中，所述栅堆叠中还包括至少一层阈值电压调节层。
在本发明的一个实施例中，所述阈值电压调节层包括：Ta、Al、Ti、TiN、TiAl、TiAlN、TaN或其组合。
在本发明的一个实施例中，所述阈值电压调节层的厚度约为3-7nm。
本发明实施例通过替换栅工艺在高温退火等高温工艺结束之后形成沟道材料，从而能够有效地避免由于高温工艺对形成的沟道材料构成的不良影响。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
如图1-8所示，为本发明实施例的形成沟道材料方法的中间步骤的结构剖面图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
如图1所示，为本发明实施例的半导体结构示意图，该半导体结构包括衬底100，以及形成在衬底100之上的具有栅堆叠的MOS器件，在图中以CMOS器件为例，以及形成在栅堆叠之下的沟道沟槽700，其中，沟道沟槽700中填充的沟道材料是通过替换栅工艺形成的。这样本发明可通过替换栅工艺在高温退火等高温工艺结束之后形成沟道材料，从而能够有效地避免由于高温工艺对形成的沟道材料构成的不良影响。
为了更好的理解本发明，本发明还提出了一种形成上述半导体结构的方法，如图1-8所示，为本发明实施例的形成沟道材料方法的中间步骤的结构剖面图。该形成沟道材料的方法包括以下步骤：
步骤1，形成衬底100。在本发明实施例中，衬底100可包括任何半导体衬底材料，具体可以是但不限于硅、锗、锗化硅、SOI(绝缘体上硅)、碳化硅、砷化镓或者任何III/V族化合物半导体等。
步骤2，在衬底100之上采用传统的CMOS工艺流程形成CMOS晶体管，但是需要说明的是，在该实施例中以CMOS结构举例进行描述，但是其他任何MOSFET管也可适用于本发明中。如图2所示，形成的CMOS结构包括衬底100，形成在衬底100之中的源极/漏极200，形成在衬底100之上的伪栅堆叠300和伪栅堆叠300两侧的侧墙600，以及氮化物覆盖层400和HDP(氧化物)500。其中，在本发明的一个实施例中，氮化物覆盖层400的厚度约为20nm。在另一个实施例中，HDP500的厚度约为300nm。在本发明的实施例中，伪栅堆叠300可包括一层或多层栅介质层301，还可包括多晶硅栅302或其他层，本发明实施例对伪栅堆叠300并无具体的限制。
步骤3，进行CMP(化学机械抛光)以打开多晶硅栅302，如图3所示。
步骤4，去除(如刻蚀)多晶硅栅302以及多晶硅栅302之下的一层或多层栅介质层301，并停止在衬底100之上，如图4所示。
步骤5，在下部沟道处形成沟道沟槽700，如图5所示。在本发明的一个实施例中，优选地，沟道沟槽700的厚度约为
Figure GSA00000038289600041
，优选为
Figure GSA00000038289600042
。
步骤6，在沟道沟槽700中填充沟道材料，如图6所示。在本发明的一个实施例中，可采用生长(Epi)的方式填充沟道材料，当然本领域技术人员还可选择其他方式进行填充。在本发明的另一个实施例中，沟道材料包括Ge、InGaAs、GaAs、GaN或其组合等。
步骤7，再次形成栅堆叠。具体地，先淀积形成一层或多层栅介质层301，之后淀积阈值电压调节层303，如图7所示，在本发明的一个实施例中，阈值电压调节层303可包括Ta、Al、Ti、TiN、TiAl、TiAlN、TaN或其组合等。在其他实施例中，阈值电压调节层303的厚度约为3-7nm。
步骤8，淀积金属栅层900，如图8所示。
步骤9，进行CMP去除金属栅层900并停止在氮化物覆盖层400之上，从而形成金属栅极1000，如图1所示。在本发明的一个实施例中步骤9进行CMP之前，还可为阈值电压调节层303进行一次低温退火，由于此次退火为低温退火，因此对通过本发明实施例形成的沟道材料不会产生不良的影响。
本发明实施例通过替换栅工艺在高温退火等高温工艺结束之后形成沟道材料，从而能够有效地避免由于高温工艺对形成的沟道材料构成的不良影响。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同限定。

Claims (14)

1.一种形成沟道材料的方法，其特征在于，包括以下步骤：
形成衬底；
在所述衬底之上形成具有伪栅堆叠的MOS器件；
去除所述伪栅堆叠；
在所述伪栅堆叠的下部沟道处形成沟道沟槽；
用沟道材料填充所述沟道沟槽；
形成栅堆叠。
2.如权利要求1所述的形成沟道材料的方法，其特征在于，所述沟道材料包括Ge、InGaAs、GaAs、GaN或其组合。
3.如权利要求2所述的形成沟道材料的方法，其特征在于，填充有所述沟道材料的所述沟道沟槽的厚度约为优选为
Figure FSA00000038289500012
4.如权利要求1所述的形成沟道材料的方法，其特征在于，在形成所述栅堆叠的时候，还包括：淀积并形成阈值电压调节层。
5.如权利要求4所述的形成沟道材料的方法，其特征在于，所述阈值电压调节层包括：Ta、Al、Ti、TiN、TiAl、TiAlN、TaN或其组合。
6.如权利要求4所述的形成沟道材料的方法，其特征在于，所述阈值电压调节层的厚度约为3-7nm。
7.如权利要求4所述的形成沟道材料的方法，其特征在于，形成栅堆叠包括：
在所述填充有所述沟道材料的所述沟道沟槽之上形成一层或多层栅介质层；
淀积并形成阈值电压调节层；
淀积并形成金属栅极。
8.如权利要求4所述的形成沟道材料的方法，其特征在于，淀积并形成阈值电压调节层之后，还包括：
进行低温退火。
9.一种半导体结构，其特征在于，包括：
衬底；
形成在所述衬底之上的具有栅堆叠的MOS器件；和
形成在所述栅堆叠之下的沟道沟槽，所述沟道沟槽中填充的沟道材料是通过替换栅工艺形成的。
10.如权利要求9所述的半导体结构，其特征在于，所述沟道材料包括Ge、InGaAs、GaAs、GaN或其组合。
11.如权利要求10所述的半导体结构，其特征在于，所述沟道沟槽的厚度约为
Figure FSA00000038289500021
优选为
Figure FSA00000038289500022
12.如权利要求9所述的半导体结构，其特征在于，所述栅堆叠中还包括至少一层阈值电压调节层。
13.如权利要求12所述的半导体结构，其特征在于，所述阈值电压调节层包括：Ta、Al、Ti、TiN、TiAl、TiAlN、TaN或其组合。
14.如权利要求12所述的半导体结构，其特征在于，所述阈值电压调节层的厚度约为3-7nm。
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