CN104701310B - 具有轮廓化功函金属栅电极的半导体器件及其制造方法 - Google Patents

具有轮廓化功函金属栅电极的半导体器件及其制造方法 Download PDF

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CN104701310B
CN104701310B CN201410734195.2A CN201410734195A CN104701310B CN 104701310 B CN104701310 B CN 104701310B CN 201410734195 A CN201410734195 A CN 201410734195A CN 104701310 B CN104701310 B CN 104701310B
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function metal
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CN104701310A (zh
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李达元
刘冠廷
钟鸿钦
李显铭
张文
章勋明
罗唯仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了具有轮廓化功函金属栅电极的半导体器件。半导体结构包括在绝缘层的开口中形成的金属栅极结构。该金属栅极结构包括栅极介电层、阻挡层、位于栅极介电层和阻挡层之间的功函金属层、以及位于阻挡层上方的功函调整层,其中,功函金属具有有序的晶粒取向。本发明还提供了制造具有轮廓化功函金属栅电极的半导体器件的方法。

Description

具有轮廓化功函金属栅电极的半导体器件及其制造方法
技术领域
本发明涉及集成电路器件,更具体地,涉及具有轮廓化功函金属栅电极的半导体器件及其制造方法。
背景技术
互补金属氧化物半导体(CMOS)技术是用于制造集成电路(IC)的半导体技术。CMOS晶体管通常利用多晶硅作为NMOS和PMOS晶体管的栅电极,其中,多晶硅掺杂有N型掺杂剂以形成NMOS晶体管以及掺杂有P型掺杂剂以形成PMOS晶体管。
发明内容
为了解决现有技术中存在的问题,本发明提供了一种半导体器件,包括:金属栅极结构,形成在绝缘层的开口中,所述金属栅极结构包括:栅极介电层;阻挡层;功函金属层,位于所述栅极介电层和所述阻挡层之间,其中,功函金属具有有序的晶粒取向;以及功函调整层,位于所述阻挡层上方。
在上述半导体器件中,其中,所述半导体器件包括:覆盖层,位于所述栅极介电层和所述功函金属层之间。
在上述半导体器件中,其中,所述功函金属层具有凹形功函轮廓或凸形功函轮廓。
在上述半导体器件中,其中,所述功函金属包括结晶化金属。
在上述半导体器件中,其中,所述功函金属包括TiAl或TiAl3中的至少一种。
在上述半导体器件中,其中,所述功函金属层具有约10埃至约100埃的厚度。
在上述半导体器件中,其中,所述功函调整层包括铝。
在上述半导体器件中,其中,所述栅极介电层包括高k材料。
根据本发明的另一方面,提供了一种半导体器件,包括:金属栅极结构,形成在绝缘层中的开口中,所述金属栅极结构包括:高k栅极介电层;阻挡层;功函金属层,位于所述高k栅极介电层和所述阻挡层之间,其中,功函金属具有有序的晶粒取向;覆盖层,位于所述高k栅极介电层和所述功函金属层之间;以及功函调整层,位于所述阻挡层上方。
在上述半导体器件中,其中,所述功函金属是结晶化的。
在上述半导体器件中,其中,所述功函金属是TiAl或TiAl3
在上述半导体器件中,其中,所述功函金属层具有10埃至100埃的厚度。
在上述半导体器件中,其中,所述功函调整层是铝。
根据本发明的又一方面,提供了一种制造半导体器件的方法,包括:在绝缘层的第一开口中形成高k栅极介电层;在大于约200℃的温度下在所述高k栅极介电层上方形成中间功函金属层;在所述中间功函金属层上方形成阻挡层;在所述阻挡层上方形成功函调整层;以及实施后热退火以将所述中间功函金属层转变成功函金属层。
在上述方法中,其中,在200℃至500℃之间的温度下沉积所述中间功函金属层。
在上述方法中,其中,在300℃至600℃之间的温度下实施所述后热退火。
在上述方法中,其中,所述中间功函金属层是TiAl,所述功函金属是TiAl3,并且所述功函调整层是Al。
在上述方法中,其中,通过PVD、CVD或ALD工艺形成所述功函金属层。
在上述方法中,其中,所述方法包括:在去除第一伪栅极和第一伪电介质之前,形成源极、漏极和ILD层。
在上述方法中,其中,所述方法包括:在所述高k介电层和所述中间功函金属层之间形成覆盖层。
附图说明
图1是根据一些实施例的示出用于制造具有轮廓化(profiled)功函金属栅电极的半导体器件的方法的流程图;
图2至图5是根据一些实施例的处于各个制造阶段的半导体器件的截面图;
图6是根据一些实施例的中间功函金属的晶体结构的图示;
图7、图8a、图8b和图9是根据一些实施例的处于各个制造阶段的半导体器件的截面图;
图10是根据一些实施例的形成功函金属层的图示;
图11是根据一些实施例的功函金属的晶体结构的图示;
图12是根据一些实施例的相互扩散能量势垒的图解说明;以及
图13是根据一些实施例的功函金属栅电极中的轮廓的图解说明。
具体实施方式
现在结合附图描述所要求保护的主题,其中,贯穿全文,相同的参考标号通常用于代表相同的元件。在以下描述中,为了解释的目的,阐述了许多具体细节以提供对所要求保护的主题的理解。然而,显而易见地,在没有这些具体细节的情况下可以实践所要求保护的主题。在其他情况下,以框图形式示出了结构和器件以便利描述所要求保护的主题。
根据一些实施例,本文中提供了具有金属栅电极(与掺杂的多晶硅栅电极相反)的半导体器件。示出了关于制造NMOS晶体管的一些实施例。然而,在一些实施例中,制造PMOS和NMOS晶体管,PMOS和NMOS晶体管彼此邻近、彼此间隔开或分别地制造。
参照图1,示出了根据一些实施例的用于制造具有轮廓化功函金属栅电极的半导体器件的方法100的流程图。也参照图2至图5和图7至图9,示出了根据一些实施例(诸如根据图1的方法100)的处于各个制造阶段的半导体器件200的截面图。在一些实施例中,利用CMOS工艺流程制造半导体器件200的部分。在一些实施例中,在图1的方法100之前、期间和之后提供额外的工艺。图2示出了实施例,其中,示出了对层间电介质(ILD)进行化学机械抛光(CMP)之后的暴露伪多晶硅栅极的半导体器件200。
在步骤102中,提供半导体衬底202。在一些实施例中,衬底包括晶圆、由晶圆形成的管芯等。在一些实施例中,半导体衬底202是硅衬底。在一些实施例中,衬底202是硅锗、砷化镓中的至少一种或其他合适的半导体材料。在一些实施例中,衬底202包括一种或多种掺杂区,诸如P阱或N阱中的至少一种。在一些实施例中,衬底202包括诸如掩埋层或外延层的其他部件。在一些实施例中,衬底202是诸如绝缘体上硅(SOI)的绝缘体上半导体。在一些实施例中,半导体衬底202包括掺杂的外延层。在一些实施例中,半导体衬底202包括位于另一不同类型的半导体层上面的半导体层。在一些实施例中,半导体衬底202是位于硅锗层上的硅层。
在一些实施例中,半导体器件200包括形成在衬底202中的诸如浅沟槽隔离(STI)部件的隔离结构210以用于隔离衬底的有源区204。在一些实施例中,隔离结构210包括硅的局部氧化(LOCOS)配置。在一些实施例中,隔离结构210由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料中的至少一种形成。在一些实施例中,有源区配置为NMOS器件(诸如nFET 212)或PMOS器件(未示出)中的至少一种。在一些实施例中,隔离结构210使NMOS器件212的有源区和邻近器件(诸如PMOS器件)的有源区隔离。
在步骤104中,在衬底202上方形成伪栅极结构220,伪栅极结构包括伪电介质216和伪多晶硅栅极218。在一些实施例中,伪栅极结构220的形成包括形成各个材料层以及蚀刻/图案化各个材料层以形成nFET 212器件的栅极结构。
在一些实施例中,在衬底202上形成伪电介质216。在一些实施例中,伪电介质216包括氧化物。在一些实施例中,伪电介质216包括从约10埃()至约50埃()的范围内的厚度。在一些实施例中,伪多晶硅栅极218是多晶硅。在一些实施例中,通过诸如沉积的合适的工艺在伪电介质216上方形成伪多晶硅栅极218。在一些实施例中,通过利用硅烷(SiH4)、二硅烷(Si2H6)或二氯硅烷(SiCl2H4)中的一种或多种的化学汽相沉积(CVD)工艺形成伪多晶硅栅极218。在一些实施例中,伪多晶硅栅极218的厚度为约200埃至约2000埃。
在一些实施例中,在形成伪栅极结构220之后,半导体器件200经受额外的CMOS加工以形成nFET 212的各种部件。在一些实施例中,半导体器件200包括掺杂的源极/漏极区225、侧壁间隔件或栅极间隔件227、硅化物部件、接触蚀刻停止层(CESL)和层间电介质(ILD)230。在一些实施例中,在去除伪栅极结构220之前形成侧壁间隔件227,从而使得伪栅极结构220用于限定侧壁间隔件227。因此,当去除伪栅极结构220时,将开口288限定在侧壁间隔件227之间和ILD 230内,其中,ILD 230用作绝缘层。在一些实施例中,ILD 230包括通过高深宽比工艺(HARP)或高密度等离子体(HDP)沉积工艺中的至少一种形成的氧化物。在一些实施例中,ILD 230的沉积填充半导体器件200和邻近的半导体器件之间的间隙。在一些实施例中,邻近的半导体器件是pFET。在一些实施例中,对ILD 230实施化学机械抛光(CMP)工艺以平坦化ILD,直到暴露伪多晶硅栅极218。
在步骤106中,如图3所示,去除伪电介质216和伪多晶硅栅极218,从而在ILD 230中形成开口288。在一些实施例中,通过干蚀刻、湿蚀刻、干蚀刻和湿蚀刻的组合、或其他合适的工艺去除伪多晶硅栅极218和伪电介质216。在一些实施例中,在单个蚀刻工艺中去除伪多晶硅栅极218和伪电介质216。在一些实施例中,第一湿蚀刻工艺用于去除伪多晶硅栅极218,而第二湿蚀刻工艺用于去除伪电介质216。在一些实施例中,第二湿蚀刻工艺是选择性的以去除伪电介质216,而停止在衬底202上,从而形成开口288。
在步骤108中,如图4所示,形成栅极介电层238和覆盖层239以至少部分地填充开口288。在一些实施例中,栅极介电层238形成在侧壁间隔件227上以及衬底202的有源区204上方。在一些实施例中,栅极介电层是高k介电层。在一些实施例中,通过ALD、CVD、金属有机CVD(MOCVD)、PVD、等离子体增强CVD(PECVD)、等离子体增强ALD(PEALD)或其他合适的技术中的至少一种形成栅极介电层238。在一些实施例中,栅极介电层238的厚度为约5埃至约20埃。在一些实施例中,栅极介电层238包括二元或三元高k膜。在一些实施例中,栅极介电层238是HfOx。在一些实施例中,栅极介电层238是LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SiTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4或氮氧化物中的至少一种。在一些实施例中,作为形成介电层238的部分,实施高k沉积后退火。
在一些实施例中,在栅极介电层238上方形成覆盖层239。在一些实施例中,覆盖层239包括氮化钛(TiN)或氮化钽(TaN)。在一些实施例中,覆盖层239的厚度为约5埃至约50埃。在一些实施例中,覆盖层239包括Si3N4。在一些实施例中,覆盖层239用作阻挡件以保护栅极介电层238。在一些实施例中,通过诸如ALD、PVD或CVD中的至少一种的沉积技术形成覆盖层239。在一些实施例中,覆盖层239是可选择的,并且因此不形成覆盖层239。
在一些实施例中,界面层(未示出)存在于侧壁间隔件227和栅极介电层238之间。在一些实施例中,界面层包括厚度在从约5埃至约20埃的范围内的氧化硅(SiO2)层。在一些实施例中,界面层包括通过原子层沉积(ALD)、CVD、PVD、热氧化和氮化、等离子体氧化或氮化中的至少一种形成的HfSiO或SiON中的至少一种。在一些实施例中,为了形成界面层,通过ALD、CVD或PVD在热氧化物上形成Hf膜,并且然后通过热O2氧化Hf膜以形成HfSiO。在一些实施例中,在反应性的O2和H2O环境中通过ALD、CVD或PVD形成Hf膜。
在步骤110中,如图5所示,在覆盖层239上形成中间功函金属层291。在一些实施例中,覆盖层239是可选择的,并且因此中间功函金属层291形成在栅极介电层238上。在一些实施例中,中间功函金属层291是N型或P型功函金属。在一些实施例中,中间功函金属层291是铝化钛(TiAl)。在一些实施例中,中间功函金属层291是TiAl3。在一些实施例中,中间功函金属层291是铝化镍(NiAl)或铝化铁(FeAl)中的至少一种。
在一些实施例中,在超过约200℃的温度下通过诸如ALD、CVD或PVD中的至少一种的沉积技术形成中间功函金属层291。在一些实施例中,在介于约250℃至约500℃之间的温度下沉积中间功函金属层291。在一些实施例中,在介于约300℃至400℃之间的温度下沉积中间功函金属层291。在一些实施例中,中间功函金属层291的金属晶粒取向在超过200℃的沉积期间恢复。在一些实施例中,中间功函金属层291在沉积之前为非结晶的,而在沉积之后为结晶的。在一些实施例中,中间功函金属层291是结晶化金属。在一些实施例中,中间功函金属层291具有晶体XRD轮廓。在一些实施例中,中间功函金属是晶体TiAl,并且通过具有介于约38.0至约40.0度2θ之间的峰值的XRD图案表征。如图6所示,在一些实施例中,中间功函金属具有(111)取向的平面。如图6所示,在一些实施例中,中间功函金属的(111)取向的平面是化学计量的并且交替出现Ti 604和Al606的密堆积行。如图6所示,在一些实施例中,中间功函金属层包含具有FCC晶体结构602的金属。
在一些实施例中,中间功函金属层291的厚度为至少10埃。在一些实施例中,中间功函金属层291的厚度介于约20埃至约100埃之间。在一些实施例中,在邻近衬底202的开口288的底部处的中间功函金属层291比沿着邻近侧壁间隔件227的开口288的侧部的中间功函金属层291更厚。在一些实施例中,沿着邻近侧壁间隔件227的开口288的侧部的中间功函金属层291的厚度为约5埃至约40埃,并且在邻近衬底202的开口288的底部处的中间功函金属层291的厚度为约20埃至约80埃。在一些实施例中,开口288的底部处的中间功函金属层291比开口288的侧部的中间功函金属层291厚至少1.5倍。
在步骤112中,如图7所示,在中间功函金属层291上方形成阻挡层293。在一些实施例中,阻挡层293是氮化钛/氮化钨(TiN/WN)。在一些实施例中,阻挡层293是氮化钨(WN)、氮化钽(TaN)或钌(Ru)中的至少一种。在一些实施例中,阻挡层293是多金属层结构。在一些实施例中,阻挡层293的厚度介于约20埃至约100埃之间。在一些实施例中,开口288的侧壁处的阻挡层293比开口288的底部处的阻挡层293更薄。在一些实施例中,通过诸如ALD、CVD或PVD中的至少一种的沉积技术形成阻挡层293。
在步骤114中,如图8a所示,形成功函调整层296以填充开口288的剩余部分。在一些实施例中,功函调整层296是金属。在一些实施例中,功函调整层296是Al。在一些实施例中,通过CVD形成第一Al层以及然后通过PVD形成第二Al层来沉积功函调整层296。在一些实施例中,功函调整层296包括Al、钨(W)、铜(Cu)或其他合适的金属材料中的至少一种。如图8b所示,在一些实施例中,对半导体器件200实施CMP以去除位于开口288外部的过量的材料。
在步骤116中,如图9所示,进行后热退火298以形成功函金属层299。在一些实施例中,在已经实施后段制程(BEOL)工艺之后进行后热退火298。虽然未示出,但是尤其地,这种BEOL工艺在半导体器件200上方形成导电接触件或介电层中的至少一种。通过后热退火298形成功函金属层299,后热退火298驱使功函调整层296穿过阻挡层293以与中间功函金属层291相互作用。在一些实施例中,在超过约200℃的温度下实施后热退火298。在一些实施例中,在从约300℃至约600℃的范围内的温度下实施后热退火298。在一些实施例中,持续实施后热退火298约1分钟。根据一些实施例,半导体器件200由此具有形成在ILD 230或绝缘层中的开口288中的金属栅极结构221,其中,金属栅极结构包括栅极介电层238、阻挡层293、功函金属层299和功函调整层296。
图10提供了后热退火298的实施例的图示,后热退火298驱使功函调整层296穿过阻挡层293以与中间功函金属层291相互作用,从而形成功函金属层299。在一些实施例中,功函调整层296是Al,并且中间功函金属层291是TiAl。在一些实施例中,Al从功函调整层296扩散穿过阻挡层293并且与中间功函金属层291相互作用,从而形成TiAl3功函金属层299。
在一些实施例中,功函金属层299包含晶体金属。在一些实施例中,功函金属层299是晶体TiAl3。在一些实施例中,功函金属层299包括晶体TiAl或晶体TiAl3中的至少一种。在一些实施例中,功函金属层299具有晶体XRD轮廓。在一些实施例中,功函金属层299包含晶体功函金属,晶体功函金属具有如图11所示的D022晶体结构610。
在一些实施例中,结晶化TiAl和TiAl3的特征是具有比非结晶的TiAl和TiAl3更低的相互扩散能量势垒。图12是曲线图1200,其示出,与为118ev的晶体TiAl的相互扩散能量势垒相比,非结晶的TiAl的Ti-Al相互扩散能量势垒为267ev。
在一些实施例中,功函金属层299的厚度大于10埃。在一些实施例中,功函金属层299的厚度介于约20埃至约100埃之间。在一些实施例中,开口的底部处的功函金属层299比开口的侧部处的功函金属层299更厚。在一些实施例中,开口的底部处的功函金属层299比开口的侧部处的功函金属层299厚至少1.5倍。
在一些实施例中,功函金属层299具有有序的晶粒取向。在一些实施例中,功函金属层299具有提供均匀的阈值电压和漏电流的有序的金属晶粒取向。如图13的曲线图1300所示,在一些实施例中,功函金属层299具有凹形的或凸形的轮廓1302。如曲线图1300所示,在一些实施例中,由于Al从功函调整层296扩散穿过阻挡层293的底部和侧壁,因此功函金属层299在中心1301以及边缘1303a和1303b处具有增大的Al浓度。在一些实施例中,增大的Al浓度部分是由于TiAl3的形成。在一些实施例中,凹形或凸形轮廓降低了半导体器件200的源极和漏极延伸件之间的电阻。
根据本发明的各方面,提供了一种半导体结构。该半导体结构包括在绝缘层的开口中形成的金属栅极结构。该金属栅极结构包括栅极介电层、阻挡层、位于栅极介电层和阻挡层之间的功函金属层、以及位于阻挡层上方的功函调整层。功函金属具有有序的晶粒取向。
根据本发明的各方面,提供了一种半导体结构。该半导体结构包括在绝缘层中的开口中形成的金属栅极结构。该金属栅极结构包括高k栅极介电层、阻挡层、位于高k栅极介电层和阻挡层之间的功函金属层、位于高k栅极介电层和功函金属层之间的覆盖层、以及位于阻挡层上方的功函调整层。功函金属具有有序的晶粒取向。
根据本发明的各方面,提供了一种制造半导体器件的方法。该方法包括在绝缘层的第一开口中形成高k栅极介电层。在大于约200℃的温度下在高k栅极介电层上方形成中间功函金属层。在中间功函金属层上方形成阻挡层。在阻挡层上方形成功函调整层,以及实施后热退火以将中间功函金属层转变成功函金属层。
尽管已经以针对结构特征或方法步骤的语言描述了主题,但是应该理解,所附权利要求的主题不必限于以上描述的特定特征或步骤。相反,以上描述的特定特征或步骤公开为实现至少一些权利要求的示例形式。
本文中提供了实施例的各个操作。描述的一些或所有操作的顺序不应解释为暗示着这些操作必须是顺序依赖的。将理解,可选顺序具有该描述的有益效果。而且,将理解,不是所有操作都必须存在于本文中提供的每个实施例中。同样,将理解,在一些实施例中,不是所有操作都是必需的。
而且,除非另有说明,“第一”、“第二”等不旨在暗示着时间方面、空间方面、顺序等。相反,这些术语仅用作用于部件、元件、物品等的标识符、名称等。例如,第一沟道和第二沟道通常对应于沟道A和沟道B或者两个不同的沟道或者两个相同的沟道或者同一个沟道。
将理解,本文中示出的层、部件、元件等示出为具有相对于彼此的特定尺寸,诸如结构尺寸和/或方位,在一些实施例中,为了简单和易于理解的目的,物质的实际尺寸与本文中示出的显著不同。此外,存在用于形成本文中提到的层、区域、部件、元件等的多种技术,例如,诸如注入技术、掺杂技术、旋涂技术、溅射技术、生长技术(诸如热生长)或沉积技术(诸如化学汽相沉积(CVD))。
此外,本文中使用的“示例性”意思是用作实例、例子、例证等,并且不必是有利的。如在该申请中使用的,“或”旨在意指包含性的“或”,而不是排他的“或”。此外,除非另有说明或从上下文中清楚地得出单数形式,否则在该申请中使用的“一”和“一个”通常解释为意指“一个或多个”。而且,A和B等的至少一个通常意指A或者B或者A和B。此外,在某种程度上,在具体描述或权利要求中使用了术语“包括”、“具有”、“有”、“带有”或其变体,这些术语类似于术语“包括”,意义是包括的。
而且,尽管已经关于一种或多种实施方式示出和描述了本发明,但是基于阅读和理解该说明书和附图,本领域技术人员将想到等同改变和更改。本发明包括所有这些更改和改变,并且仅由以下权利要求的范围限制。特别地,关于由以上描述的部件(例如,元件、资源等)实施的各种功能,除非另有说明,用于描述这些部件的术语旨在对应于实施所述部件的特定功能的任何部件(例如,功能等同),即使与公开的结构不是结构等同。此外,虽然可能仅关于若干实施方式的一个公开了本发明的特定特征,但是这些特征可以根据需要和用于任何给定或特定应用的优势而与其他实施方式的一个或多个其他特征结合。

Claims (19)

1.一种半导体器件,包括:
金属栅极结构,形成在绝缘层的开口中,所述金属栅极结构包括:
栅极介电层;
阻挡层;
功函金属层,位于所述栅极介电层和所述阻挡层之间,其中,功函金属具有有序的晶粒取向;以及
功函调整层,位于所述阻挡层上方,其中,所述功函调整层的靠近所述阻挡层的部分中的具有均匀一致的分布的金属材料扩散穿过所述阻挡层的底部和侧壁,所述功函金属层的中心以及边缘处具有增大的所述金属的浓度,使得所述功函金属层具有凹形功函轮廓或凸形功函轮廓。
2.根据权利要求1所述的半导体器件,包括:
覆盖层,位于所述栅极介电层和所述功函金属层之间。
3.根据权利要求1所述的半导体器件,其中,所述功函金属包括结晶化金属。
4.根据权利要求1所述的半导体器件,其中,所述功函金属包括TiAl或TiAl3中的至少一种。
5.根据权利要求1所述的半导体器件,其中,所述功函金属层具有10埃至100埃的厚度。
6.根据权利要求1所述的半导体器件,其中,所述功函调整层包括铝。
7.根据权利要求1所述的半导体器件,其中,所述栅极介电层包括高k材料。
8.一种半导体器件,包括:
金属栅极结构,形成在绝缘层中的开口中,所述金属栅极结构包括:
高k栅极介电层;
阻挡层;
功函金属层,位于所述高k栅极介电层和所述阻挡层之间,其中,功函金属具有有序的晶粒取向;
覆盖层,位于所述高k栅极介电层和所述功函金属层之间;以及
功函调整层,位于所述阻挡层上方,其中,所述功函调整层的靠近所述阻挡层的部分中的具有均匀一致的分布的金属材料扩散穿过所述阻挡层的底部和侧壁,所述功函金属层的中心以及边缘处具有增大的所述金属的浓度,使得所述功函金属层具有凹形功函轮廓或凸形功函轮廓。
9.根据权利要求8所述的半导体器件,其中,所述功函金属是结晶化的。
10.根据权利要求8所述的半导体器件,其中,所述功函金属是TiAl或TiAl3
11.根据权利要求8所述的半导体器件,其中,所述功函金属层具有10埃至100埃的厚度。
12.根据权利要求8所述的半导体器件,其中,所述功函调整层是铝。
13.一种制造半导体器件的方法,包括:
在绝缘层的第一开口中形成高k栅极介电层;
在大于200℃的温度下在所述高k栅极介电层上方形成中间功函金属层;
在所述中间功函金属层上方形成阻挡层;
在所述阻挡层上方形成功函调整层;以及
实施后热退火以将所述中间功函金属层转变成具有有序的晶粒取向的功函金属层,其中,所述功函调整层的靠近所述阻挡层的部分中的具有均匀一致的分布的金属材料扩散穿过所述阻挡层的底部和侧壁,所述功函金属层的中心以及边缘处具有增大的所述金属的浓度,使得所述功函金属层具有凹形功函轮廓或凸形功函轮廓。
14.根据权利要求13所述的制造半导体器件的方法,其中,在200℃至500℃之间的温度下沉积所述中间功函金属层。
15.根据权利要求13所述的制造半导体器件的方法,其中,在300℃至600℃之间的温度下实施所述后热退火。
16.根据权利要求13所述的制造半导体器件的方法,其中,所述中间功函金属层是TiAl,所述功函金属是TiAl3,并且所述功函调整层是Al。
17.根据权利要求13所述的制造半导体器件的方法,其中,通过PVD、CVD或ALD工艺形成所述功函金属层。
18.根据权利要求13所述的制造半导体器件的方法,包括:
在去除第一伪栅极和第一伪电介质之前,形成源极、漏极和ILD层。
19.根据权利要求13所述的制造半导体器件的方法,包括:
在所述高k介电层和所述中间功函金属层之间形成覆盖层。
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