CN106158860A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN106158860A
CN106158860A CN201510190639.5A CN201510190639A CN106158860A CN 106158860 A CN106158860 A CN 106158860A CN 201510190639 A CN201510190639 A CN 201510190639A CN 106158860 A CN106158860 A CN 106158860A
Authority
CN
China
Prior art keywords
hard mask
metal
groove
sac hard
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510190639.5A
Other languages
English (en)
Other versions
CN106158860B (zh
Inventor
陈皇魁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106158860A publication Critical patent/CN106158860A/zh
Application granted granted Critical
Publication of CN106158860B publication Critical patent/CN106158860B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)

Abstract

本发明提供了半导体结构，半导体结构包括具有第一和第二表面的半导体层、以及分别限定位于第一和第二表面上方的第一金属栅极和第二金属栅极的层间电介质(ILD)。第一和第二金属栅极分别包括第一SAC硬掩模和第二SAC硬掩模，其中，第一和第二SAC硬掩模分别向位于第一和第二金属栅极下方的沟道区施加相反的应力。本发明提供了制造半导体结构的方法。该方法分别包括形成金属栅极凹槽、在金属栅极凹槽中形成金属栅极和SAC硬掩模。本发明涉及半导体结构及其制造方法。

Description

半导体结构及其制造方法
技术领域
本发明涉及半导体结构及其制造方法。
背景技术
半导体集成电路(IC)产业经历了快速发展。在IC发展过程中，功能密度(即，每芯片面积上互连器件的数量)普遍增加，而几何尺寸(即，使用制造工艺可以创建的最小的组件(或线))却已下降。这种按比例缩小工艺通常通过提高生产效率和降低相关成本而提供益处。这种按比例缩小也增加了加工和制造IC的复杂性，并且为了实现这些进步，需要IC加工和制造中的类似发展。随着晶体管尺寸的减小，栅极氧化物的厚度必须减小以在具有减小的栅极长度的情况下维持性能。然而，为了降低栅极泄漏，使用高介电常数(高k)栅极绝缘层，其在保持与由在更大的技术节点中使用的典型的栅极氧化物所提供的相同有效电容的同时，允许更大的物理厚度。
此外，随着技术节点缩小，在一些IC设计中，期望以金属栅(MG)电极代替典型的多晶硅栅电极以在部件尺寸减小的情况下改进器件性能。形成MG电极的一种工艺被称为“后栅极”工艺，其与称为“先栅极”的另一种MG电极形成工艺相反。“后栅极”工艺允许后续工艺的数量降低，包括必须在栅极形成之后实施的高温处理。
因此，期望为形成在衬底上的每个NFET、PFET、N-FinFET和P-FinFET提供不同配置的金属栅极结构的方法和半导体器件。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种半导体结构，包括：半导体衬底，包括第一表面和第二表面；层间电介质(ILD)，具有位于所述半导体衬底的所述第一表面上方的第一凹槽和位于所述半导体衬底的所述第二表面上方的第二凹槽；第一间隔件和第二间隔件，所述第一间隔件衬于所述第一凹槽的侧壁上，所述第二间隔件衬于所述第二凹槽的侧壁上；第一高k介电层和第二高k介电层，所述第一高k介电层接触所述第一凹槽的底部和所述第一间隔件的侧壁，所述第二高k介电层接触所述第二凹槽的底部和所述第二间隔件的侧壁；第一金属和第二金属，所述第一金属接触所述第一高k介电层的底部和侧壁，所述第二金属接触所述第二高k介电层的底部和侧壁；其中，所述第一金属和第二金属用于彼此不同导电类型的半导体；以及第一SAC(自对准接触)硬掩模和第二SAC硬掩模，所述第一SAC硬掩模位于所述第一金属上，所述第二SAC硬掩模位于所述第二金属上，其中，所述第一SAC硬掩模和所述第二SAC硬掩模对预定的蚀刻剂具有不同的蚀刻速率。
在上述半导体结构中，所述第一SAC硬掩模位于所述第一金属和所述第一间隔件上。
在上述半导体结构中，所述第二SAC硬掩模位于所述第二金属和所述第二间隔件上。
在上述半导体结构中，所述第一SAC硬掩模或所述第二SAC硬掩模包括氮化物。
在上述半导体结构中，所述第一SAC硬掩模的纵向高度和所述第二SAC硬掩模的纵向高度基本上彼此不同。
在上述半导体结构中，所述第一金属的纵向高度和所述第二金属的纵向高度不同。
在上述半导体结构中，所述第一SAC硬掩模具有上部和下部，所述第一SAC硬掩模的所述上部和所述下部的横向长度不同。
在上述半导体结构中，所述第二SAC硬掩模具有上部和下部，所述第二SAC硬掩模的所述上部和所述下部的横向长度不同。
根据本发明的另一方面，还提供了一种半导体结构，包括：半导体衬底，包括表面；层间电介质(ILD)，具有位于所述半导体衬底的所述表面上方的凹槽；第一间隔件，衬于所述凹槽的侧壁上；源极/漏极区，位于所述半导体衬底中，邻近所述凹槽下方的沟道区；高k介电层，接触所述凹槽的底部和所述第一间隔件的侧壁；金属，接触所述高k介电层的底部和侧壁；以及SAC硬掩模，位于所述金属上，其中，所述SAC硬掩模具有上部和下部，并且所述SAC硬掩模的所述上部和所述下部的横向长度不同。
在上述半导体结构中，第二间隔件在纵向方向上夹在所述第一间隔件和所述层间电介质之间，并且在横向方向上夹在所述表面和所述层间电介质之间。
在上述半导体结构中，所述第二间隔件包括氮化物。
在上述半导体结构中，所述源极/漏极区是外延层。
在上述半导体结构中，所述SAC硬掩模包括氮化物并且所述层间电介质包括氧化物。
在上述半导体结构中，所述凹槽具有上部和下部，并且所述上部的横向长度基本上长于所述下部的横向长度。
在上述半导体结构中，所述半导体结构是FinFET结构。
根据本发明的又一方面，还提供了一种制造半导体结构的方法，包括：在层间电介质(ILD)中形成第一凹槽和第二凹槽；形成衬于所述第一凹槽的侧壁上的第一间隔件和衬于所述第二凹槽的侧壁上的第二间隔件；形成接触所述第一凹槽的底部和所述第一间隔件的侧壁的第一高k介电层；形成接触所述第一高k介电层的底部和侧壁的第一金属；形成接触所述第二凹槽的底部和所述第二间隔件的侧壁的第二高k介电层；形成接触所述第二高k介电层的底部和侧壁的第二金属；以及在所述第一金属上形成第一SAC硬掩模和在所述第二金属上形成第二SAC硬掩模；其中，所述第一SAC硬掩模和所述第二SAC硬掩模对预定的蚀刻剂具有不同的蚀刻速率。
在上述方法中，包括去除位于所述第二金属上的所述第一SAC硬掩模。
在上述方法中，还包括回蚀刻所述第一金属或所述第二金属。
在上述方法中，还包括：通过使用蚀刻剂在所述层间电介质中形成接触件以暴露源极/漏极区。
在上述方法中，还包括确定所述第一金属和所述第二金属的应力需求。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图2是根据本发明的一些实施例的具有金属栅极结构的鳍式场效应晶体管(FinFET)的透视图；
图3是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图4是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图5是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图6是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图7是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图8是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图9是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图10是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图11是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作；
图12是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图13是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图14是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图15是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图16是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图17是根据本发明的一些实施例的用于金属栅极和硬掩模的半导体结构制造方法的操作；
图18是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图19是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图20是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图21是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图22是根据本发明的一些实施例的具有金属栅极和硬掩模的半导体结构的截面图；
图23是根据本发明的一些实施例的具有金属栅极、硬掩模和接触件的半导体结构的截面图。
具体实施方式
在以下详细描述中，阐述了大量具体细节以提供本发明的更透彻的理解。然而，本领域普通技术人员应当理解，可以在不具有这些具体细节的情况下实践本发明。在其他情况下，没有详细描述公知的方法、工序、部件和电路以便不模糊本发明。应当理解，以下公开内容提供了用于实现各个实施例的不同特征的许多不同的实施例或实例。以下描述部件和布置的具体实例以简化本发明。当然，这些仅仅是实例而不在于限制。
下文中详细讨论了本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式，而不用于限制本发明的范围。
在本发明中，论述了具有不同应力的NMOS和PMOS的半导体结构及其制造方法。
图1示出了具有第一金属栅极103a和第二金属栅极103b的半导体结构10的截面图，其中第一金属栅极103a的导电类型不同于第二金属栅极103b的导电类型。例如，如果第一金属栅极103a是P型栅极，则第二金属栅极103b是N型。半导体结构10具有半导体层100，其中，层间介电层(ILD)101设置在半导体层100上方。ILD101也限定并且围绕第一金属栅极103a和第二金属栅极103b。
仍参考图1，第一金属栅极103a和第二金属栅极103b分隔开。如图1所示，在一些实施例中，STI(浅沟槽隔离)区域102在半导体层100中并且位于第一金属栅极103a和第二金属栅极103b之间。半导体层100具有接近第一金属栅极103a下方的沟道区的第一表面101a以及接近第二金属栅极103b下方的沟道区的第二表面101b。第一源极/漏极区1011a位于半导体衬底中，并且第一源极/漏极区1011a邻近第一金属栅极103a下方的沟道区。第二源极/漏极区1011b位于半导体衬底中，并且第二源极/漏极区1011b邻近第二金属栅极103b下方的沟道区。第一SAC硬掩107a位于第一金属栅极103a的顶上，并且第二SAC硬掩模107b位于第二金属栅极103b的顶上。
在图1中，第一间隔件1035a设置在ILD 101和第一金属栅极103a之间。第二间隔件1035b设置在ILD 101和第二金属栅极103b之间。第一金属栅极103a、第一间隔件1035a和ILD 101设置在半导体层100的第一表面101a上方。第二金属栅极103b、第二间隔件1035b和ILD 101设置在半导体层100的第二表面101b上方。
第一高k介电层1033a接触第一金属栅极103a的底部和第一间隔件1035a的侧壁，并且第二高k介电层1033b接触第二金属栅极103b的底部和第二间隔件1035b的侧壁。第一金属栅极103a包括接触第一高k介电层1033a的第一金属层105a。并且类似于第一金属栅极103a，第二金属栅极103b包括接触第二高k介电层1033b的第二金属层105b。然而，第一金属103a的导电类型可以不同于第二金属103b的导电类型。例如，如果第一金属层103a是P型栅极，则第二金属层103b是N型栅极。
在本发明的一些实施例中，本文中所述的半导体衬底100是其上形成有各个层和器件结构的块状半导体衬底。在一些实施例中，块状衬底包括硅或化合物半导体，诸如GaAs、InP、Si/Ge或SiC。在半导体衬底100上可以形成各个层。例如，介电层、掺杂层、多晶硅层或导电层。可以在半导体衬底101上形成各种器件。例如，晶体管、电阻器和/或电容器，其可以通过互连层互连至额外的集成电路。
仍参考图1，第一间隔件1035a围绕第一金属栅极103a的侧壁部分，并且金属栅极103a的底部设置在第一表面101a上方。在一些实施例中，金属栅极103a包括位于第一高k介电层1033a的水平部分和第一表面101a之间的任选的中间层1031a。第二间隔件1035b围绕第二金属栅极103b的侧壁部分，并且金属栅极103b的底部设置在第二表面101b上方。并且类似于金属栅极103a，金属栅极103b还包括位于第二高k介电层1033b的水平部分和第二表面101b之间的任选的中间层1031b。
第一SAC硬掩模107a和二SAC硬掩模107b可以配置为具有不同的特征性能以提高晶体管的性能。例如，当第一金属栅极103a是N型栅极时，优选具有引入到第一栅极103a下方的沟道区的拉伸应力，以提高载流子迁移率。相反，由于第二金属栅极103b是P型，优选具有引入到第二栅极103b下方的沟道区的压缩应力，以提高载流子迁移率。
在本发明中，具有通过配置用于不同金属栅极的SAC硬掩模的膜性能来分别调整引入到金属栅极103a和103b下方的沟道区的应力的各种方法。例如，在SAC硬掩模的形成过程中，第一SAC硬掩模107a和第二SAC硬掩模107b可以形成为不同的形状，或通过诸如不同的压力、等离子体密度或RF功率的不同的工艺条件来形成。实施例及其制造方法的细节将在后面给出。在一些实施例中，ILD 101包括介电材料。例如，介电材料包括氧化硅、氮化硅、氮氧化硅、自旋玻璃(SOG)、氟化石英玻璃(FSG)、碳掺杂的氧化硅(例如，SiCOH)、BLACK(加利福尼亚圣克拉拉的应用材料公司)、氟化非晶碳、聚对二甲苯、BCB(双苯并环丁烯)、(密歇根米德兰陶氏化学)、聚酰亚胺、其他合适的多孔聚合物材料、其他合适的介电材料、和/或它们的组合。在一些实施例中，ILD 101包括高密度等离子体(HDP)介电材料(例如，HDP氧化物)和/或高高宽比工艺(HARP)介电材料(例如，HARP氧化物)。应当理解，ILD 101可以包括一种或多种介电材料和/或一个或多个介电层。如图1所示，通过化学机械抛光(CMP)工艺平坦化ILD 101直到暴露出第一金属栅极103a和第二金属栅极103b的顶部。CMP工艺包括高选择性以提供第一金属栅极103a和第二金属栅极103b、第一间隔件1035a和第二间隔件1035b以及ILD 101的基本上平坦的表面。在一些实施例中，CMP工艺具有低凹陷和/或金属腐蚀效果。
例如，在一些实施例中，第一间隔件1035a和第二间隔件1035b包括氧化硅、氮化硅、氮氧化硅、其他合适的材料、和/或它们的组合。间隔件可以通过ALD、CVD、金属有机CVD(MOCVD)、PVD、等离子体增强CVD(PECVD)、等离子体增强ALD(PEALD)、热氧化、它们的组合或其他适合的技术形成。
在本发明的一些实施例中，第一高k介电层1033a和第二高k介电层1033b是由ALD、CVD、金属有机CVD(MOCVD)、PVD、等离子体增强CVD(PECVD)、等离子体增强ALD(PEALD)、热氧化、它们的组合或其他适合的技术形成的。在一些实施例中，第一高k介电层1033a和第二高k介电层1033b包括介于约至约范围内的厚度。第一高k介电层1033a和第二高k介电层1033b包括二元或三元高-k膜。在一些实施例中，第一高k介电层1033a和第二高k介电层1033b包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物或其他合适的材料。
在一些实施例中，第一金属栅极层105a和第二金属栅层105b分别包括覆盖层、功函金属层和栅极填充金属。
覆盖层包括诸如TiN、TaN的金属氮化物或诸如碳氮化钛的金属碳氮化物或具有通式(M1，M2)(C，N)的另一四元层，其中M1，M2是IVa或Va族的不同金属。在一些实施例中，覆盖层的厚度介于从约至约的范围内。覆盖层用作阻挡件以保护高k介电层1033a和1033b。通过诸如ALD、PVD、CVD、PECVD的各种沉积技术或其他适合的技术形成覆盖层。
在一些实施例中，覆盖层是包括至少两个材料层的复合膜堆叠件。例如，接近高k介电层(1033a或1033b)的一个覆盖层由金属氮化物或金属碳氮化物的第一组分制成，而接近功函金属层的另一覆盖层是由金属氮化物或金属碳氮化物的第二组分制成。例如，该功函金属层的复合膜可以是相同的材料，但原子浓度不同。例如，该功函金属层的复合膜可以是不同的材料。
在一些实施例中，接近高k介电层(1033a或1033b)的覆盖层称为阻挡层。在一些实施例中，接近高k介电层(1033a或1033b)的覆盖层的厚度介于约至约的范围内。接近功函金属层的覆盖层的厚度介于约至约的范围内。
在一些实施例中，功函金属层包括诸如TiCN的金属碳氮化物、诸如TiSiN的金属硅氮化物、或金属铝化物。在一些实施例中，功函金属层由金属碳氮化物或金属硅氮化物制成。在其他实施例中，功函金属层包括TiAlN、TiAl、或TaAl。可以通过诸如ALD、PVD、CVD、PECVD或其他适合的技术的各种沉积技术来沉积功函金属层。在一些实施例中，功函金属层的厚度介于约至约的范围内。
在一些实施例中，在金属栅极103a和103b中设置栅极填充金属。栅极填充金属包括具有介于4.2eV至4.8eV之间的独立功函数的金属。在一些实施例中，栅极填充金属包括W、Al、Co、和它们的合金。在一些实施例中，栅极填充金属的厚度介于约至之间。
例如，在一些实施例中，第一SAC硬掩模107a和第二SAC硬掩模107b可以由CVD、PECVD、HDP、IPM或其他适合的技术形成。在一些实施例中，第一SAC硬掩模107a和第二SAC硬掩模107b包括介于约至约范围内的厚度。在一些实施例中，第一SAC硬掩模107a和第二SAC硬掩模107b包括氮化物。
由于半导体器件尺寸的缩小，FinFET结构用于提高器件性能。图2是FinFET结构30的透视图。两个半导体鳍300设置在衬底31上并且通过STI302分隔开。半导体鳍300可以由硅、锗硅、锗、或其他合适的半导体材料形成。金属栅极303位于半导体鳍300的顶面300A和侧壁300B上方。晶体管的沟道(未示出)限定为沿着半导体鳍的顶面300A和侧壁300B并且在半导体鳍300的源极/漏极区之间延伸。如图2所示，ILD 301设置为覆盖并且围绕半导体鳍300。
在一些实施例中，半导体结构10是具有从约10nm至约40nm的沟道长度Lg的平面N-MOSFET或P-MOSFET。在其他实施例中，半导体结构10是具有从约5nm至约40nm的沟道长度Lg的非平面N-FinFET或P-FinFET。
图3至图21是根据本发明的一些实施例的用于金属栅极结构的半导体结构制造方法的操作。
在图3中，牺牲栅电极2013a和2013b被覆盖在ILD 101内。
在一些实施例中，第一中间层1031a和第二中间层1031b由在牺牲栅电极2013a和2013b的去除或蚀刻期间具有选择性的材料形成。中间层用作当去除牺牲栅电极2013a和2013b时的下面的半导体层100的保护层。如果中间层1031a和1031b是热生长的电介质，则它们将仅形成在半导体层100的暴露表面上。如果中间层1031a和1031b是通过沉积操作形成的，则它们将毯式沉积到半导体层100下方的绝缘衬底(未示出)上以及半导体层100上。
间隔件1035a和1035b分别形成在牺牲栅电极2013a和2013b的侧壁上。外部间隔件2037的纵向部分夹在间隔件1035a、1035b和ILD 101之间。外部间隔件2037的横向部分夹在表面101a、101b和ILD 101之间。间隔件1035a和1035b以及外部间隔件2037均可以通过毯式沉积共形介电膜以覆盖牺牲栅电极2013a和2013b来形成。在一些实施例中，外部间隔件2037包括氮化物。
形成间隔件和外部间隔件2037的材料包括但不限于氮化硅、氧化硅、氮氧化硅或它们的组合。在本发明的一些实施例中，间隔件是由热壁(hotwall)、低压化学汽相沉积(LPCVD)操作形成的氮化硅膜。可以采用各向异性蚀刻以去除毯式沉积的间隔件和外部间隔件膜的部分。
在图4中，在形成ILD 101之后，实施诸如化学机械抛光(CMP)操作的平坦化操作。执行平坦化操作以去除位于牺牲栅电极2013a和2013b的顶面上方的过量的ILD 101，直至牺牲栅电极2013a和2013b从ILD 101暴露出来。
在图5中，通过去除第一牺牲栅电极2013a和中间层1031a形成第一金属栅极凹槽203a。通过去除第二牺牲栅电极2013b和中间层1031b形成第二金属栅极凹槽203b。在一些实施例中，牺牲栅电极2013a和2013b由多晶硅形成。通过利用包括四甲基氢氧化铵和水的湿蚀刻剂去除多晶硅牺牲栅电极2013a和2013b。
在本发明的实施例中，湿蚀刻剂溶液包括约10-35％体积的四甲基氢氧化铵。在本发明的实施例中，在蚀刻期间将四甲基氢氧化铵溶液加热至在60摄氏度至95摄氏度之间的温度。在本发明的实施例中，在蚀刻工艺期间施加诸如超声波或兆声波的声波能量。声波能量向蚀刻剂提供搅动，这使得蚀刻残留物从改变的牺牲栅电极2013a、2013b移除，从而允许新的蚀刻剂进入沟槽以分别蚀刻牺牲栅电极2013a和2013b。
在本发明的一些实施例中，用于第一牺牲栅电极2013a的蚀刻剂对中间层1031a具有选择性，并且用于第二牺牲栅电极2013b的蚀刻剂对中间层1031b具有选择性(即，不蚀刻或仅轻微蚀刻中间层1031a和1031b)，从而使得中间层1031a和1031b分别用作用于牺牲栅电极2013a和2013b蚀刻的蚀刻停止层。以这种方式，第一金属栅极凹槽203a的下面的沟道区和第二金属栅极凹槽203b的下面的沟道区可以免受蚀刻剂的影响。在一些实施例中，牺牲栅电极与中间层电介质之间的蚀刻选择性为至少10:1是所期望的。
进行下一步操作，去除中间层1031a和1031b。在本发明的实施例中，中间层1031a和1031b是氧化物并且可以利用包括氢氟酸水溶液的蚀刻剂去除。在本发明的实施例中，使用具有1-2％的体积的HF的蚀刻剂溶液
参考图6，在金属栅极凹槽203a和203b的底部上形成中间层1031a’和1031b’。以共形的方式在第一金属栅极凹槽203a内部和ILD 101的顶上形成第一高k介电层1033a。类似地，以共形的方式在第二金属栅极凹槽203b内部和ILD 101的顶上形成第二高k介电层1033b。在一些实施例中，中间层1031a’和1031b’对设计者而言是可选择的，从而使得可直接形成接近半导体层100的沟道区的高k介电层1033a和1033b。
在本发明的实施例中，分别生长厚度介于约至之间的高k介电层1033a和1033b。在本发明的实施例中，高k介电层1033a和1033b是沉积的电介质，诸如但不限于金属氧化物电介质，诸如五氧化钽(Ta2O5)和氧化钛(TiO2)、氧化钽、氧化铪、氧化锆、氧化铝、氧化镧、氧化镧铝和它们的硅酸盐或其他高k电介质，诸如PZT和BST。可以通过诸如但不限于化学汽相沉积(CVD)或原子层沉积(ALD)的技术形成高k介电膜。
参考图7，第一覆盖层2034a形成在第一高k介电层1033a上，并且第二覆盖层2034b形成在第二高k介电层1033b上。在一些实施例中，覆盖层2034a和2034b包括厚度介于约至约范围内的TiN或TaN。覆盖层2034a和2034b用作阻挡件以保护高k介电层1033a和1033b。可以通过诸如ALD、PVD、CVD、PECVD或其他适合的技术的各种沉积技术形成覆盖层2034a和2034b。
在一些实施例中，覆盖层2034a和2034b包括复合膜堆叠件。例如，复合膜堆叠件可以由任意两个金属碳氮化物层TiN和TaN制成。在一些实施例中，TiN或TaN可以具有从约至约的厚度。
图8示出了在第一金属栅极凹槽203a中形成第一功函金属层2036a和在第二金属栅极凹槽203b中形成第二功函金属层2036b之后的截面图。设计者可以使用本领域中的图案化技术以分别形成功函金属2036a和2036b。
为了简化的目的，将包括第一功函金属层2036a的晶体管定义为第一晶体管，并且将包括第二功函金属层2036b的晶体管定义为第二晶体管。分别形成在金属栅极凹槽203a和203b中的功函金属层2036a和2036b使得第一和第二晶体管具有相反的导电类型。例如，如果第一晶体管作为P型晶体管，则第二晶体管作为N型晶体管。
在一些实施例中，通过原子层沉积、物理汽相沉积、化学汽相沉积、溅射、或其他合适的操作在覆盖层2034a和2034b上形成功函金属层2036a和2036b。在一些实施例中，功函金属层2036a和2036b包括合适的金属化合物，诸如金属碳氮化物、金属铝化物、金属硅氮化物、TiN、TiSiN、TiAlN、TiAl、TaAl、TaN、或Ru。在一些实施例中，功函金属层2036a和2036b包括诸如TiN/WN的多金属层结构。
在一些实施例中，通过ALD操作在功函金属层2036a或2036b内掺杂铝原子。在其他实施例中，在形成功函金属层2036a或2036b之后，执行铝离子注入操作以调整金属栅电极的阈值电压或功函数。
参考图9，栅极凹槽形成为具有诸如2038a和2038b的填充金属。在一些实施例中，填充金属过填充凹槽。在一些实施例中，将包括Al、W、WN、TaN或Ru的单一金属溅射到金属栅极凹槽203a和203b内，和随后通过CMP操作(未示出)以去除过量的栅极填充金属2038a/2038b。在一些实施例中，功函金属层2036a/2036b、覆盖层2034a/2034b、和高k介电层1033a/1033b也从ILD 101的顶面去除。在一些实施例中，栅极填充金属2038a和2038b包括诸如TaN、TiN、W、WN、和WCN或它们的任何组合的复合膜堆叠结构。
为简化起见，在填充栅极填充金属2038a和2038b后，将包括第一功函金属层2036a的金属栅极结构定义为第一金属栅极，并且将包括第二功函金属层2036b的金属栅极结构定义为第二金属栅极。在图10中，回蚀刻第一和第二金属栅极的上部以限定位于第一金属栅极和第二金属栅极中的沟槽。在一些实施例中，第一和第二金属栅极的回蚀刻工艺是湿蚀刻工艺。在一些实施例中，在湿蚀刻工艺中使用的蚀刻剂是磷酸。
在图11中，第一SAC硬掩模107a形成在ILD 101上并且覆盖金属栅极中的沟槽。如图12所示，去除第一SAC硬掩模107a的一部分以达到预定的高度，从而使得第一SAC硬掩模107a的至少部分保留在沟槽中。
参考图13，在第一SAC硬掩模107a和ILD 101的部分上形成光刻胶905，从而使得暴露出第二金属栅极的至少部分。在图14中，去除第二金属栅极中的第一SAC硬掩模107a。
图15至图17示出了在金属栅极上形成第二SAC硬掩模的操作。在图15中，去除光刻胶905。在图16中，形成第二SAC硬掩模107b以毯式覆盖金属栅极和ILD 101。如图17所示，去除过量的第二SAC硬掩模107b并且仅部分保留在第二金属栅极的沟槽中。
由于第一SAC硬掩107a和第二硬掩模107b分别形成，因此可以独立地控制每个硬掩模的性能。器件设计者可以首先决定需要什么类型的应力来提高每个器件的性能，然后确定采用用于相应的金属栅极的什么类型的SAC硬掩模。换句话说，合适的SAC硬掩模用作应力提供件并且可以根据设计者的偏好选择性地施加在金属栅极上。
例如，在一些实施例中，使用PECVD(等离子体增强化学汽相沉积)工艺以形成第一SAC硬掩模107a。PECVD工艺可以具有介于200瓦至3000瓦范围内的RF功率以形成氮化硅膜，从而将拉伸应力引入到第一金属栅极下方的沟道区。对于第二SAC硬掩模107b，使用HDP(高密度等离子体)工艺以形成膜，从而将压缩应力引入到第二金属栅极下方的沟道区。
对于一些实施例，可以扩展SAC硬掩模以覆盖金属栅极的更多的区域。如图18所示，将SAC硬掩模设计为覆盖间隔件1035a和1035b的一部分。在金属栅极上的增大的覆盖度提供了引入至金属栅极下方的沟道区内的更大的应力。
为了用SAC硬掩模覆盖间隔件1035a和1035b的部分，利用如图10所示的类似的操作以形成暴露间隔件1035a和1035b的部分的沟槽。由此，形成如图18中所示的扩展的SAC硬掩模以覆盖间隔件1035a和1035b。
也可以调整在图10中形成的沟槽(203a和203b)以在不同的金属栅极之间具有不同深度，以在其间形成具有不同纵向高度的SAC硬掩模。例如，如图19所示，第一SAC硬掩107a大于第二SAC硬掩模107b。在一些实施例中，可以通过SAC硬掩模的纵向高度调整引入金属栅极下方的沟道区内的应力。
另一种实现第一和第二金属栅极的不同的纵向高度的可选方法可以通过如图16至图17中的CMP操作实现，并且选择性地蚀刻期望的金属栅极。因此，如图20所示，选择的金属栅极比未选择的金属栅极具有更低的纵向高度。
另一种调整金属栅极下方的不同沟道区的应力的方法是改变SAC硬掩模的形状。如图21所示，对于一些实施例，SAC硬掩模107a和107b分别形成为不同的形状。具有横向较长下部的SAC硬掩模可以将拉伸应力引入到金属栅极下方的沟道区，如图21中所示的第一SAC硬掩模107a。具有横向较长上部的SAC硬掩模可以将压缩应力引入到金属栅极下方的沟道区，如图21中所示的第二SAC硬掩模107b。
为了实现两个SAC硬掩模的不同形状，在图10所示的操作期间，可以设计不同的横向侧壁蚀刻以在不同的步骤中去除间隔件1035a和1035b，从而在栅极之间具有不同的沟槽形状。因此，随后的SAC硬掩模可以形成为栅极之间的不同的形状。
如图22所示，对于一些实施例，第一金属栅极凹槽203a和第二金属栅极凹槽203b(在图22未示出)均具有较长的上部并且使得随后形成的金属栅极和SAC硬掩模拥有横向上部。在一些情况下，具有如图22所示的锥形形状的SAC硬掩模具有引入到金属栅极下方的沟道区的压缩应力。
如图23所示，在一些实施例中，形成接触件209a和209b以暴露源极/漏极区1011a和1011b。用于蚀刻ILD 101以暴露源极/漏极区1011a和1011b的蚀刻剂在SAC硬掩模和ILD 101之间具有蚀刻选择性。在一些实施例中，SAC硬掩模包括氮化物并且ILD 101包括氧化物。
在一些实施例中，源极/漏极区1011a和1011b具有突出部分。
在一些实施例中，突出的源极/漏极区1011a和1011b的至少一个是外延层。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。
因此，所附权利要求预期将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在其范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种半导体结构，包括：
半导体衬底，包括第一表面和第二表面；
层间电介质(ILD)，具有位于所述半导体衬底的所述第一表面上方的第一凹槽和位于所述半导体衬底的所述第二表面上方的第二凹槽；
第一间隔件和第二间隔件，所述第一间隔件衬于所述第一凹槽的侧壁上，所述第二间隔件衬于所述第二凹槽的侧壁上；
第一高k介电层和第二高k介电层，所述第一高k介电层接触所述第一凹槽的底部和所述第一间隔件的侧壁，所述第二高k介电层接触所述第二凹槽的底部和所述第二间隔件的侧壁；
第一金属和第二金属，所述第一金属接触所述第一高k介电层的底部和侧壁，所述第二金属接触所述第二高k介电层的底部和侧壁；
其中，所述第一金属和第二金属用于彼此不同导电类型的半导体；以及
第一SAC(自对准接触)硬掩模和第二SAC硬掩模，所述第一SAC硬掩模位于所述第一金属上，所述第二SAC硬掩模位于所述第二金属上，
其中，所述第一SAC硬掩模和所述第二SAC硬掩模对预定的蚀刻剂具有不同的蚀刻速率。
2.根据权利要求1所述的半导体结构，其中，所述第一SAC硬掩模位于所述第一金属和所述第一间隔件上。
3.根据权利要求1所述的半导体结构，其中，所述第二SAC硬掩模位于所述第二金属和所述第二间隔件上。
4.根据权利要求1所述的半导体结构，其中，所述第一SAC硬掩模或所述第二SAC硬掩模包括氮化物。
5.根据权利要求1所述的半导体结构，其中，所述第一SAC硬掩模的纵向高度和所述第二SAC硬掩模的纵向高度基本上彼此不同。
6.根据权利要求1所述的半导体结构，其中，所述第一金属的纵向高度和所述第二金属的纵向高度不同。
7.根据权利要求1所述的半导体结构，其中，所述第一SAC硬掩模具有上部和下部，所述第一SAC硬掩模的所述上部和所述下部的横向长度不同。
8.根据权利要求1所述的半导体结构，其中，所述第二SAC硬掩模具有上部和下部，所述第二SAC硬掩模的所述上部和所述下部的横向长度不同。
9.一种半导体结构，包括：
半导体衬底，包括表面；
层间电介质(ILD)，具有位于所述半导体衬底的所述表面上方的凹槽；
第一间隔件，衬于所述凹槽的侧壁上；
源极/漏极区，位于所述半导体衬底中，邻近所述凹槽下方的沟道区；
高k介电层，接触所述凹槽的底部和所述第一间隔件的侧壁；
金属，接触所述高k介电层的底部和侧壁；以及
SAC硬掩模，位于所述金属上，
其中，所述SAC硬掩模具有上部和下部，并且所述SAC硬掩模的所述上部和所述下部的横向长度不同。
10.一种制造半导体结构的方法，包括：
在层间电介质(ILD)中形成第一凹槽和第二凹槽；
形成衬于所述第一凹槽的侧壁上的第一间隔件和衬于所述第二凹槽的侧壁上的第二间隔件；
形成接触所述第一凹槽的底部和所述第一间隔件的侧壁的第一高k介电层；
形成接触所述第一高k介电层的底部和侧壁的第一金属；
形成接触所述第二凹槽的底部和所述第二间隔件的侧壁的第二高k介电层；
形成接触所述第二高k介电层的底部和侧壁的第二金属；以及
在所述第一金属上形成第一SAC硬掩模和在所述第二金属上形成第二SAC硬掩模；
其中，所述第一SAC硬掩模和所述第二SAC硬掩模对预定的蚀刻剂具有不同的蚀刻速率。
CN201510190639.5A 2014-10-15 2015-04-21 半导体结构及其制造方法 Active CN106158860B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/514,874 2014-10-15
US14/514,874 US9484346B2 (en) 2014-10-15 2014-10-15 Semiconductor structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN106158860A true CN106158860A (zh) 2016-11-23
CN106158860B CN106158860B (zh) 2019-10-15

Family

ID=55749670

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510190639.5A Active CN106158860B (zh) 2014-10-15 2015-04-21 半导体结构及其制造方法

Country Status (4)

Country Link
US (1) US9484346B2 (zh)
KR (1) KR101757521B1 (zh)
CN (1) CN106158860B (zh)
TW (1) TWI629787B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109841570A (zh) * 2017-11-29 2019-06-04 台湾积体电路制造股份有限公司 半导体装置、制造半导体装置的方法及用于执行半导体装置的方法
CN110838487A (zh) * 2018-08-16 2020-02-25 台湾积体电路制造股份有限公司 半导体器件及方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269917B2 (en) * 2016-10-19 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls
US9876010B1 (en) * 2016-11-03 2018-01-23 Globalfoundries Inc. Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure
CN108258033B (zh) * 2016-12-29 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
TWI726128B (zh) * 2017-07-17 2021-05-01 聯華電子股份有限公司 半導體元件及其製作方法
US10269803B2 (en) * 2017-08-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid scheme for improved performance for P-type and N-type FinFETs
US10957543B2 (en) * 2017-09-29 2021-03-23 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method of dielectric layer
US10475788B2 (en) * 2017-11-24 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with capping layer and method for forming the same
KR102392845B1 (ko) 2017-11-28 2022-04-29 삼성전자주식회사 반도체 장치
US11462436B2 (en) 2017-11-30 2022-10-04 Intel Corporation Continuous gate and fin spacer for advanced integrated circuit structure fabrication
US10347540B1 (en) * 2017-12-14 2019-07-09 International Business Machines Corporation Gate cut using selective deposition to prevent oxide loss
US10692778B2 (en) * 2018-08-01 2020-06-23 International Business Machines Corporation Gate-all-around FETs having uniform threshold voltage

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098070A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US20120181630A1 (en) * 2011-01-14 2012-07-19 International Business Machines Corporation Replacement gate with reduced gate leakage current
US20130015525A1 (en) * 2011-07-11 2013-01-17 International Business Machines Corporation Cmos with dual raised source and drain for nmos and pmos
CN104347426A (zh) * 2013-08-06 2015-02-11 格罗方德半导体公司 形成用于晶体管的替换闸极结构的方法及其造成的装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605511B1 (ko) 2004-09-21 2006-07-28 삼성전자주식회사 반도체 장치 내 적어도 하나의 금속 게이트 패턴의형성방법들
US7151023B1 (en) 2005-08-01 2006-12-19 International Business Machines Corporation Metal gate MOSFET by full semiconductor metal alloy conversion
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8445340B2 (en) * 2009-11-19 2013-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Sacrificial offset protection film for a FinFET device
US8329546B2 (en) * 2010-08-31 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Modified profile gate structure for semiconductor device and methods of forming thereof
US9023696B2 (en) * 2011-05-26 2015-05-05 Globalfoundries Inc. Method of forming contacts for devices with multiple stress liners
US9076889B2 (en) * 2011-09-26 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate semiconductor device
US8507979B1 (en) 2012-07-31 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit with metal gate
US8778789B2 (en) * 2012-11-30 2014-07-15 GlobalFoundries, Inc. Methods for fabricating integrated circuits having low resistance metal gate structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098070A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US20120181630A1 (en) * 2011-01-14 2012-07-19 International Business Machines Corporation Replacement gate with reduced gate leakage current
US20130015525A1 (en) * 2011-07-11 2013-01-17 International Business Machines Corporation Cmos with dual raised source and drain for nmos and pmos
CN104347426A (zh) * 2013-08-06 2015-02-11 格罗方德半导体公司 形成用于晶体管的替换闸极结构的方法及其造成的装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109841570A (zh) * 2017-11-29 2019-06-04 台湾积体电路制造股份有限公司 半导体装置、制造半导体装置的方法及用于执行半导体装置的方法
CN109841570B (zh) * 2017-11-29 2021-03-19 台湾积体电路制造股份有限公司 半导体装置、制造半导体装置的方法及用于执行半导体装置的方法
US11532728B2 (en) 2017-11-29 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method semiconductor device fabrication with improved epitaxial source/drain proximity control
CN110838487A (zh) * 2018-08-16 2020-02-25 台湾积体电路制造股份有限公司 半导体器件及方法
US11908750B2 (en) 2018-08-16 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Also Published As

Publication number Publication date
KR101757521B1 (ko) 2017-07-26
CN106158860B (zh) 2019-10-15
TWI629787B (zh) 2018-07-11
US20160111425A1 (en) 2016-04-21
KR20160044394A (ko) 2016-04-25
TW201626563A (zh) 2016-07-16
US9484346B2 (en) 2016-11-01

Similar Documents

Publication Publication Date Title
CN106158860A (zh) 半导体结构及其制造方法
US9768069B2 (en) Method of manufacturing semiconductor device
TWI437708B (zh) 用於場效應電晶體之閘極電極以及場效應電晶體
CN103021862B (zh) 具有低温除氧的金属栅极器件
CN108231588A (zh) 晶体管及其形成方法
US8609484B2 (en) Method for forming high-K metal gate device
CN105789274B (zh) 金属栅极结构及其制造方法
CN109728090A (zh) 一种半导体器件及其形成方法
US11211465B2 (en) Semiconductor device having gate dielectric and inhibitor film over gate dielectric
CN102222610A (zh) 半导体装置的制造方法
CN105470133B (zh) 半导体器件制造方法
CN103545211A (zh) 半导体器件制造方法
CN105405764B (zh) 半导体器件制造方法
TW201729238A (zh) 半導體元件結構及其形成方法
CN108878529A (zh) 半导体器件及其制造方法
CN103839806B (zh) 半导体器件及其制造方法
CN116153863A (zh) 半导体元件及其制作方法
TW202401661A (zh) 一種半導體器件及其製作方法
CN104916590B (zh) 一种半导体器件及其制造方法
CN109119335B (zh) 功函数层、金属栅极、半导体器件及其制造方法
CN107689393B (zh) 一种半导体器件及其制造方法
CN105336784A (zh) 半导体器件及其制造方法
CN107689329A (zh) 鳍式场效应晶体管及其制造方法
CN104143534A (zh) 半导体器件制造方法
CN106158649A (zh) 半导体结构的形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant