TW202401661A - 一種半導體器件及其製作方法 - Google Patents

一種半導體器件及其製作方法 Download PDF

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TW202401661A
TW202401661A TW112108549A TW112108549A TW202401661A TW 202401661 A TW202401661 A TW 202401661A TW 112108549 A TW112108549 A TW 112108549A TW 112108549 A TW112108549 A TW 112108549A TW 202401661 A TW202401661 A TW 202401661A
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substrate
semiconductor device
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陳維邦
吳志楠
鄭志成
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大陸商合肥晶合集成電路股份有限公司
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Abstract

本發明公開了一種半導體器件及其製作方法，所述半導體器件包括：襯底，且所述襯底包括第一區域和第二區域；淺溝槽隔離結構，設置在所述第一區域和所述第二區域上，且所述淺溝槽隔離結構低於所述襯底表面，形成開口；介質層，設置在所述開口內和所述襯底上，且所述介質層在所述第二區域的高度大於在所述第一區域的高度；柵極，設置在所述介質層上；源極，設置在所述襯底上，且所述源極位於所述柵極一側；以及漏極，設置在所述襯底上，且所述漏極位於所述柵極的另一側。通過本發明提供的一種半導體器件及其製作方法，可提高半導體器件的綜合性能。

Description

一種半導體器件及其製作方法
本發明屬於半導體技術領域，特別涉及一種半導體器件及其製作方法。
隨著半導體器件集成度的不斷提高，半導體器件的一個普遍趨勢是半導體器件微小化。且往往需要將多種類型的器件集成在一起進行製作，例如同一襯底上製備不同類型的晶體管，不同晶體管之間通過淺溝槽隔離結構進行隔離。但晶體管尺寸越小，晶體管易出現許多問題，如柵極電流洩露、硼穿透效應以及晶體管邊緣淺溝槽隔離結構出現凹陷等，造成晶體管電性衰減，降低半導體器件的效應。
因此，如何獲得高性能的半導體器件成為亟需解決的問題。
有鑑於此，吾等發明人乃潛心進一步研究，並著手進行研發及改良，期以一較佳發明以解決上述問題，且在經過不斷試驗及修改後而有本發明之問世。
本發明的目的在於提供一種半導體器件及其製作方法，通過本發明提供的一種半導體器件及其製作方法，可以提高半導體器件的綜合性能。
為解決上述技術問題，本發明是通過以下技術方案實現的：
本發明提供一種半導體器件，其至少包括：
襯底，且所述襯底包括第一區域和第二區域；
淺溝槽隔離結構，設置在所述第一區域和所述第二區域上，且所述淺溝槽隔離結構低於所述襯底表面，形成開口；
介質層，設置在所述開口內和所述襯底上，且所述介質層在所述第二區域的高度大於在所述第一區域的高度；
柵極，設置在所述介質層上；
源極，設置在所述襯底上，且所述源極位於所述柵極一側；以及
漏極，設置在所述襯底上，且所述漏極位於所述柵極的另一側。
在本發明一實施例中，所述淺溝槽隔離結構低於所述襯底表面10nm~30nm。
在本發明一實施例中，所述半導體器件包括側牆結構，且所述側牆結構位於所述柵極兩側，所述側牆結構位於所述介質層上。
在本發明一實施例中，所述側牆結構為單層絕緣層或為絕緣層與應力層的堆疊結構。
在本發明一實施例中，所述半導體器件包括鈍化保護層，且所述鈍化保護層設置在所述柵極、所述側牆結構以及所述介質層上。
在本發明一實施例中，所述柵極包括第一金屬柵極，且所述第一金屬柵極兩側的所述襯底中設置有應力區。
在本發明一實施例中，所述應力區向所述第一金屬柵極底部延伸，且延伸至所述側牆結構和所述第一金屬柵極連接處。
在本發明一實施例中，所述柵極包括第二金屬柵極，且所述第二金屬柵極兩側的襯底中設置有輕摻雜區。
在本發明一實施例中，所述介質層在所述第一區域的厚度為2nm~5nm，所述介質層在所述第二區域的厚度為4nm~8nm。
在本發明一實施例中，所述柵極為單層金屬、多層金屬或金屬與金屬化合物堆疊結構。
本發明還提供一種半導體器件的製作方法，包括：
提供一襯底，所述襯底包括第一區域和第二區域；
在所述第一區域和所述第二區域上形成多個淺溝槽隔離結構；
在去除所述襯底上的墊氧化層時，延長刻蝕時間，以移除部分所述淺溝槽隔離結構；
在所述淺溝槽隔離結構上形成低於所述襯底表面的開口；
在所述開口內及所述襯底上形成介質層，且所述介質層在所述第二區域的高度大於在所述第一區域的高度；
在所述介質層上形成柵極；
在所述襯底上形成源極，且所述源極位於所述柵極一側；以及
在所述襯底上形成漏極，且所述漏極位於所述柵極的另一側。
本發明提供的一種半導體器件及其製作方法，能夠減少淺溝槽隔離結構邊緣凹陷現象，提高半導體器件的電學性能。在製備過程中，不添加光罩數目，簡化製作流程，降低成本。且可以增加半導體器件的有效寬度，增加半導體器件的效能。綜上所述，通過本發明提供一種半導體器件及其製作方法，可提高半導體器件的性能。
當然，實施本發明的任一產品並不一定需要同時達到以上所述的所有優點。
關於吾等發明人之技術手段，茲舉數種較佳實施例配合圖式於下文進行詳細說明，俾供  鈞上深入瞭解並認同本發明。
以下通過特定的具體實例說明本發明的實施方式，本發明所屬技術領域中具有通常知識者可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用，本說明書中的各項細節也可以基於不同觀點與應用，在沒有背離本發明的精神下進行各種修飾或改變。
需要說明的是，本實施例中所提供的圖示僅以示意方式說明本發明的基本構想，遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的組件數目、形狀及尺寸繪製，其實際實施時各組件的型態、數量及比例可為一種隨意的改變，且其組件佈局型態也可能更為複雜。
在本發明中，需要說明的是，如出現術語“中心”、“上”、“下”、“左”、“右”、“豎直”、“水平”、“內”、“外”等，其所指示的方位或位置關係為基於附圖所示的方位或位置關係，僅是為了便於描述本申請和簡化描述，而不是指示或暗示所指的裝置或元件必須具有特定的方位、以特定的方位構造和操作，因此不能理解為對本申請的限制。此外，如出現術語“第一”、“第二”僅用於描述和區分目的，而不能理解為指示或暗示相對重要性。
本發明提供一種半導體器件及其製作方法，可在同一襯底的不同區域製備不同功能的半導體器件，且每個半導體器件具有優異性能。且本發明提供的半導體器件的製作方法，可廣泛應用於各種微小半導體器件的製程中。
請參閱圖1所示，在本發明一實施例中，襯底110例如包括第一區域1和第二區域2，且在第一區域1和第二區域2內可設置多個金氧半場效晶體管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOS），例如包括P型金氧半場效晶體管（Positive Channel Metal Oxide Semiconductor，PMOS）和N型金氧半場效晶體管（Negative Channel Metal Oxide Semiconductor，NMOS），且PMOS晶體管和NMOS晶體管交錯排列。通過在同一襯底的不同區域製備半導體器件，提高生產效率，降低生產成本。
請參閱圖1所示，在本發明一實施例中，首先提供襯底110，且襯底110可以為任意適於形成的材料，例如為矽片、鍺襯底、矽鍺、絕緣體上矽或絕緣體上層疊矽等。本發明並不限制襯底110的種類和厚度，在本實施例中，襯底110例如選擇矽片進行闡述，且襯底110例如為P型矽片，襯底110例如包括第一區域1和第二區域2。其中，第一區域1例如設置器件內部使用的Core MOS，一般工作電壓較低。第二區域2例如設置與Core MOS晶體管相對應的邊緣金氧半場效晶體管，即IO MOS晶體管，一般用於芯片與外部接口交互，工作電壓較Core MOS晶體管的工作電壓高。在本實施例中，以第一區域1包括一個PMOS晶體管和NMOS晶體管以及第二區域2包括一個PMOS晶體管和NMOS晶體管為例進行闡述，且PMOS晶體管和NMOS晶體管交替分佈，PMOS晶體管和NMOS晶體管之間通過淺溝槽隔離結構進行隔離。
請參閱圖1所示，在本發明一實施例中，在襯底110上形成多個淺溝槽隔離結構，具體地，在襯底110上形成墊氧化層120，且墊氧化層120例如為緻密的氧化矽等材料，墊氧化層120例如可以通過熱氧化法、原位水汽生長法或化學氣相沉積（Chemical Vapor Deposition，CVD）等方法製備。在墊氧化層120上形成墊氮化層130，且墊氮化層130例如為氮化矽或氮化矽和氧化矽的混合物，墊氮化層130可通過化學氣相澱積等方法形成。在形成淺溝槽隔離結構過程中，墊氧化層120可以改善襯底110與墊氧化層120之間的應力，同時可在進行離子注入形成阱區時，保護襯底110，防止襯底110被高能量離子損傷。在墊氮化層130上形成圖案化光阻層140，圖案化光阻層140上設置多個第一凹部141，第一凹部141用來定義淺溝槽隔離結構的位置，且第一凹部141暴露出墊氮化層130。
請參閱圖1至圖2所示，在本發明一實施例中，在形成圖案化光阻層140後，以圖案化光阻層140為掩膜，例如使用幹法刻蝕向襯底110的方向進行刻蝕，形成淺溝槽，且刻蝕氣體例如可以是氯氣（Cl2）、三氟甲烷（CHF3）、二氟甲烷（CH2F2）、三氟化氮（NF3）、六氟化硫（SF6）或溴化氫（HBr）等中的一種或幾種混合。在淺溝槽內例如通過熱氧化法在淺溝槽內形成一內襯氧化層（圖中未顯示），以修復在形成淺溝槽的過程中的刻蝕損傷，減少半導體器件漏電情況。在淺溝槽內例如通過高密度等離子體化學氣相澱積（High Density Plasma CVD，HDP-CVD）或高深寬比化學氣相澱積（High Aspect Ratio Process CVD，HARP-CVD）等方式沉積隔離介質，且隔離介質例如為氧化矽等絕緣物質。在隔離介質沉積完成後，例如通過化學機械拋光（Chemical Mechanical Polishing，CMP）工藝平坦化隔離介質和墊氮化層130，形成淺溝槽隔離結構150，且淺溝槽隔離結構150與兩側的墊氧化層120齊平。
請參閱圖3所示，在本發明一實施例中，在淺溝槽隔離結構150製備完成後，對襯底110進行離子注入，以形成不同的阱區。首先，以高注入能量注入比襯底110濃度高的摻雜離子，即在襯底110內形成第一阱區160。在形成NMOS晶體管的區域以高注入能量注入比第一阱區160濃度高的摻雜離子，以形成第二阱區170，且第二阱區170位於部分第一阱區160上。在本實施例中，第一阱區160和第二阱區170的類型不同，其中，第一阱區160例如設置為N型深阱，摻雜離子為磷（P）、砷（As）或鋁（Al）等，第二阱區170例如設置為P型深阱，摻雜離子為硼（B）或鎵（Ga）等。在第一阱區160和第二阱區170形成後，對在第一阱區160和第二阱區170進行快速熱退火製程（Rapid Thermal Anneal，RTA），在本實施例中，退火溫度例如為1000℃~1400℃，退火時間例如為1h~3h，且退火製程是在穩定氣體氛圍下進行，例如在氮氣氛圍下進行。通過退火製程，使得第一阱區160和第二阱區170的離子注入至合適深度，同時提高半導體器件的抗雪崩擊穿能力。
請參閱圖3至圖4所示，在本發明一實施例中，在第一阱區160和第二阱區170形成之後，去除墊氧化層120。在本實施例中，例如採用濕法刻蝕去除墊氧化層120，且濕法刻蝕液例如選用氫氟酸，在常溫下進行刻蝕。在其他實施例中，也可採用其他刻蝕方式，根據具體的製作要求進行選擇。同時，在去除墊氧化層120時，延長刻蝕時間，去除部分淺溝槽隔離結構150中的隔離介質，形成開口11，且開口11的深度例如為10nm~30nm，即刻蝕後開口11的下表面低於兩側的襯底110表面，高度差例如為10nm~30nm。通過設置開口11，可避免在去除墊氧化層120時，在淺溝槽隔離結構150的邊緣形成凹陷，從而減少漏電的發生，提高半導體器件的電學性能。同時，去除墊氧化層120和形成開口11在同一製程中形成，光罩數目不變，不會增加光阻和刻蝕的步驟，降低成本。
請參閱圖5和圖15所示，在本發明一實施例中，在開口11形成後，在開口11內以及襯底110上沉積高介電常數材料，形成介質層180，以作為半導體器件的柵介質層。在本實施例中，介質層180例如可通過利用原子層沉積法（Atomic Layer Deposition，ALD）、金屬有機氣相沉積法（Metal-Organic Chemical Vapor Deposition，MOCVD）、分子束外延法（Molecular BeamEpitaxy，MBE）、化學氣相沉積法或物理氣相沉積法（Physical Vapor Deposition，PVD）等方法形成。且介質層180例如為氧化鉿（HfO2）、氮氧化鉿（HfON）、氧化鋯（ZrO2）、氮氧化鋯（ZrON）、氧氮矽酸鋯（ZrSiON）、矽酸鉿（HfSiO）、氧氮矽酸鉿（HfSiON）、鑭氧氮化鉿（HfLaON）或氧化鉿鋁（HfAlO）等中的一種或幾種混合。因介質層180選擇高介電常數介質材料，與襯底110之間的界面品質較差，因此，在沉積介質層180之前，例如採用原位水汽生成（In-Situ Steam Generation，ISSG）在襯底110上以及開口11的側壁上形成一層界面層111，且界面層111的厚度例如為0.5nm~1.5nm，以改善介質層180與襯底110之間的界面品質。在介質層180沉積完成，對介質層180進行平坦化工藝，因第二區域2的晶體管的工作電壓較高，所以在第一區域1和第二區域2上，介質層180的保留厚度不同。在本實施例中，介質層180在第一區域1的阱區上的厚度例如2nm~5nm，介質層180在第二區域2的阱區上的厚度例如4nm~8nm，可提高第二區域2上晶體管的壓耐。通過設置開口11及介質層180，增加了後續晶體管的有效寬度，從而提高器件的性能，並減少漏電流的現象。
請參閱圖6所示，在本發明一實施例中，在介質層180形成後，在介質層180上形成偽柵極190。具體的，在介質層180上依次形成保護層191、多晶矽層192、遮蔽層193以及抗反射層194。在本實施例中，保護層191例如為氮化鈦等，且例如採用原子層沉積方法（Atomic Layer Deposition，ALD）製備保護層191，通過設置保護層191，可以在後續製備過程中，防止介質層180受到污染或損傷，可提高後續製備的金屬柵極的性能。多晶矽層192例如為N型摻雜的多晶矽層，可以在後續製程中，提高多晶矽層192的去除速度。遮蔽層193例如為氮化矽、氮化鈦或氮碳化矽等中的一種或多種。抗反射層194例如為氮氧化矽等反射材料，以確保在形成偽柵極190的過程中，保證偽柵極190的結構完整性。在抗反射層194上形成圖案的化光阻層（圖中未顯示），後對抗反射層194、遮蔽層193、多晶矽層192以及保護層191進行刻蝕，且介質層180作為刻蝕停止層，在介質層180上形成層疊的柱狀結構，去除遮蔽層193和抗反射層194，在介質層180上形成偽柵極190，且偽柵極190位於第一阱區160和第二阱區170上。
請參閱圖7所示，在本發明一實施例中，在偽柵極190形成後，在偽柵極190的兩側形成側牆結構200，即側牆結構200形成於偽柵極190的側面，且側牆結構200位於介質層180上，側牆結構200的邊緣與位於偽柵極190下方的介質層180的邊緣重合。在本實施例中，側牆結構200為疊層結構，其中，側牆結構200例如包括第一絕緣層201、第一應力層202、第二絕緣層203和第二應力層204，絕緣層例如為氧化矽等，應力層例如為氮化矽等。即側牆結構200為氧化矽層/氮化矽層的疊層，其中應力層可以在去除偽柵極190的過程中，確保側牆結構的穩定，減少因側牆結構內傾而導致的後續柵極沉積不均勻，提高柵極結構的均勻性，從而提高半導體結構的閾值電壓的穩定性。在其他實施例中，側牆結構200也可以為單層絕緣層或其他結構。通過將側牆結構設置為多層結構，減少側牆結構在後續製程中的損失。
請參閱圖8至圖9所示，在本發明一實施例中，在側牆結構200形成後，在第二阱區170中形成輕摻雜區210，且輕摻雜區210位於側牆結構200與淺溝槽隔離結構150之間，並與側牆結構200與淺溝槽隔離結構150相鄰，以改善形成的晶體管的短溝道效應。具體地，以較低注入能量注入摻雜離子，因此，形成的輕摻雜區210位於第二阱區170靠近介質層180的一側。其中，注入的摻雜離子例如為磷、砷或鋁等N型離子，輕摻雜區210可以作為NMOS晶體管的源極或漏極區。在輕摻雜區210後，去除淺溝槽隔離結構150、第一阱區160以及第二阱區170上的介質層180，保留偽柵極190及側牆結構200覆蓋區域的介質層180，保留開口11內的介質層180，且開口11內的介質層180與襯底110齊平。在本實施例中，介質層180可通過幹法刻蝕、濕法刻蝕或幹法刻蝕與濕法刻蝕相結合去除。通過在形成輕摻雜區210後去除介質層180，可防止在形成輕摻雜區210時，對第二阱區170的損傷，從而提高半導體器件的性能。
請參閱圖10至圖11所示，在本發明一實施例中，在去除介質層180後，在第一阱區160上形成凹槽12，且凹槽12位於側牆結構200與淺溝槽隔離結構150之間，並與側牆結構200與淺溝槽隔離結構150相鄰。具體地，在襯底110上形成圖案的化光阻層（圖中未顯示），通過幹法刻蝕或濕法刻蝕第一阱區160上側牆結構200兩側的襯底110，形成凹槽12。在本實施例中，凹槽12的側壁呈開口多邊形設置，可以擴大後續沉積應力區220與晶體管溝道區域的接觸面積，提高溝道區域受到的應力作用，從而提高溝道區域內的遷移率。在凹槽12內沉積半導體材料以形成應力區220，且應力區220可以作為PMOS晶體管的源極區或漏極區。在本實施例中，應力區220例如為矽鍺（SiGe），且SiGe為摻雜了P型雜質的SiGe。其中應力區220的形狀和凹槽12形狀一致，例如為多邊形形狀，且多邊形的一邊與淺溝槽隔離結構150相鄰，應力區220向偽柵極190底部延伸，且延伸至側牆結構200和偽柵極190連接處。通過設置應力區220延伸至側牆結構200和偽柵極190連接處，可避免應力區220延伸至偽柵極190底部時，而導致的漏電流現象，同時，當應力區220未延伸至側牆結構200和偽柵極190連接處時，應力區220之間的溝道區域寬度較大，載流子遷移率降低，影響半導體器件性能。因此，通過將應力區220延伸至側牆結構200和偽柵極190連接處時，半導體器件的電性可以達到最好效能。在本實施例中，應力區220例如通過低溫外延工藝沉積製備，採用低溫外延工藝的外源氣體包括鍺源氣體、矽源氣體、氯化氫氣體和氫氣等，通過調整鍺源氣體和矽源氣體的比例，調節應力區220中鍺的比例，且應力區220中鍺的比例例如為20%~40%。通過控制鍺的含量，可以減小應力區220與凹槽12內壁的晶格常數差異，減少應力區220內的缺陷。在應力區220形成後，對輕摻雜區210和應力區220進行激活，例如將襯底110進行快速熱退火。通過快速熱退火，能夠修復製作過程中產生的晶格缺陷、激活摻雜離子和最小化摻雜離子擴散三者之間取得優化，進而激活應力層和輕摻雜區，且快速熱退火還能減小瞬時增強擴散。
請參閱圖12所示，在本發明一實施例中，在偽柵極190、輕摻雜區210和應力區220形成自對準矽化物阻擋層（Self-Aligned Block，SAB）230。具體地，在介質層180、偽柵極190、輕摻雜區210和應力區220上形成金屬層（圖中未顯示），且金屬層例如為鈦層（Ti）、鈷層（Co）或鎳層（Ni）等。然後對襯底110進行第一次退火，第一次退火的溫度例如為300℃~350℃，使得金屬原子與偽柵極190、輕摻雜區210或應力區220中的矽原子反應，形成中間矽化物層，然後通過化學溶液選擇去除未反應的金屬層，並對中間矽化物層進行第二次退火，第二次退火的溫度比第一次退火的溫度高，第二次退火的溫度例如為400℃~500℃。中間矽化物層經過退火之後轉化為矽化物層，也就是自對準矽化物阻擋層230。自對準矽化物阻擋層230具有良好的熱穩定性，可以降低器件的電阻，其保證與後期製備的金屬電極接觸良好。
請參閱圖6和圖13所示，在本發明一實施例中，在形成自對準矽化物阻擋層230後，去除偽柵極190頂部的自對準矽化物阻擋層230和偽柵極190中的多晶矽層192，保留偽柵極190中的保護層191，以形成溝槽13，即溝槽13暴露出保護層191。在去除多晶矽層192時，可採用幹法刻蝕、濕法刻蝕或幹法刻蝕和濕法刻蝕相結合。當採用幹法刻蝕時，可以選擇氯氣、溴氣、氦氣、溴化氫或者其中至少一種氣體和氧氣的混合氣體，幹法刻蝕各向異性、選擇性好以及刻蝕效率高。當採用濕法刻蝕時，可選用四甲基氫氧化銨溶液或氫氧化鉀溶液去除多晶矽層192，採用濕法刻蝕的優點是操作簡便、對設備要求低、易於大批量生產。在刻蝕過程中，側牆結構200保留，用來定位金屬柵極的位置並作為後期製備金屬柵極的側牆結構。
請參閱圖14至圖16所示，在本發明一實施例中，在形成溝槽13後，在溝槽13內沉積金屬，形成金屬柵極260，且金屬柵極260例如為單層金屬、多層金屬或金屬化合物堆疊等結構。其中，金屬柵極260包括第一金屬柵極240和第二金屬柵極250，第一金屬柵極240為PMOS晶體管的金屬柵極，第二金屬柵極250為NMOS晶體管的金屬柵極。
請參閱圖14至圖15所示，在本發明一實施例中，圖15為第一金屬柵極240在襯底110上的結構示意圖。第一金屬柵極240包括介質層180、保護層191、第一阻擋層241、第一功函數金屬層242和第一金屬導電層243。其中，介質層180為高介電常數介質層，保護層191在形成偽柵極的過程中形成，減少對介質層180的損傷。第一阻擋層241形成在保護層191上，第一阻擋層241的材料可為氮化鈦（TiN）或氮化鉭（TaN）等金屬化合物或其疊層。在本實施例中，第一阻擋層241包括氮化鈦層或氮化鉭層，其中，氮化鉭層設置在保護層191上，氮化鈦層設置在氮化鉭層上。且第一阻擋層241可利用原子層沉積、物理氣相沉積或化學氣相沉積等方法形成。第一功函數金屬層242設置在第一阻擋層241上，且第一功函數金屬層242例如為P型功函數金屬層，其材料可以為氮化鉭、氮化鈦、鋁化鈦（TiAl）、氮化鈦鋁（TiAIN）或氮化鎢（WN）等中的一種或疊層。在本實施例中，第一功函數金屬層242例如為鋁化鈦層和氮化鈦的疊層，其中鋁化鈦層設置在第一阻擋層241上，氮化鈦設置在鋁化鈦層上，且第一功函數金屬層242例如通過等離子體增強化學的氣相沉積法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、原子層沉積或物理氣相沉積等方法形成。在第一功函數金屬層242層上形成第一金屬導電層243，且第一金屬導電層243例如為金屬鎢、銅或銀等導電性較好的金屬，提高晶體管的電性性能，第一金屬導電層243例如通過磁控濺射或蒸鍍等方式形成。在第一金屬導電層243形成後，進行平坦化製程，提高第一金屬導電層243的平整度。
請參閱圖14和圖16所示，在本發明一實施例中，圖16為第二金屬柵極250在襯底110上的層結構示意圖。第二金屬柵極250包括介質層180、保護層191、第二阻擋層251、第二功函數金屬層252和第二金屬導電層253。其中，介質層180為高介電常數介質層，保護層191在形成偽柵極的過程中形成，減少對介質層180的損傷。第二阻擋層251形成在保護層191上，第二阻擋層251的材料可為氮化鈦或氮化鉭等金屬化合物或其疊層。在本實施例中，第二阻擋層251例如為氮化鉭層，且第二阻擋層251可利用原子層沉積、物理氣相沉積或化學氣相沉積等方法形成。第二功函數金屬層252設置在第二阻擋層251上，且第二功函數金屬層252例如為N型功函數金屬層，其材料可以為氮化鉭、氮化鈦、鋁化鈦、氮化鈦鋁或氮化鎢等中的一種或疊層。在本實施例中，第二功函數金屬層252例如為鋁化鈦層和氮化鈦的疊層，其中鋁化鈦層設置在第二阻擋層251上，氮化鈦設置在鋁化鈦層上，且第二功函數金屬層252例如通過等離子體增強化學的氣相沉積法、原子層沉積或物理氣相沉積等方法形成。在第二功函數金屬層252層上形成第二金屬導電層253，且第二金屬導電層253例如為金屬鎢、銅或銀等導電性較好的金屬，提高晶體管的電性性能，第二金屬導電層253例如通過磁控濺射或蒸鍍等方式形成。在第二金屬導電層253形成後，進行平坦化製程，提高第二金屬導電層253的平整度。在本實施例中，NMOS晶體管和PMOS晶體管的金屬柵極的金屬導電層可以連接起來，也可以相互斷開，可根據實際生產進行調整，且當金屬導電層互相連接時，金屬導電層在淺溝槽隔離結構150上的高度小於在襯底110上的高度，金屬導電層在淺溝槽隔離結構150上的高度比在襯底110上的高度低，且高度差例如為5nm及以上。
請參閱圖17所示，在本發明一實施例中，在金屬柵極260形成後，在襯底110靠近金屬柵極260的一側形成鈍化保護層270，即鈍化保護層270覆蓋金屬柵極260、介質層180、自對準矽化物阻擋層230以及側牆結構200。其中，鈍化保護層270在金屬柵極260和自對準矽化物阻擋層230的位置上設置有第二凹部14，暴露出金屬柵極260和自對準矽化物阻擋層230，以定位金屬電極的位置以及連接金屬電極。在本實施例中，鈍化保護層270例如為氧化矽或氧化鈦等絕緣材料，可以保護器件並提高器件的耐壓性。通過設置鈍化保護層270可以提高器件的使用壽命，提高器件的性能。
請參閱圖17至圖18所示，在本發明一實施例中，在所述襯底110上形成絕緣層280，絕緣層覆蓋全部襯底110的表面，且絕緣層280例如設置為氧化矽層。在形成絕緣層280後，進行平坦化工藝，且在絕緣層280上設置多個通道，通道位於第二凹部14上，且通道暴露出金屬柵極260和自對準矽化物阻擋層230，在通道內設置金屬連線，例如鎢、銅或銀等金屬，以形成電極。電極包括源極21、柵極22和漏極23，其中，源極21位於金屬柵極260的一側，且與自對準矽化物阻擋層230連接。柵極22設置在金屬柵極260上，且與金屬柵極260的金屬導電層連接。漏極23設置在金屬柵極260的另一側，且與自對準矽化物阻擋層230連接。
綜上所述，本發明提供一種半導體器件及其製作方法，在形成偽柵極之前，形成介質層，提高半導體器件的電學性能，且可以增加半導體器件的有效寬度，增加半導體器件的效能。提高同一襯底上不同功能的半導體器件的性能，獲得高質量半導體器件。
綜上所述，本發明所揭露之技術手段確能有效解決習知等問題，並達致預期之目的與功效，且申請前未見諸於刊物、未曾公開使用且具長遠進步性，誠屬專利法所稱之發明無誤，爰依法提出申請，懇祈  鈞上惠予詳審並賜准發明專利，至感德馨。
惟以上所述者，僅為本發明之數種較佳實施例，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明書內容所作之等效變化與修飾，皆應仍屬本發明專利涵蓋之範圍內。
〔本發明〕 11:開口 110:襯底 12:凹槽 120:墊氧化層 13:溝槽 130:墊氮化層 14:第二凹部 140:圖案化光阻層 141:第一凹部 150:淺溝槽隔離結構 160:第一阱區 170:第二阱區 180:介質層 190:偽柵極 191:保護層 192:多晶矽層 193:遮蔽層 194:抗反射層 200:側牆結構 201:第一絕緣層 202:第一應力層 203:第二絕緣層 204:第二應力層 21:源極 210:輕摻雜區 22:柵極 220:應力區 23:漏極 230:自對準矽化物阻擋層 240:第一金屬柵極 241:第一阻擋層 242:第一功函數金屬層 243:第一金屬導電層 250:第二金屬柵極 251:第二阻擋層 252:第二功函數金屬層 253:第二金屬導電層 260:金屬柵極 270:鈍化保護層 280:絕緣層
為了更清楚地說明本發明實施例的技術方案，下面將對實施例描述所需要使用的附圖作簡單地介紹，顯而易見地，下面描述中的附圖僅僅是本發明的一些實施例，對於本發明所屬技術領域中具有通常知識者來講，在不付出進步性勞動的前提下，還可以根據這些附圖獲得其他的附圖。 [圖1]為一實施例中襯底分佈示意圖; [圖2]為一實施例中淺溝槽隔離結構示意圖; [圖3]為一實施例中阱區分佈示意圖; [圖4]為一實施例中開口示意圖; [圖5]為一實施例中介質層示意圖; [圖6]為一實施例中偽柵極示意圖; [圖7]為一實施例中側牆結構示意圖; [圖8]為一實施例中輕摻雜區結構示意圖; [圖9]至[圖11]為一實施例中形成應力區的示意圖; [圖12]為一實施例中自對準矽化物阻擋層示意圖; [圖13]為一實施例中去除多晶矽層示意圖; [圖14]為一實施例中金屬柵極示意圖; [圖15]為一實施例中第一金屬柵極在襯底上的結構示意圖; [圖16]部分為一實施例中第二金屬柵極在襯底上的結構示意圖; [圖17]為一實施例中鈍化保護層示意圖; [圖18]為一實施例中具有PMOS晶體管和NMOS晶體管的半導體器件示意圖。
110:襯底
150:淺溝槽隔離結構
160:第一阱區
170:第二阱區
180:介質層
21:源極
210:輕摻雜區
22:柵極
23:漏極
280:絕緣層

Claims (11)

  1. 一種半導體器件，其特徵在於，包括： 襯底，且所述襯底包括第一區域和第二區域； 淺溝槽隔離結構，設置在所述第一區域和所述第二區域上，且所述淺溝槽隔離結構低於所述襯底表面，形成開口； 介質層，設置在所述開口內和所述襯底上，且所述介質層在所述第二區域的高度大於在所述第一區域的高度； 柵極，設置在所述介質層上； 源極，設置在所述襯底上，且所述源極位於所述柵極一側；以及 漏極，設置在所述襯底上，且所述漏極位於所述柵極的另一側。
  2. 如請求項1所述之半導體器件，其中，所述淺溝槽隔離結構低於所述襯底表面10nm~30nm。
  3. 如請求項1所述之半導體器件，其中，所述半導體器件包括側牆結構，且所述側牆結構位於所述柵極兩側，所述側牆結構位於所述介質層上。
  4. 如請求項3所述之半導體器件，其中，所述側牆結構為單層絕緣層或為絕緣層與應力層的堆疊結構。
  5. 如請求項3所述之半導體器件，其中，所述半導體器件包括鈍化保護層，且所述鈍化保護層設置在所述柵極、所述側牆結構以及所述介質層上。
  6. 如請求項3所述之半導體器件，其中，所述柵極包括第一金屬柵極，且所述第一金屬柵極兩側的所述襯底中設置有應力區。
  7. 如請求項6所述之半導體器件，其中，所述應力區向所述第一金屬柵極底部延伸，且延伸至所述側牆結構和所述第一金屬柵極連接處。
  8. 如請求項1所述之半導體器件，其中，所述柵極包括第二金屬柵極，且所述第二金屬柵極兩側的襯底中設置有輕摻雜區。
  9. 如請求項1所述之半導體器件，其中，所述介質層在所述第一區域的厚度為2nm~5nm，所述介質層在所述第二區域的厚度為4nm~8nm。
  10. 如請求項1所述之半導體器件，其中，所述柵極為單層金屬、多層金屬或金屬與金屬化合物堆疊結構。
  11. 一種半導體器件的製作方法，其特徵在於，包括： 提供一襯底，所述襯底包括第一區域和第二區域； 在所述第一區域和所述第二區域上形成多個淺溝槽隔離結構； 在去除所述襯底上的墊氧化層時，延長刻蝕時間，以移除部分所述淺溝槽隔離結構； 在所述淺溝槽隔離結構上形成低於所述襯底表面的開口； 在所述開口內及所述襯底上形成介質層，且所述介質層在所述第二區域的高度大於在所述第一區域的高度； 在所述介質層上形成柵極； 在所述襯底上形成源極，且所述源極位於所述柵極一側；以及 在所述襯底上形成漏極，且所述漏極位於所述柵極的另一側。
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