CN114784003A - 一种半导体器件及其制作方法 - Google Patents

一种半导体器件及其制作方法 Download PDF

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CN114784003A
CN114784003A CN202210701263.XA CN202210701263A CN114784003A CN 114784003 A CN114784003 A CN 114784003A CN 202210701263 A CN202210701263 A CN 202210701263A CN 114784003 A CN114784003 A CN 114784003A
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layer
substrate
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semiconductor device
dielectric layer
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CN114784003B (zh
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陈维邦
吴志楠
郑志成
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Nexchip Semiconductor Corp
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Priority to KR1020230042261A priority patent/KR20230174699A/ko
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Abstract

本发明公开了一种半导体器件及其制作方法，所述半导体器件包括：衬底，且所述衬底包括第一区域和第二区域；浅沟槽隔离结构，设置在所述第一区域和所述第二区域上，且所述浅沟槽隔离结构低于所述衬底表面，形成开口；介质层，设置在所述开口内和所述衬底上，且所述介质层在所述第二区域的高度大于在所述第一区域的高度；栅极，设置在所述介质层上；源极，设置在所述衬底上，且所述源极位于所述栅极一侧；以及漏极，设置在所述衬底上，且所述漏极位于所述栅极的另一侧。通过本发明提供的一种半导体器件及其制作方法，可提高半导体器件的综合性能。

Description

一种半导体器件及其制作方法
技术领域
本发明属于半导体技术领域，特别涉及一种半导体器件及其制作方法。
背景技术
随着半导体器件集成度的不断提高，半导体器件的一个普遍趋势是半导体器件微小化。且往往需要将多种类型的器件集成在一起进行制作，例如同一衬底上制备不同类型的晶体管，不同晶体管之间通过浅沟槽隔离结构进行隔离。但晶体管尺寸越小，晶体管易出现许多问题，如栅极电流泄露、硼穿透效应以及晶体管边缘浅沟槽隔离结构出现凹陷等，造成晶体管电性衰减，降低半导体器件的效应。
因此，如何获得高性能的半导体器件成为亟需解决的问题。
发明内容
本发明的目的在于提供一种半导体器件及其制作方法，通过本发明提供的一种半导体器件及其制作方法，可以提高半导体器件的综合性能。
为解决上述技术问题，本发明是通过以下技术方案实现的：
本发明提供一种半导体器件，其至少包括：
衬底，且所述衬底包括第一区域和第二区域；
浅沟槽隔离结构，设置在所述第一区域和所述第二区域上，且所述浅沟槽隔离结构低于所述衬底表面，形成开口；
介质层，设置在所述开口内和所述衬底上，且所述介质层在所述第二区域的高度大于在所述第一区域的高度；
栅极，设置在所述介质层上；
源极，设置在所述衬底上，且所述源极位于所述栅极一侧；以及
漏极，设置在所述衬底上，且所述漏极位于所述栅极的另一侧。
在本发明一实施例中，所述浅沟槽隔离结构低于所述衬底表面10nm~30nm。
在本发明一实施例中，所述半导体器件包括侧墙结构，且所述侧墙结构位于所述栅极两侧，所述侧墙结构位于所述介质层上。
在本发明一实施例中，所述侧墙结构为单层绝缘层或为绝缘层与应力层的堆叠结构。
在本发明一实施例中，所述半导体器件包括钝化保护层，且所述钝化保护层设置在所述栅极、所述侧墙结构以及所述介质层上。
在本发明一实施例中，所述栅极包括第一金属栅极，且所述第一金属栅极两侧的所述衬底中设置有应力区。
在本发明一实施例中，所述应力区向所述第一金属栅极底部延伸，且延伸至所述侧墙结构和所述第二金属栅极连接处。
在本发明一实施例中，所述栅极包括第二金属栅极，且所述第二金属栅极两侧的衬底中设置有轻掺杂区。
在本发明一实施例中，所述介质层在所述第一区域的厚度为2nm~5nm，所述介质层在所述第二区域的厚度为4nm~8nm。
在本发明一实施例中，所述栅极为单层金属、多层金属或金属与金属化合物堆叠结构。
本发明还提供一种半导体器件的制作方法，包括：
提供一衬底，所述衬底包括第一区域和第二区域；
在所述第一区域和所述第二区域上形成多个浅沟槽隔离结构；
在去除所述衬底上的垫氧化层时，延长刻蚀时间，以移除部分所述浅沟槽隔离结构；
在所述浅沟槽隔离结构上形成低于所述衬底表面的开口；
在所述开口内及所述衬底上形成介质层，且所述介质层在所述第二区域的高度大于在所述第一区域的高度；
在所述介质层上形成栅极；
在所述衬底上形成源极，且所述源极位于所述栅极一侧；以及
在所述衬底上形成漏极，且所述漏极位于所述栅极的另一侧。
本发明提供的一种半导体器件及其制作方法，能够减少浅沟槽隔离结构边缘凹陷现象，提高半导体器件的电学性能。在制备过程中，不添加光罩数目，简化制作流程，降低成本。且可以增加半导体器件的有效宽度，增加半导体器件的效能。综上所述，通过本发明提供一种半导体器件及其制作方法，可提高半导体器件的性能。
当然，实施本发明的任一产品并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中衬底分布示意图。
图2为一实施例中浅沟槽隔离结构示意图。
图3为一实施例中阱区分布示意图。
图4为一实施例中开口示意图。
图5为一实施例中介质层示意图。
图6为一实施例中伪栅极示意图。
图7为一实施例中侧墙结构示意图。
图8为一实施例中轻掺杂区结构示意图。
图9至图11为一实施例中形成应力区的示意图。
图12为一实施例中自对准硅化物阻挡层示意图。
图13为一实施例中去除多晶硅层示意图。
图14为一实施例中金属栅极示意图。
图15为一实施例中第一金属栅极在衬底上的结构示意图。
图16为一实施例中第二金属栅极在衬底上的结构示意图。
图17为一实施例中钝化保护层示意图。
图18为一实施例中具有PMOS晶体管和NMOS晶体管的半导体器件示意图。
标号说明：
110衬底；120垫氧化层；130垫氮化层；140图案化光阻层；141第一凹部；150浅沟槽隔离结构；160第一阱区；170第二阱区；180介质层；190伪栅极；191保护层；192多晶硅层；193遮蔽层；194抗反射层；200侧墙结构；201第一绝缘层；202第一应力层；203第二绝缘层；204第二应力层；210轻掺杂区；220应力区；230自对准硅化物阻挡层；240第一金属栅极；241第一阻挡层；242第一功函数金属层；243第一金属导电层；250第二金属栅极；251第二阻挡层；252第二功函数金属层；253第二金属导电层；260金属栅极；270钝化保护层；280绝缘层；11开口；12凹槽；13沟槽；14第二凹部；21源极；22栅极；23漏极。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
在本发明中，需要说明的是，如出现术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等，其所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，如出现术语“第一”、“第二”仅用于描述和区分目的，而不能理解为指示或暗示相对重要性。
本发明提供一种半导体器件及其制作方法，可在同一衬底的不同区域制备不同功能的半导体器件，且每个半导体器件具有优异性能。且本发明提供的半导体器件的制作方法，可广泛应用于各种微小半导体器件的制程中。
请参阅图1所示，在本发明一实施例中，衬底110例如包括第一区域1和第二区域2，且在第一区域1和第二区域2内可设置多个金氧半场效晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOS），例如包括P型金氧半场效晶体管（Positive Channel Metal Oxide Semiconductor，PMOS）和N型金氧半场效晶体管（Negative Channel Metal Oxide Semiconductor，NMOS），且PMOS晶体管和NMOS晶体管交错排列。通过在同一衬底的不同区域制备半导体器件，提高生产效率，降低生产成本。
请参阅图1所示，在本发明一实施例中，首先提供衬底110，且衬底110可以为任意适于形成的材料，例如为硅片、锗衬底、硅锗、绝缘体上硅或绝缘体上层叠硅等。本发明并不限制衬底110的种类和厚度，在本实施例中，衬底110例如选择硅片进行阐述，且衬底110例如为P型硅片，衬底110例如包括第一区域1和第二区域2。其中，第一区域1例如设置器件内部使用的Core MOS，一般工作电压较低。第二区域2例如设置与Core MOS晶体管相对应的边缘金氧半场效晶体管，即IO MOS晶体管，一般用于芯片与外部接口交互，工作电压较CoreMOS晶体管的工作电压高。在本实施例中，以第一区域1包括一个PMOS晶体管和NMOS晶体管以及第二区域2包括一个PMOS晶体管和NMOS晶体管为例进行阐述，且PMOS晶体管和NMOS晶体管交替分布，PMOS晶体管和NMOS晶体管之间通过浅沟槽隔离结构进行隔离。
请参阅图1所示，在本发明一实施例中，在衬底110上形成多个浅沟槽隔离结构，具体地，在衬底110上形成垫氧化层120，且垫氧化层120例如为致密的氧化硅等材料，垫氧化层120例如可以通过热氧化法、原位水汽生长法或化学气相沉积（Chemical VaporDeposition，CVD）等方法制备。在垫氧化层120上形成垫氮化层130，且垫氮化层130例如为氮化硅或氮化硅和氧化硅的混合物，垫氮化层130可通过化学气相淀积等方法形成。在形成浅沟槽隔离结构过程中，垫氧化层120可以改善衬底110与垫氧化层120之间的应力，同时可在进行离子注入形成阱区时，保护衬底110，防止衬底110被高能量离子损伤。在垫氮化层130上形成图案化光阻层140，图案化光阻层140上设置多个第一凹部141，第一凹部141用来定义浅沟槽隔离结构的位置，且第一凹部141暴露出垫氮化层130。
请参阅图1至图2所示，在本发明一实施例中，在形成图案化光阻层140后，以图案化光阻层140为掩膜，例如使用干法刻蚀向衬底110的方向进行刻蚀，形成浅沟槽，且刻蚀气体例如可以是氯气（Cl2）、三氟甲烷（CHF3）、二氟甲烷（CH2F2）、三氟化氮（NF3）、六氟化硫（SF6）或溴化氢（HBr）等中的一种或几种混合。在浅沟槽内例如通过热氧化法在浅沟槽内形成一内衬氧化层（图中未显示），以修复在形成浅沟槽的过程中的刻蚀损伤，减少半导体器件漏电情况。在浅沟槽内例如通过高密度等离子体化学气相淀积（High Density PlasmaCVD，HDP-CVD）或高深宽比化学气相淀积（High Aspect Ratio Process CVD，HARP-CVD）等方式沉积隔离介质，且隔离介质例如为氧化硅等绝缘物质。在隔离介质沉积完成后，例如通过化学机械抛光（Chemical Mechanical Polishing，CMP）工艺平坦化隔离介质和垫氮化层130，形成浅沟槽隔离结构150，且浅沟槽隔离结构150与两侧的垫氧化层120齐平。
请参阅图3所示，在本发明一实施例中，在浅沟槽隔离结构150制备完成后，对衬底110进行离子注入，以形成不同的阱区。首先，以高注入能量注入比衬底110浓度高的掺杂区，即在衬底110内形成第一阱区160。在形成NMOS晶体管的区域以高注入能量注入比第一阱区160浓度高的掺杂离子，以形成第二阱区170，且第二阱区170位于部分第一阱区160上。在本实施例中，第一阱区160和第二阱区170的类型不同，其中，第一阱区160例如设置为N型深阱，掺杂离子为磷（P）、砷（As）或铝（Al）等，第二阱区170例如设置为P型深阱，掺杂离子为硼（B）或镓（Ga）等。在第一阱区160和第二阱区170形成后，对在第一阱区160和第二阱区170进行快速热退火制程（Rapid Thermal Anneal，RTA），在本实施例中，退火温度例如为1000℃~1400℃，退火时间例如为1h~3h，且退火制程是在稳定气体氛围下进行，例如在氮气氛围下进行。通过退火制程，使得第一阱区160和第二阱区170的离子注入至合适深度，同时提高半导体器件的抗雪崩击穿能力。
请参阅图3至图4所示，在本发明一实施例中，在第一阱区160和第二阱区170形成之后，去除垫氧化层120。在本实施例中，例如采用湿法刻蚀去除垫氧化层120，且湿法刻蚀液例如选用氢氟酸，在常温下进行刻蚀。在其他实施例中，也可采用其他刻蚀方式，根据具体的制作要求进行选择。同时，在去除垫氧化层120时，延长刻蚀时间，去除部分浅沟槽隔离结构150中的隔离介质，形成开口11，且开口11的深度例如为10nm~30nm，即刻蚀后开口11的下表面低于两侧的衬底110表面，高度差例如为10nm~30nm。通过设置开口11，可避免在去除垫氧化层120时，在浅沟槽隔离结构150的边缘形成凹陷，从而减少漏电的发生，提高半导体器件的电学性能。同时，去除垫氧化层120和形成开口11在同一制程中形成，光罩数目不变，不会增加光阻和刻蚀的步骤，降低成本。
请参阅图5和图15所示，在本发明一实施例中，在开口11形成后，在开口11内以及衬底110上沉积高介电常数材料，形成介质层180，以作为半导体器件的栅介质层。在本实施例中，介质层180例如可通过利用原子层沉积法（Atomic Layer Deposition，ALD）、金属有机气相沉积法（Metal-Organic Chemical Vapor Deposition，MOCVD）、分子束外延法（Molecular BeamEpitaxy，MBE）、化学气相沉积法或物理气相沉积法（Physical VaporDeposition，PVD）等方法形成。且介质层180例如为氧化铪（HfO2）、氮氧化铪（HfON）、氧化锆（ZrO2）、氮氧化锆（ZrON）、氧氮硅酸锆（ZrSiON）、硅酸铪（HfSiO）、氧氮硅酸铪（HfSiON）、镧氧氮化铪（HfLaON）或氧化铪铝（HfAlO）等中的一种或几种混合。因介质层180选择高介电常数介质材料，与衬底110之间的界面品质较差，因此，在沉积介质层180之前，例如采用原位水汽生成（In-Situ Steam Generation，ISSG）在衬底110上以及开口11的侧壁上形成一层界面层111，且界面层111的厚度例如为0.5nm~1.5nm，以改善介质层180与衬底110之间的界面品质。在介质层180沉积完成，对介质层180进行平坦化工艺，因第二区域2的晶体管的工作电极较高，所以在第一区域1和第二区域2上，介质层180的保留厚度不同。在本实施例中，介质层180在第一区域1的阱区上的厚度例如2nm~5nm，介质层180在第二区域2的阱区上的厚度例如4nm~8nm，可提高第二区域2上晶体管的压耐。通过设置开口11及介质层180，增加了后续晶体管的有效宽度，从而提高器件的性能，并减少漏电流的现象。
请参阅图6所示，在本发明一实施例中，在介质层180形成后，在介质层180上形成伪栅极190。具体的，在介质层180上依次形成保护层191、多晶硅层192、遮蔽层193以及抗反射层194。在本实施例中，保护层191例如为氮化钛等，且例如采用原子层沉积方法（AtomicLayer Deposition，ALD）制备保护层191，通过设置保护层191，可以在后续制备过程中，防止介质层180受到污染或损伤，可提高后续制备的金属栅极的性能。多晶硅层192例如为N型掺杂的多晶硅层，可以在后续制程中，提高多晶硅层192的去除速度。遮蔽层193例如为氮化硅、氮化钛或氮碳化硅等中的一种或多种。抗反射层194例如为氮氧化硅等反射材料，以确保在形成伪栅极190的过程中，保证伪栅极190的结构完整性。在抗反射层194上形成图案的化光阻层（图中未显示），后对抗反射层194、遮蔽层193、多晶硅层192以及保护层191进行刻蚀，且介质层180作为刻蚀停止层，在介质层180上形成层叠的柱状结构，去除遮蔽层193和抗反射层194，在介质层180上形成伪栅极190，且伪栅极190位于第一阱区160和第二阱区170上。
请参阅图7所示，在本发明一实施例中，在伪栅极190形成后，在伪栅极190的两侧形成侧墙结构200，即侧墙结构200形成于伪栅极190的侧面，且侧墙结构200位于介质层180上，侧墙结构200的边缘与位于伪栅极190下方的介质层180的边缘重合。在本实施例中，侧墙结构200为叠层结构，其中，侧墙结构200例如包括第一绝缘层201、第一应力层202、第二绝缘层203和第二应力层204，绝缘层例如为氧化硅等，应力层例如为氮化硅等。即侧墙结构200为氧化硅层/氮化硅层的叠层，其中应力层可以在去除伪栅极190的过程中，确保侧墙结构的稳定，减少因侧墙结构内倾而导致的后续栅极沉积不均匀，提高栅极结构的均匀性，从而提高半导体结构的阈值电压的稳定性。在其他实施例中，侧墙结构200也可以为单层绝缘层或其他结构。通过将侧墙结构设置为多层结构，减少侧墙结构在后续制程中的损失。
请参阅图8至图9所示，在本发明一实施例中，在侧墙结构200形成后，在第二阱区170中形成轻掺杂区210，且轻掺杂区210位于侧墙结构200与浅沟槽隔离结构150之间，并与侧墙结构200与浅沟槽隔离结构150相邻，以改善形成的晶体管的短沟道效应。具体地，以较低注入能量注入掺杂离子，因此，形成的轻掺杂区210位于第二阱区170靠近介质层180的一侧。其中，注入的掺杂离子例如为磷、砷或铝等N型离子，轻掺杂区210可以作为NMOS晶体管的源极或漏极区。在轻掺杂区210后，去除浅沟槽隔离结构150、第一阱区160以及第二阱区170上的介质层180，保留伪栅极190及侧墙结构200覆盖区域的介质层180，保留开口11内的介质层180，且开口11内的介质层180与衬底110齐平。在本实施例中，介质层180可通过干法刻蚀、湿法刻蚀或干法刻蚀与湿法刻蚀相结合去除。通过在形成轻掺杂区210后去除介质层180，可防止在形成轻掺杂区210时，对第二阱区170的损伤，从而提高半导体器件的性能。
请参阅图10至图11所示，在本发明一实施例中，在去除介质层180后，在第一阱区160上形成凹槽12，且凹槽12位于侧墙结构200与浅沟槽隔离结构150之间，并与侧墙结构200与浅沟槽隔离结构150相邻。具体地，在衬底110上形成图案的化光阻层（图中未显示），通过干法刻蚀或湿法刻蚀第一阱区160上侧墙结构200两侧的衬底110，形成凹槽12。在本实施例中，凹槽12的侧壁呈开口多边形设置，可以扩大后续沉积应力区220与晶体管沟道区域的接触面积，提高沟道区域受到的应力作用，从而提高沟道区域内的迁移率。在凹槽12内沉积半导体材料以形成应力区220，且应力区220可以作为PMOS晶体管的源极区或漏极区。在本实施例中，应力区220例如为硅锗（SiGe），且SiGe为掺杂了P型杂质的SiGe。其中应力区220的形状和凹槽12形状一致，例如为多边形形状，且多边形的一边与浅沟槽隔离结构150相邻，应力区220向伪栅极190底部延伸，且延伸至侧墙结构200和伪栅极190连接处。通过设置应力区220延伸至侧墙结构200和伪栅极190连接处，可避免应力区220延伸至伪栅极190底部时，而导致的漏电流现象，同时，当应力区220未延伸至侧墙结构200和伪栅极190连接处时，应力区220之间的沟道区域宽度较大，载流子迁移率降低，影响半导体器件性能。因此，通过将应力区220延伸至侧墙结构200和伪栅极190连接处时，半导体器件的电性可以达到最好效能。在本实施例中，应力区220例如通过低温外延工艺沉积制备，采用低温外延工艺的外源气体包括锗源气体、硅源气体、氯化氢气体和氢气等，通过调整锗源气体和硅源气体的比例，调节应力区220中锗的比例，且应力区220中锗的比例例如为20%~40%。通过控制锗的含量，可以减小应力区220与凹槽12内壁的晶格常数差异，减少应力区220内的缺陷。在应力区220形成后，对轻掺杂区210和应力区220进行激活，例如将衬底110进行快速热退火。通过快速热退火，能够修复制作过程中产生的晶格缺陷、激活掺杂离子和最小化掺杂离子扩散三者之间取得优化，进而激活应力层和轻掺杂区，且快速热退火还能减小瞬时增强扩散。
请参阅图12所示，在本发明一实施例中，在伪栅极190、轻掺杂区210和应力区220形成自对准硅化物阻挡层（Self-Aligned Block，SAB）230。具体地，在介质层180、伪栅极190、轻掺杂区210和应力区220上形成金属层（图中未显示），且金属层例如为钛层（Ti）、钴层（Co）或镍层（Ni）等。然后对衬底110进行第一次退火，第一次退火的温度例如为300℃~350℃，使得金属原子与伪栅极190、轻掺杂区210或应力区220中的硅原子反应，形成中间硅化物层，然后通过化学溶液选择去除未反应的金属层，并对中间硅化物层进行第二次退火，第二次退火的温度比第一次退火的温度高，第二次退火的温度例如为400℃~500℃。中间硅化物层经过退火之后转化为硅化物层，也就是自对准硅化物阻挡层230。自对准硅化物阻挡层230具有良好的热稳定性，可以降低器件的电阻，其保证与后期制备的金属电极接触良好。
请参阅图6和图13所示，在本发明一实施例中，在形成自对准硅化物阻挡层230后，去除伪栅极190顶部的自对准硅化物阻挡层230和伪栅极190中的多晶硅层192，保留伪栅极190中的保护层191，以形成沟槽13，即沟槽13暴露出保护层191。在去除多晶硅层192时，可采用干法刻蚀、湿法刻蚀或干法刻蚀和湿法刻蚀相结合。当采用干法刻蚀时，可以选择氯气、溴气、氦气、溴化氢或者其中至少一种气体和氧气的混合气体，干法刻蚀各向异性、选择性好以及刻蚀效率高。当采用湿法刻蚀时，可选用四甲基氢氧化接溶液或氢氧化钾溶液去除多晶硅层192，采用湿法刻蚀的优点是操作简便、对设备要求低、易于大批量生产。在刻蚀过程中，侧墙结构200保留，用来定位金属栅极的位置并作为后期制备金属栅极的侧墙结构。
请参阅图14至图16所示，在本发明一实施例中，在形成沟槽13后，在沟槽13内沉积金属，形成金属栅极260，且金属栅极260例如为单层金属、多层金属或金属化合物堆叠等结构。其中，金属栅极260包括第一金属栅极240和第二金属栅极250，第一金属栅极240为PMOS晶体管的金属栅极，第二金属栅极250为NMOS晶体管的金属栅极。
请参阅图14至图15所示，在本发明一实施例中，图15为第一金属栅极240在衬底110上的结构示意图。第一金属栅极240包括介质层180、保护层191、第一阻挡层241、第一功函数金属层242和第一金属导电层243。其中，介质层180为高介电常数介质层，保护层191在形成伪栅极的过程中形成，减少对介质层180的损伤。第一阻挡层241形成在保护层191上，第一阻挡层241的材料可为氮化钛（TiN）或氮化钽（TaN）等金属化合物或其叠层。在本实施例中，第一阻挡层241包括氮化钛层或氮化钽层，其中，氮化钽层设置在保护层191上，氮化钛层设置在氮化钽层上。且第一阻挡层241可利用原子层沉积、物理气相沉积或化学气相沉积等方法形成。第一功函数金属层242设置在第一阻挡层241上，且第一功函数金属层242例如为P型功函数金属层，其材料可以为氮化钽、氮化钛、铝化钛（TiAl）、氮化钛铝（TiAIN）或氮化钨（WN）等中的一种或叠层。在本实施例中，第一功函数金属层242例如为铝化钛层和氮化钛的叠层，其中铝化钛层设置在第一阻挡层241上，氮化钛设置在铝化钛层上，且第一功函数金属层242例如通过等离子体增强化学的气相沉积法(Plasma Enhanced ChemicalVapor Deposition，PECVD)、原子层沉积或物理气相沉积等方法形成。在第一功函数金属层242层上形成第一金属导电层243，且第一金属导电层243例如为金属钨、铜或银等导电性较好的金属，提高晶体管的电性性能，第一金属导电层243例如通过磁控溅射或蒸镀等方式形成。在第一金属导电层243形成后，进行平坦化制程，提高第一金属导电层243的平整度。
请参阅图14和图16所示，在本发明一实施例中，图16为第二金属栅极250在衬底110上的层结构示意图。第二金属栅极250包括介质层180、保护层191、第二阻挡层251、第二功函数金属层252和第二金属导电层253。其中，介质层180为高介电常数介质层，保护层191在形成伪栅极的过程中形成，减少对介质层180的损伤。第二阻挡层251形成在保护层191上，第二阻挡层251的材料可为氮化钛或氮化钽等金属化合物或其叠层。在本实施例中，第二阻挡层251例如为氮化钽层，且第二阻挡层251可利用原子层沉积、物理气相沉积或化学气相沉积等方法形成。第二功函数金属层252设置在第二阻挡层251上，且第二功函数金属层252例如为N型功函数金属层，其材料可以为氮化钽、氮化钛、铝化钛、氮化钛铝或氮化钨等中的一种或叠层。在本实施例中，第二功函数金属层252例如为铝化钛层和氮化钛的叠层，其中铝化钛层设置在第二阻挡层251上，氮化钛设置在铝化钛层上，且第二功函数金属层252例如通过等离子体增强化学的气相沉积法、原子层沉积或物理气相沉积等方法形成。在第二功函数金属层252层上形成第二金属导电层253，且第二金属导电层253例如为金属钨、铜或银等导电性较好的金属，提高晶体管的电性性能，第二金属导电层253例如通过磁控溅射或蒸镀等方式形成。在第二金属导电层253形成后，进行平坦化制程，提高第二金属导电层253的平整度。在本实施例中，NMOS晶体管和PMOS晶体管的金属栅极的金属导电层可以连接起来，也可以相互断开，可根据实际生产进行调整，且当金属导电层互相连接时，金属导电层在浅沟槽隔离结构150上的高度小于在衬底110上的高度，金属导电层在浅沟槽隔离结构150上的高度比在衬底110上的高度低，且高度差例如为5nm及以上。
请参阅图17所示，在本发明一实施例中，在金属栅极260形成后，在衬底110靠近金属栅极260的一侧形成钝化保护层270，即钝化保护层270覆盖金属栅极260、介质层180、自对准硅化物阻挡层230以及侧墙结构200。其中，钝化保护层270在金属栅极260和自对准硅化物阻挡层230的位置上设置有第二凹部14，暴露出金属栅极260和自对准硅化物阻挡层230，以定位金属电极的位置以及连接金属电极。在本实施例中，钝化保护层270例如为氧化硅或氧化钛等绝缘材料，可以保护器件并提高器件的耐压性。通过设置钝化保护层270可以提高器件的使用寿命，提高器件的性能。
请参阅图17图18所示，在本发明一实施例中，在所述衬底110上形成绝缘层280，绝缘层覆盖全部衬底110的表面，且绝缘层280例如设置为氧化硅层。在形成绝缘层280后，进行平坦化工艺，且在绝缘层280上设置多个通道，通道位于第二凹部14上，且通道暴露出金属栅极260和自对准硅化物阻挡层230，在通道内设置金属连线，例如钨、铜或银等金属，以形成电极。电极包括源极21、栅极22和漏极23，其中，源极21位于金属栅极260的一侧，且与自对准硅化物阻挡层230连接。栅极22设置在金属栅极260上，且与金属栅极260的金属导电层连接。漏极23设置在金属栅极260的另一侧，且与自对准硅化物阻挡层230连接。
综上所述，本发明提供一种半导体器件及其制作方法，在形成伪栅极之前，形成介质层，提高半导体器件的电学性能，且可以增加半导体器件的有效宽度，增加半导体器件的效能。提高同一衬底上不同功能的半导体器件的性能，获得高质量半导体器件。
以上公开的本发明实施例只是用于帮助阐述本发明。实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施方式。显然，根据本说明书的内容，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地理解和利用本发明。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (11)

1.一种半导体器件，其特征在于，包括：
衬底，且所述衬底包括第一区域和第二区域；
浅沟槽隔离结构，设置在所述第一区域和所述第二区域上，且所述浅沟槽隔离结构低于所述衬底表面，形成开口；
介质层，设置在所述开口内和所述衬底上，且所述介质层在所述第二区域的高度大于在所述第一区域的高度；
栅极，设置在所述介质层上；
源极，设置在所述衬底上，且所述源极位于所述栅极一侧；以及
漏极，设置在所述衬底上，且所述漏极位于所述栅极的另一侧。
2.根据权利要求1所述的半导体器件，其特征在于，所述浅沟槽隔离结构低于所述衬底表面10nm~30nm。
3.根据权利要求1所述的半导体器件，其特征在于，所述半导体器件包括侧墙结构，且所述侧墙结构位于所述栅极两侧，所述侧墙结构位于所述介质层上。
4.根据权利要求3所述的半导体器件，其特征在于，所述侧墙结构为单层绝缘层或为绝缘层与应力层的堆叠结构。
5.根据权利要求3所述的半导体器件，其特征在于，所述半导体器件包括钝化保护层，且所述钝化保护层设置在所述栅极、所述侧墙结构以及所述介质层上。
6.根据权利要求3所述的半导体器件，其特征在于，所述栅极包括第一金属栅极，且所述第一金属栅极两侧的所述衬底中设置有应力区。
7.根据权利要求6所述的半导体器件，其特征在于，所述应力区向所述第一金属栅极底部延伸，且延伸至所述侧墙结构和所述第一金属栅极连接处。
8.根据权利要求1所述的半导体器件，其特征在于，所述栅极包括第二金属栅极，且所述第二金属栅极两侧的衬底中设置有轻掺杂区。
9.根据权利要求1所述的半导体器件，其特征在于，所述介质层在所述第一区域的厚度为2nm~5nm，所述介质层在所述第二区域的厚度为4nm~8nm。
10.根据权利要求1所述的半导体器件，其特征在于，所述栅极为单层金属、多层金属或金属与金属化合物堆叠结构。
11.一种半导体器件的制作方法，其特征在于，包括：
提供一衬底，所述衬底包括第一区域和第二区域；
在所述第一区域和所述第二区域上形成多个浅沟槽隔离结构；
在去除所述衬底上的垫氧化层时，延长刻蚀时间，以移除部分所述浅沟槽隔离结构；
在所述浅沟槽隔离结构上形成低于所述衬底表面的开口；
在所述开口内及所述衬底上形成介质层，且所述介质层在所述第二区域的高度大于在所述第一区域的高度；
在所述介质层上形成栅极；
在所述衬底上形成源极，且所述源极位于所述栅极一侧；以及
在所述衬底上形成漏极，且所述漏极位于所述栅极的另一侧。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116053274A (zh) * 2023-01-28 2023-05-02 合肥晶合集成电路股份有限公司 一种半导体集成器件及其制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117912979A (zh) * 2024-03-20 2024-04-19 合肥晶合集成电路股份有限公司 关键尺寸的量测方法及量测结构

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093593A (en) * 1999-06-28 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of forming a gate which provides a reduced corner recess in adjacent shallow trench isolation
CN1797736A (zh) * 2004-12-03 2006-07-05 台湾积体电路制造股份有限公司 调整晶体管的浅沟渠隔离结构应力的方法
US20090014810A1 (en) * 2007-06-26 2009-01-15 Eun-Jong Shin Method for fabricating shallow trench isolation and method for fabricating transistor
CN101572250A (zh) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 半导体器件、p型MOS晶体管及其制作方法
US20100171168A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd Non-volatile memory device and method of manufacturing the same
US20110081765A1 (en) * 2009-10-01 2011-04-07 International Business Machines Corporation Method to improve wet etch budget in feol integration
US20120292735A1 (en) * 2011-05-20 2012-11-22 GLOBALFOUNDRIES Singapore Pte.Ltd. Corner transistor suppression
CN104078409A (zh) * 2014-07-25 2014-10-01 上海华力微电子有限公司 浅沟槽隔离的工艺方法
CN104425347A (zh) * 2013-09-09 2015-03-18 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离的制备方法
CN106033744A (zh) * 2015-03-09 2016-10-19 无锡华润上华半导体有限公司 半导体器件的制备方法
CN106373924A (zh) * 2015-07-23 2017-02-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093593A (en) * 1999-06-28 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of forming a gate which provides a reduced corner recess in adjacent shallow trench isolation
CN1797736A (zh) * 2004-12-03 2006-07-05 台湾积体电路制造股份有限公司 调整晶体管的浅沟渠隔离结构应力的方法
US20090014810A1 (en) * 2007-06-26 2009-01-15 Eun-Jong Shin Method for fabricating shallow trench isolation and method for fabricating transistor
CN101572250A (zh) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 半导体器件、p型MOS晶体管及其制作方法
US20100171168A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd Non-volatile memory device and method of manufacturing the same
US20110081765A1 (en) * 2009-10-01 2011-04-07 International Business Machines Corporation Method to improve wet etch budget in feol integration
US20120292735A1 (en) * 2011-05-20 2012-11-22 GLOBALFOUNDRIES Singapore Pte.Ltd. Corner transistor suppression
CN104425347A (zh) * 2013-09-09 2015-03-18 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离的制备方法
CN104078409A (zh) * 2014-07-25 2014-10-01 上海华力微电子有限公司 浅沟槽隔离的工艺方法
CN106033744A (zh) * 2015-03-09 2016-10-19 无锡华润上华半导体有限公司 半导体器件的制备方法
CN106373924A (zh) * 2015-07-23 2017-02-01 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116053274A (zh) * 2023-01-28 2023-05-02 合肥晶合集成电路股份有限公司 一种半导体集成器件及其制作方法

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