CN110838487A - 半导体器件及方法 - Google Patents

半导体器件及方法 Download PDF

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CN110838487A
CN110838487A CN201910689499.4A CN201910689499A CN110838487A CN 110838487 A CN110838487 A CN 110838487A CN 201910689499 A CN201910689499 A CN 201910689499A CN 110838487 A CN110838487 A CN 110838487A
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CN110838487B (zh
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廖书翎
柯忠祁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及半导体器件及方法。一个实施例是一种器件，包括：第一鳍，从衬底延伸；第一栅极堆叠，位于第一鳍的侧壁上方并且沿着第一鳍的侧壁；第一栅极间隔件，沿着第一栅极堆叠的侧壁设置；第一外延源极/漏极区域，在第一鳍中并与第一栅极间隔件相邻；以及保护层，在第一外延源极/漏极区域和第一栅极间隔件之间，并且在第一栅极间隔件和第一栅极堆叠之间。

Description

半导体器件及方法
优先权声明和交叉引用
本申请要求于2018年8月16日提交的美国临时申请No.62/764,865的权益，该临时申请的整体通过引用结合于此。
技术领域
本公开总体涉及半导体器件及方法。
背景技术
半导体器件被用于各种电子应用中，例如，个人计算机、蜂窝电话、数码相机和其他电子设备。半导体器件通常通过以下方式来制造：在半导体衬底上方按顺序沉积绝缘或电介质层、导电层和半导体材料层，并且使用光刻来图案化各种材料层以在其上形成电路组件和元件。
半导体工业通过不断减小最小特征尺寸来持续改善各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多组件被集成到给定区域中。然而，随着最小特征尺寸的减小，出现了应当被解决的其他问题。
发明内容
本公开的一个实施例提供了一种半导体器件，包括：第一鳍，从衬底延伸；第一栅极堆叠，位于所述第一鳍的侧壁上方并且沿着所述第一鳍的侧壁被设置；第一栅极间隔件，沿着所述第一栅极堆叠的侧壁被设置；第一外延源极/漏极区域，位于所述第一鳍中并且与所述第一栅极间隔件相邻；以及保护层，位于所述第一外延源极/漏极区域和所述第一栅极间隔件之间，并且所述保护层位于所述第一栅极间隔件和所述第一栅极堆叠之间。
本公开的另一实施例提供了一种用于形成半导体器件的方法，包括：在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；沿着所述第一栅极的侧壁形成第一低k栅极间隔件；在所述第一鳍中与所述第一低k栅极间隔件相邻地蚀刻第一凹陷；在所述第一凹陷中外延生长第一源极/漏极区域；去除所述第一低k栅极间隔件，所述去除在所述第一栅极和所述第一源极/漏极区域之间形成第二凹陷；在所述第一栅极上方、在所述第一源极/漏极区域上方、并且在所述第二凹陷中形成保护层；在所述保护层上方形成低k层；以及蚀刻所述低k层以在所述第二凹陷中形成第二低k栅极间隔件，所述第二低k栅极间隔件沿着沿所述第一栅极的侧壁延伸的所述保护层延伸。
本公开的又一实施例提供了一种用于形成半导体器件的方法，包括：在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；沿着所述第一栅极的侧壁形成第一低k栅极间隔件；在所述第一鳍上与所述第一低k栅极间隔件相邻地外延生长第一源极/漏极区域；蚀刻所述第一低k栅极间隔件；在所述第一栅极和所述第一源极/漏极区域上方形成电介质层；对所述电介质层上执行氧处理；以及蚀刻经处理的电介质层以沿着所述第一栅极的侧壁形成第二栅极间隔件。
附图说明
在结合附图阅读下面的具体实施方式时，可以从下面的具体实施方式中最佳地理解本公开的各个方面。应当注意，根据行业的标准做法，各种特征不是按比例绘制的。事实上，为了讨论的清楚起见，各种特征的尺寸可能被任意增大或减小。
图1示出了根据一些实施例的三维视图中的FinFET的示例。
图2、3、4、5、6、7、8A、8B、9A、9B、10A、10B、10C、10D、11A、11B，12A、12B、13A、13B、14A、14B、15A、15B、16A、16B、17A、17B、18A、18B、18C、19A、19B、20A和20B是根据一些实施例的FinFET的制造的中间阶段的横截面图。
图21A、21B、22A、22B、23A、23B、24A、24B、25A和25B是根据一些实施例的FinFET的制造的中间阶段的横截面图。
图26A、26B、27A、27B、28A、28B、29A、29B、30A和30B是根据一些实施例的FinFET的制造的中间阶段的横截面图。
图31A、31B、32A、32B、33A、33B、34A、34B、35A和35B是根据一些实施例的FinFET的制造的中间阶段的横截面图。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然，这些仅仅是示例而不意图是限制性的。例如，在下面的说明中，在第二特征上方或之上形成第一特征可以包括以直接接触的方式形成第一特征和第二特征的实施例，并且还可以包括可以在第一特征和第二特征之间形成附加特征以使得第一特征和第二特征可以不直接接触的实施例。此外，本公开在各个示例中可能重复参考标号和/或字母。这种重复是为了简单性和清楚性的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，本文中可能使用了空间相关术语(例如，“下方”、“之下”、“低于”、“以上”、“上部”等)，以易于描述图中所示的一个要素或特征相对于另一个(一些)要素或特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转了90度或处于其他朝向)，并且本文中所用的空间相关描述符同样可能被相应地解释。
根据各种实施例提供了鳍式场效应晶体管(FinFET)及其形成方法。示出了形成FinFET的中间阶段。在使用后栅极(gate-last)(有时称为替换栅极工艺)工艺形成的FinFET的背景下讨论了本文讨论的一些实施例。在其他实施例中，可以使用先栅极(gate-first)工艺。讨论了实施例的一些变型。此外，一些实施例考虑了在平面器件(例如，平面FET)中使用的方面。本领域普通技术人员将容易地理解在其他实施例的范围内构思的可以做出的其他修改。尽管以特定顺序讨论了方法实施例，但可以以任何逻辑顺序执行各种其他方法实施例，并且可以包括比本文描述的更少或更多的步骤。
在具体地解决所示实施例之前，将一般地解决本公开实施例的某些有利特征和方面。一般而言，本公开是半导体器件及其形成方法，以通过减小器件的栅极和源极/漏极区域之间的电容来提高FinFET器件的性能，同时不会损坏源极/漏极区域。在所公开的实施例中，源极/漏极区域是外延结构，并且形成在栅极电极的侧壁上的间隔件被形成为低k间隔件，以减小栅极电极和源极/漏极区域之间的电容。在一些实施例中，形成低k间隔件的方法利用保护层来保护源极/漏极区域并防止其在低k间隔件的形成期间被损坏。在一些实施例中，栅极间隔件被形成为空气间隔件(例如，栅极电极和源极/漏极区域之间的空隙或间隙)，以降低栅极电极和源极/漏极区域之间的空间的k值。所公开的工艺和结构可以提高FinFET器件的性能、可靠性和产量。
一些实施例考虑了在制造工艺期间制造的诸如n型FinFET之类的n型器件和诸如p型FinFET之类的p型器件。因此，一些实施例考虑形成补充器件。下面的附图可以示出一个器件，但本领域普通技术人员将容易地理解，可以在工艺期间形成多个器件，一些器件具有不同的器件类型。下面讨论形成补充器件的一些方面，但这些方面可能未必在附图中示出。
图1示出了根据一些实施例的三维视图中的FinFET的示例。FinFET包括位于衬底50(例如，半导体衬底)上的鳍52。隔离区域56设置在衬底50中，并且鳍52从相邻的隔离区域56之间突出并突出在其上方。尽管隔离区域56被描述/示出为与衬底50分离，但如本文所使用的，术语“衬底”可以用于仅指代半导体衬底或包括隔离区域的半导体衬底。此外，尽管鳍52被示出为单个连续材料作为衬底50，但鳍52和/或衬底50可以包括单个材料或多个材料。在该上下中，鳍52指代在相邻的隔离区域56之间延伸的部分。
栅极电介质层98沿着侧壁并且在鳍52的顶表面上方，并且栅极电极100在栅极电介质层98上方。源极/漏极区域82被设置在鳍52的相对于栅极电介质层98和栅极电极100的相对侧中。图1进一步示出了在后面的附图中使用的参考横截面。横截面A-A沿着栅极电极100的纵轴并且在例如垂直于FinFET的源极/漏极区域82之间的电流方向的方向上。横截面B-B垂直于横截面A-A并沿着鳍52的纵轴，并且在例如FinFET的源极/漏极区域82之间的电流的方向上。横截面C-C平行于横截面A-A并延伸通过FinFET的源极/漏极区域。为清楚起见，后续附图参考这些参考横截面。
在使用后栅极工艺形成的FinFET的上下文中讨论了本文所讨论的一些实施例。在其他实施例中，可以使用先栅极工艺。此外，一些实施例考虑了在平面器件(例如，平面FET)中使用的方面。
图2至图20B是根据一些实施例的FinFET的制造的中间阶段的横截面图。图2至图7示出了图1中示出的参考横截面A-A，除了多个鳍/栅极/FinFET之外。以A结尾的图(例如，图8A、9A、10A等)沿图1中所示的参考横截面A-A示出，并且以B结尾的图(例如，图8B、9B、10B等)沿图1中所示的类似横截面B-B示出，除了多个鳍/栅极/FinFET之外。图10C和10D沿图1中所示的参考横截面C-C示出，除了多个鳍/栅极/FinFET之外。
在图2中，提供了衬底50。衬底50可以是半导体衬底，例如，体半导体、绝缘体上半导体(SOI)衬底等，其可以是掺杂的(例如，用p型或n型掺杂剂)或未掺杂的。衬底50可以是晶片，例如，硅晶片。通常，SOI衬底是在绝缘体层上形成的半导体材料层。绝缘体层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘体层设置在衬底上，衬底通常是硅或玻璃衬底。也可以使用其他衬底，例如，多层或梯度衬底。在一些实施例中，衬底50的半导体材料可包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或其组合。
衬底50具有区域50N和区域50P。区域50N可以用于形成n型器件，例如，NMOS晶体管，如n型FinFET。区域50P可以用于形成p型器件，例如，PMOS晶体管，如p型FinFET。区域50N可以与区域50P物理地分离(如分隔器51所示)，并且可以在区域50N和区域50P之间设置任何数量的器件特征(例如，其他有源器件、掺杂区域、隔离结构等)。
在图3中，鳍52被形成在衬底50中。鳍52是半导体条带。在一些实施例中，可以通过蚀刻衬底50中的沟槽来在衬底50中形成鳍52。蚀刻可以是任何可接受的蚀刻工艺，例如，反应离子蚀刻(RIE)、中性束蚀刻(NBE)等、或其组合。蚀刻可以是各向异性的。
可以通过任何合适的方法对鳍进行图案化。例如，可以使用一个或多个光刻工艺来图案化鳍，包括双图案化或多图案化工艺。通常，双图案化或多图案化工艺组合光刻和自对准工艺，允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺进行图案化。使用自对准工艺在经图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件来图案化鳍。
在图4中，在衬底50上方和相邻的鳍52之间形成绝缘材料54。绝缘材料54可以是氧化物，例如，氧化硅、氮化物等、或它们的组合，并且可以通过高密度等离子体化学气相沉积(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的基于CVD的材料沉积和后固化以使其转换成另一材料，例如氧化物)等、或其组合来形成。可以使用通过任何可接受的工艺形成的其他绝缘材料。在所示实施例中，绝缘材料54是通过FCVD工艺形成的氧化硅。一旦形成绝缘材料，则可以执行退火工艺。在实施例中，绝缘材料54被形成为使得多余的绝缘材料54覆盖鳍52。尽管绝缘材料54被示出为单层，但一些实施例可以使用多个层。例如，在一些实施例中，可以首先沿衬底50和鳍52的表面形成衬垫(未示出)。此后，可以在衬垫上方形成例如上面讨论的填充材料。
在图5中，将去除工艺应用于绝缘材料54以去除鳍52上方的多余的绝缘材料54。在一些实施例中，可以使用平坦化工艺，例如，化学机械抛光(CMP)、回蚀刻工艺、它们的组合等。平坦化工艺暴露出鳍52，使得在平坦化工艺完成之后鳍52和绝缘材料54的顶表面是水平的。
在图6中，绝缘材料54被凹陷以形成浅沟槽隔离(STI)区域56。绝缘材料54被凹陷以使得区域50N和区域50P中的鳍52的上部从相邻的STI区域56之间突出。此外，STI区域56的顶表面可以具有如图所示的平坦表面、凸表面、凹表面(例如，凹陷)、或其组合。通过适当的蚀刻，STI区域56的顶表面可以形成为平坦的、凸出的和/或凹入的。STI区域56可以使用可接受的蚀刻工艺进行凹陷，例如，对绝缘材料54的材料具有选择性的蚀刻工艺(例如，以比鳍52的材料更快的速率蚀刻绝缘材料54的材料)。例如，可以使用利用例如使用稀释氢氟(dHF)酸的适当蚀刻工艺可以去除的化学氧化物。
关于图2至图6描述的工艺仅是如何形成鳍52的一个示例。在一些实施例中，可以通过外延生长工艺形成鳍。例如，可以在衬底50的顶表面上方形成电介质层，并且可以蚀刻沟槽通过电介质层以暴露下面的衬底50。可以在沟槽中外延生长同质外延结构，并且电介质层可以被凹陷以使得同质外延结构从电介质层突出以形成鳍。此外，在一些实施例中，异质外延结构可用于鳍52。例如，图5中的鳍52可以被凹陷，并且不同于鳍52的材料可以在凹陷的鳍52上方外延生长。在这样的实施例中，鳍52包括凹陷材料以及设置在凹陷材料上方的外延生长材料。在更进一步的实施例中，可以在衬底50的顶表面上方形成电介质层，并且可以蚀刻沟槽通过电介质层。然后可以使用与衬底50不同的材料在沟槽中外延生长异质外延结构，并且电介质层可以被凹陷以使得异质外延结构从电介质层突出以形成鳍52。在外延生长同质外延结构或异质外延结构一些实施例中，外延生长材料可以在生长期间被原位掺杂，这可以避免先前和随后的注入，尽管可以一起使用原位掺杂和注入掺杂。
更进一步地，在区域50N(例如，NMOS区域)中外延生长与区域50P(例如，PMOS区域)中的材料不同的中材料可能是有利的。在各种实施例中，鳍52的上部可以由硅锗(SixGe1-x，其中x可以在0到1的范围内)、碳化硅、纯的或基本上纯的锗、III-V化合物半导体、II-VI化合物半导体等形成。例如，用于形成III-V化合物半导体的可用材料包括但不限于InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP等。
此外，在图6中，可以在鳍52和/或衬底50中形成适当的阱(未示出)。在一些实施例中，可以在区域50N中形成P阱，并且可以在区域50P中形成N阱。在一些实施例中，在区域50N和区域50P二者中形成P阱或N阱。
在具有不同阱类型的实施例中，可以使用光致抗蚀剂或其他掩模(未示出)来实现区域50N和区域50P的不同注入步骤。例如，可以在区域50N中的鳍52和STI区域56上方形成光致抗蚀剂。图案化光致抗蚀剂以暴露衬底50的区域50P，例如，PMOS区域。可以通过使用旋涂技术来形成光致抗蚀剂，并且可以使用可接受的光刻技术对光致抗蚀剂进行图案化。一旦光致抗蚀剂被图案化，则在区域50P中执行n型杂质注入，并且光致抗蚀剂可以用作掩模以基本上防止n型杂质被注入到区域50N中，例如，NMOS区域。n型杂质可以是以等于或小于1018cm-3(例如，在约1017cm-3和约1018cm-3之间)的浓度注入该区域中的磷、砷、锑等。在注入之后，例如通过可接受的灰化工艺去除光致抗蚀剂。
在注入区域50P之后，在区域50P中的鳍52和STI区域56上方形成光致抗蚀剂。图案化光致抗蚀剂以暴露衬底50的区域50N，例如，NMOS区域。可以通过使用旋涂技术来形成光致抗蚀剂，并且可以使用可接受的光刻技术对光致抗蚀剂进行图案化。一旦光致抗蚀剂被图案化，则在区域50N中执行p型杂质注入，并且光致抗蚀剂可以用作掩模以基本上防止p型杂质被注入到区域50P中，例如，PMOS区域。p型杂质可以是以等于或小于1018cm-3(例如，在约1017cm-3和约1018cm-3之间)的浓度注入该区域中的硼、BF2、铟等。在注入之后，例如通过可接受的灰化工艺去除光致抗蚀剂。
在区域50N和区域50P的注入之后，可以执行退火以激活被注入的p型和/或n型杂质。在一些实施例中，外延鳍的生长材料可以在生长期间被原位掺杂，这可以避免注入，尽管可以一起使用原位掺杂和注入掺杂。
在图7中，在鳍52上形成虚设电介质层60。虚设电介质层60可以是例如氧化硅、氮化硅、它们的组合等，并且可以根据可接受的技术来沉积或热生长。在虚设电介质层60上方形成虚设栅极层62，并且在虚设栅极层62上方形成掩模层64。虚设栅极层62可以沉积在虚设电介质层60上并然后被平坦化，例如通过CMP。掩模层64可以沉积在虚设栅极层62上方。虚设栅极层62可以是导电材料，并且可以选自包括非晶硅、多晶硅(多晶硅)、多晶硅锗(多晶SiGe)、金属氮化物、金属硅化物、金属氧化物和金属的组。虚设栅极层62可以通过物理气相沉积(PVD)、CVD、溅射沉积、或本领域已知并用于沉积导电材料的其他技术来沉积。虚设栅极层62可以由从隔离区域的蚀刻具有高蚀刻选择性的其他材料制成。掩模层64可以包括例如SiN、SiON等。在该示例中，跨区域50N和区域50P形成单个虚设栅极层62和单个掩模层64。应注意，仅为了说明的目的，虚设电介质层60被示出仅覆盖鳍52。在一些实施例中，虚设电介质层60可以被沉积为使得虚设电介质层60覆盖STI区域56，在虚设栅极层62和STI区域56之间延伸。
图8A至20B示出了实施例器件的制造中的各种附加步骤。图8A至20B示出了区域50N和区域50P中的任一个的特征。例如，图8A至20B中所示的结构可适用于区域50N和区域50P二者。区域50N和区域50P的结构中的差异(如果有的话)在结合每个附图的文本中进行描述。
在图8A和8B中，可以使用可接受的光刻和蚀刻技术将掩模层64(参见图7)图案化以形成掩模74。然后可以将掩模74的图案转移到虚设栅极层62。在一些实施例(未示出)中，掩模74的图案还也可以通过可接受的蚀刻技术转移到虚设电介质层60以形成虚设栅极72。虚设栅极72覆盖鳍52的相应沟道区域58。掩模74的图案可以用于将每个虚设栅极72与相邻的虚设栅极物理地分开。虚设栅极72还可以具有基本上垂直于相应的外延鳍52的长度方向的长度方向。
此外，在图8A和8B中，可以在虚设栅极72、掩模74、虚设电介质层60、和/或鳍52的暴露表面上形成栅极密封间隔件层80。栅极密封间隔件层80可以通过共形地沉积绝缘材料来形成。栅极密封间隔件离层80的绝缘材料可以是SiC、SiCN等、或它们的组合。可以通过原子层沉积(ALD)、CVD等、或其组合来沉积栅极密封间隔件层80。在ALD示例中，可以通过将硅前体(例如，二氯硅烷(DCS)(SiH4Cl2))、碳前体(例如，丙烯(C3H6))、以及氮前体(例如，氨(NH3))引入虚设栅极72、掩模74、虚设电介质层60、和/或鳍52来开始该工艺。在实施例中，以从约800sccm至约1200sccm(例如，约1000sccm)的流速引入硅前体，以从约800sccm至约1200sccm(例如，约1000sccm)的流速引入碳前体，并以从约3500sccm至约5500sccm(例如，约3500sccm)的流速引入氮前体。此外，可以以从约600℃至约700℃(例如，约620℃)的温度，以及约66帕斯卡和约931帕斯卡(例如，约530帕斯卡)之间的压力执行沉积。栅极密封间隔件层80的沉积工艺可以具有从4小时至8小时的持续时间，例如，约6小时。栅极密封间隔件层80可以被形成为具有从约40％至约60％的范围内的硅原子浓度，例如，约50％；从约5％至约15％的范围内的碳原子浓度，例如，约10％；以及从约30％至约45％的范围内的氮原子浓度，例如，约37％。
在形成栅极密封间隔件层80之前或之后，可以执行对轻微掺杂源极/漏极(LDD)区域(未明确示出)的注入。在具有不同器件类型的实施例中，类似于上面在图6中讨论的注入，可以在区域50N上方形成掩模，例如，光致抗蚀剂，而暴露区域50P，并且可以将适当类型(例如，p型)杂质注入区域50P中暴露的鳍52中。然后可以去除掩模。随后，可以在区域50P上方形成掩模，例如，光致抗蚀剂，而暴露区域50N，并且可以将适当类型的杂质(例如，n型)注入到区域50N中暴露的鳍52中。然后可以去除掩模。n型杂质可以是前面讨论的任何n型杂质，并且p型杂质可以是前面讨论的任何p型杂质。轻微掺杂源极/漏极区域可具有从约1015cm-3至约1016cm-3的杂质浓度。可以使用退火来激活所注入的杂质。
在图9A和9B中，沿着虚设栅极72和掩模74的侧壁在栅极密封间隔件层80上形成栅极间隔件86。可以通过共形地沉积绝缘材料并随后各向异性蚀刻栅极间隔件86和栅极密封间隔件层80的绝缘材料来形成栅极间隔件86。栅极间隔件86的绝缘材料可以是低k层，例如，碳氮化硅(SiOCN)等。栅极间隔件86的绝缘材料可以通过ALD、CVD等或其组合来沉积。在ALD示例中，该工艺可以通过将诸如六氯乙硅烷(HCD)(Si2Cl6)之类的硅前体、诸如丙烯(C3H6)之类的碳前体、诸如氨(NH3)之类的氮前体、以及诸如O2之类的氧前体引入栅极密封间隔件层80来开始。栅极间隔件86的绝缘材料可以被形成为具有从约20％至约40％的范围内的硅原子浓度，例如，约30％；从约40％至约70％的范围内的氧原子浓度，例如，约55％；从约0％至约5％的范围内的碳原子浓度，例如，约2.5％；以及从约0％至约15％的范围内的氮原子浓度，例如，约7.5％。在一些实施例中，栅极间隔件86的绝缘材料具有约4的k值。在形成栅极间隔件86的绝缘材料之后，执行诸如各向异性蚀刻工艺之类的蚀刻工艺以形成栅极密封间隔件80和栅极间隔件86。栅极间隔件86可以由低k材料形成，并且可以称为低k栅极间隔件86。
在图10A和10B中，在鳍52中形成外延源极/漏极区域82以在各个沟道区域58中施加应力，从而提高性能。外延源极/漏极区域82被形成在鳍52中，使得每个虚设栅极72被设置在相应的相邻外延源极/漏极区域82的对之间。在一些实施例中，外延源极/漏极区域82可以延伸到鳍52中，并且还可以穿过鳍52。在一些实施例中，栅极间隔件86用于将外延源极/漏极区域82与虚设栅极72分开适当的横向距离，使得外延源极/漏极区域82不会使得随后形成的所得FinFET的栅极短路。
区域50N(例如，NMOS区域)中的外延源极/漏极区域82可以通过掩蔽区域50P(例如，PMOS区域)，并蚀刻区域50N中的鳍52的源极/漏极区域以形成鳍52中的凹陷来形成。然后，区域50N中的外延源极/漏极区域82在凹陷中外延生长。外延源极/漏极区域82可以包括例如适合于n型FinFET的任何可接受的材料。例如，如果鳍52是硅，则区域50N中的外延源极/漏极区域82可以包括在沟道区域58中施加拉伸应变的材料，例如，硅、SiC、SiCP、SiP等。区域50N中的外延源极/漏极区域82可以具有从鳍52的相应表面凸起的表面，并且可以具有刻面。
区域50P(例如，PMOS区域)中的外延源极/漏极区域82可以通过掩蔽区域50N(例如，NMOS区域)，并且蚀刻区域50P中的鳍52的源极/漏极区域以形成鳍52中的凹陷来形成。然后，区域50P中的外延源极/漏极区域82在凹陷中外延生长。外延源极/漏极区域82可以包括例如适合于p型FinFET的任何可接受的材料。例如，如果鳍52是硅，则区域50P中的外延源极/漏极区域82可以包括在沟道区域58中施加压缩应变的材料，例如，SiGe、SiGeB、Ge、GeSn等。区域50P中的外延源极/漏极区域82也可以具有从鳍52的相应表面凸起的表面，并且可以具有刻面。
可以用掺杂剂注入外延源极/漏极区域82和/或鳍52以形成源极/漏极区域，类似于先前讨论的用于形成轻微掺杂源极/漏极区域的工艺，然后进行退火。源极/漏极区域的杂质浓度可以在约1019cm-3和约1021cm-3之间。源极/漏极区域的n型和/或p型杂质可以是前面讨论的任何杂质。在一些实施例中，外延源极/漏极区域82可以在生长期间被原位掺杂。
作为用于在区域50N和区域50P中形成外延源极/漏极区域82的外延工艺的结果，外延源极/漏极区域的上表面具有横向向外扩展超过鳍52的侧壁的刻面。在一些实施例中，这些刻面使得同一FinFET的相邻的源极/漏极区域82合并，如图10C所示。在其他实施例中，相邻的源极/漏极区域82在外延工艺完成之后保持分离，如图10D所示。
在图11A和11B中，去除低k栅极间隔件86以暴露栅极密封间隔件80。在一些实施例中，通过干法蚀刻工艺去除低k栅极间隔件86。例如，蚀刻工艺可以包括使用选择性地蚀刻低k栅极间隔件86而不蚀刻栅极密封间隔件80和源极/漏极区域82的(一个或多个)反应气体的干法蚀刻工艺。在一些实施例中，干法蚀刻工艺中的(一个或多个)反应气体包括NF3、HF和H2O，并且蚀刻工艺可以在从约0℃至约60℃的温度下进行。在去除期间，栅极密封间隔件80可以用作在蚀刻栅极间隔件86时的蚀刻停止层。去除工艺在源极/漏极区域82和栅极结构之间形成凹陷。
在图12A和12B中，在栅极结构、栅极密封间隔件80和源极/漏极区域82上方形成保护层88。保护层88可以通过在图11A和11B中的结构上共形地沉积绝缘材料来形成。在不使用氧前体的情况下形成保护层88，并且通过保护源极/漏极区域82免受氧化所引起的损坏，允许随后形成包括氧的低k间隔件。保护层88可以由SiCN等制成。保护层88可以通过ALD、CVD等或其组合来沉积，并且可以被形成为具有从约10埃到约20埃的厚度。在ALD示例中，该工艺可以通过将诸如二氯硅烷(DCS)(SiH4Cl2)之类的硅前体、诸如丙烯(C3H6)之类的碳前体、以及诸如氨(NH3)之类的氮前体引入掩模74、栅极密封间隔件80、和/或源极/漏极区域82来开始。在实施例中，以从约800sccm至约1200sccm(例如，约1000sccm)的流速引入硅前体，以从约800sccm至约1200sccm(例如，约1000sccm)的流速引入碳前体，并以从约3500sccm至约5500sccm(例如，约3500sccm)的流速引入氮前体。此外，沉积可以在从约600℃至约700℃(例如，约620℃)的温度，并且在约66帕斯卡至约931帕斯卡之间(例如，约530帕斯卡)的压力下进行。保护层88的沉积工艺可以具有从4小时至8小时的持续时间，例如，约6小时。保护层88可以被形成为具有从约40％至约60％的范围内的硅原子浓度，例如，约50％；从约5％至约15％的范围内的碳原子浓度，例如，约10％；以及从约30％至约45％的范围内的氮原子浓度范围，例如，约37％。在一些实施例中，保护层88具有从约6.0至约8.0的k值，例如，约7.0。
在图13A和13B中，在保护层88上方形成替换间隔件层90。可以通过在保护层88上共形地沉积绝缘材料来形成替换间隔件层90。替换间隔件层90可以是低k层，例如，SiOCN、SiOC等。替换间隔件层90可以通过ALD、CVD等、或其组合来沉积，并且可以形成为具有从大约25埃到约50埃的厚度。在ALD示例中，该工艺可以通过将诸如六氯乙硅烷(HCD)(Si2Cl6)、二氯硅烷(DCS)(SiH4Cl2)等或其组合之类的硅前体、诸如丙烯(C3H6)之类的碳前体、诸如氨(NH3)之类的氮前体、以及诸如O2之类的氧前体引入栅极密封间隔件层80来开始。替换间隔件层90可以被形成为具有从约20％至约40％的范围内的硅原子浓度，例如，约30％；从约50％至约65％的范围内的氧原子浓度，例如，约57％；从约0％至约5％的范围内的碳原子浓度，例如，约2.5％；以及从约0％至约15％的范围内的氮原子浓度，例如，约7.5％。在一些实施例中，替换间隔件层90具有小于或等于约3.5的k值。
在图14A和14B中，从掩模74和源极/漏极区域82的顶表面去除替换间隔件层90和保护层88，以形成替换栅极间隔件92。替换间隔件层90和保护层88可以通过诸如各向异性蚀刻工艺之类的蚀刻工艺去除，以形成替换栅极间隔件92。替换栅极间隔件92可以由低k材料形成，并且可以被称为低k栅极间隔件92。
通过使替换栅极间隔件层90由低k材料形成，可以提高FinFET器件的性能，这是由于器件的栅极和源极/漏极区域之间的电容减小。此外，保护层88使得能够减小电容而不会损坏源极/漏极区域82，这些损坏会降低器件的性能。具体地，源极/漏极区域82是外延结构，并且形成在栅极电极的侧壁上的间隔件92被形成为低k间隔件，以减小栅极电极和源极/漏极区域82之间的电容。保护层保护源极/漏极区域并防止它们在低k间隔件92的形成期间被损坏。
在图15A和15B中，在图14A和14B所示的结构上方沉积第一ILD94。第一ILD 94可以由电介质材料形成，并且可以通过任何合适的方法来沉积，例如，CVD、等离子体增强CVD(PECVD)或FCVD。电介质材料可包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等。可以使用通过任何可接受的工艺形成的其他绝缘材料。在一些实施例中，接触蚀刻停止层(CESL)93被设置在第一ILD 94和外延源极/漏极区域82、掩模74、栅极密封间隔件80和替换栅极间隔件92之间。CESL 93可以包括电介质材料，例如，氮化硅、氧化硅、氮氧化硅等，其具有与上覆的第一ILD 94的材料不同的蚀刻速率。
在图16A和16B中，可以执行诸如CMP之类的平坦化工艺以使得第一ILD 94的顶表面与虚设栅极72或掩模74的顶表面齐平。平坦化工艺还可以去除虚设栅极72上的掩模74，以及沿掩模74的侧壁的栅极密封间隔件80和替换间隔件92的部分。在平坦化工艺之后，虚设栅极72、栅极密封间隔件80、替换栅极间隔件92、以及第一ILD 94的顶表面是水平的。因此，虚设栅极72的顶表面通过第一ILD 94暴露。在一些实施例中，掩模74可以保留，在这种情况下，平坦化工艺使第一ILD 94的顶表面与掩模74的顶表面齐平。
在图17A和17B中，在(一个或多个)蚀刻步骤中去除虚设栅极72和掩模74(如果存在的话)，从而形成凹陷96。还可以去除虚设电介质层60在凹陷96中的部分。在一些实施例中，仅去除虚设栅极72，并且虚设电介质层60保留并由凹陷96暴露。在一些实施例中，虚设电介质层60从管芯的第一区域(例如，核逻辑区域)中的凹陷96去除，并保留在管芯的第二区域(例如，输入/输出区域)中的凹陷96中。在一些实施例中，通过各向异性干法蚀刻工艺去除虚设栅极72。例如，蚀刻工艺可以包括使用选择性地蚀刻虚设栅极72而不蚀刻第一ILD94、栅极密封间隔件80或替换栅极间隔件92的(一个或多个)反应气体的干法蚀刻工艺。每个凹陷96暴露相应鳍52的沟道区域58。每个沟道区域58被设置在相邻的外延源极/漏极区域82对之间。在去除期间，虚设电介质层60在虚设栅极72被蚀刻时可以用作蚀刻停止层。然后可以在去除虚设栅极72之后可选地去除虚设电介质层60。
在图18A和18B中，形成栅极电介质层98和栅极电极100以用于替换栅极。图18C示出了图18B的区域99的详细视图。栅极电介质层98被共形地沉积在凹陷96中，例如，在鳍52的顶表面和侧壁上以及在栅极密封间隔件80/替换栅极间隔件92的侧壁上。栅极电介质层98也可以形成在第一ILD 94的顶表面上。根据一些实施例，栅极电介质层98包括氧化硅、氮化硅或其多个层。在一些实施例中，栅极电介质层98包括高k电介质材料，并且在这些实施例中，栅极电介质层98可具有大于约7.0的k值，并且可包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其组合的金属氧化物或硅酸盐。栅极电介质层98的形成方法可以包括分子束沉积(MBD)、ALD、PECVD等。在虚设栅极电介质60的部分保留在凹陷96中的实施例中，栅极电介质层98包括虚设栅极电介质60的材料(例如，SiO2)。
栅极电极100分别沉积在栅极电介质层98上方，并填充凹陷96的其余部分。栅极电极100可以包括含金属材料，例如，TiN、TiO、TaN、TaC、Co、Ru、Al、W、其组合或其多个层。例如，尽管图18B中示出了单层栅极电极100，但栅极电极100可以包括任何数量的衬垫层100A、任意数量的功函数调整层100B和填充材料100C，如图18C所示。在填充栅极电极100之后，可以执行诸如CMP之类的平坦化工艺以去除栅极电介质层98的多余部分和栅极电极100的材料，这些多余部分在ILD 94的顶部表面上方。因此，栅极电极100和栅极电介质层98的材料的剩余部分形成所得FinFET的替代栅极。栅极电极100和栅极电介质层98可以统称为“栅极堆叠”。栅极和栅极堆叠可以沿鳍52的沟道区域58的侧壁延伸。
在区域50N和区域50P中形成栅极电介质层98可以同时发生，使得每个区域中的栅极电介质层98由相同的材料形成，并且形成栅极电极100可以同时发生，使得每个区域中的栅极电极100由相同的材料形成。在一些实施例中，每个区域中的栅极电介质层98可以通过不同的工艺形成，使得栅极电介质层98可以是不同的材料，和/或每个区域中的栅极电极100可以通过不同的工艺形成，使得栅极电极100可以是不同的材料。在使用不同的工艺时，可以使用各种掩蔽步骤来掩蔽和暴露适当的区域。
在图19A和19B中，第二ILD 108被沉积在第一ILD 94上方。在一些实施例中，第二ILD 108是通过可流动CVD方法形成的可流动膜。在一些实施例中，第二ILD 108由诸如PSG、BSG、BPSG、USG等之类的电介质材料形成，并且可以通过任何合适的方法沉积，例如，CVD和PECVD。根据一些实施例，在形成第二ILD 108之前，栅极堆叠(包括栅极电介质层98和相应的上覆栅极电极100)被凹陷，使得直接在栅极堆叠上方并且在栅极密封间隔件80和替换栅极间隔件92的相对部分之间形成凹陷，如图19A和19B所示。在凹陷中填充包括一层或多层电介质材料(例如，氮化硅、氮氧化硅等)的栅极掩模106，然后进行平坦化工艺以去除在第一ILD 94上方延伸的电介质材料的多余部分。随后形成的栅极接触110(图16A和16B)穿透栅极掩模106以接触经凹陷的栅极电极100的顶表面。
在图20A和20B中，根据一些实施例，穿过第二ILD 108和第一ILD94形成栅极接触110和源极/漏极接触112。穿过第一和第二ILD 94和108形成源极/漏极接触112的开口，并且穿过第二ILD 108和栅极掩模106形成栅极接触110的开口。可以使用可接受的光刻和蚀刻技术来形成开口。在开口中形成诸如扩散阻挡层、粘附层等之类的衬垫以及导电材料。衬垫可包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、钴、铝、镍等。可以执行诸如CMP之类的平坦化工艺以从ILD 108的表面去除多余的材料。剩余的衬垫和导电材料在开口中形成源极/漏极接触112和栅极接触110。可以执行退火工艺以在外延源极/漏极区域82和源极/漏极接触112之间的界面处形成硅化物。源极/漏极接触112物理地和电气地耦合到外延源极/漏极区域82，并且栅极接触110物理地和电气地耦合到栅极电极106。源极/漏极接触112和栅极接触110可以以不同的工艺形成，或者可以以相同的工艺形成。尽管示出为被形成在相同的横截面中，但应理解，源极/漏极接触112和栅极接触110中的每一个可以被形成在不同的横截面中，这可以避免接触的短路。
图21A至25B示出了形成替换间隔件92的实施例。该实施例类似于图2至20B的先前实施例，除了在该实施例中，栅极间隔件86被凹陷而不是被移除。在此不再重复与前述实施例类似的关于该实施例的细节。
图21A和21B是与图10A和10B等同的工艺中间阶段，并且这里不再重复描述。
在图22A和22B中，栅极间隔件86被凹陷以暴露沿着虚设栅极72和掩模74的侧壁的栅极密封间隔件80的部分。经凹陷的栅极间隔件86可以称为间隔件基脚(footing)86。在一些实施例中，通过干法蚀刻工艺来凹陷栅极间隔件86。例如，蚀刻工艺可以包括使用选择性地蚀刻低k栅极间隔件86而不蚀刻栅极密封间隔件80和源极/漏极区域82的(一个或多个)反应气体的干法蚀刻工艺。在一些实施例中，干法蚀刻工艺中的(一个或多个)反应气体包括NF3、HF和H2O，并且蚀刻工艺可以在从约0℃至约60℃的温度下进行。在凹陷期间，栅极密封间隔件80在栅极间隔件86被蚀刻时可以用作蚀刻停止层。
在图23A和23B中，在栅极结构、栅极密封间隔件80、经凹陷的栅极间隔件86和源极/漏极区域82上方形成保护层88。保护层88类似于前述实施例的保护层88，并且这里将不再重复描述。
在图24A和24B中，在保护层88上方形成替换间隔件层90。替换间隔件层90类似于前述实施例的替换间隔件层90，并且这里将不再重复描述。在该实施例中，替换栅极间隔件92将包括保护层88、替换栅极间隔件层90和经凹陷的栅极间隔件86。
图25A和25B示出了对图24A和25B的结构的进一步工艺。这些图之间的工艺类似于上面参考图13A至20B所示出和描述的工艺，图25A和25B是与图20A和20B等同的中间阶段，并且这里不再重复描述。
图26A至30B示出了形成替换间隔件92的另一实施例。该实施例类似于图2至20B的先前实施例，除了在该实施例中，替换间隔件92包括低k间隔件层和空气间隔件层。在此不再重复与前述实施例类似的关于该实施例的细节。
图26A和26B是与图11A和11B等同的工艺中间阶段，并且这里不再重复描述。
在图27A和27B中，在栅极密封间隔件80、掩模74和源极/漏极区域82上方形成替换间隔件层122。可以通过栅极密封间隔件80、掩模74和源极/漏极区域82上共形地沉积绝缘材料，以使得在虚设栅极72的侧壁上的源极/漏极区域82和栅极密封间隔件80之间形成气隙120来形成替换间隔件层90。替换间隔件层122覆盖并密封虚设栅极72的侧壁上的源极/漏极区域82和栅极密封间隔件80之间的区域，以形成气隙120。替换间隔件层122可以是低k层，例如，SiCN等。替换间隔件层122可以通过ALD、CVD等或其组合来沉积，并且可以被形成为具有从约25埃到约50埃的厚度。
在ALD示例中，该工艺可以通过将诸如六氯乙硅烷(HCD)(Si2Cl6)、二氯硅烷(DCS)(SiH4Cl2)等或其组合之类的硅前体、诸如丙烯(C3H6)之类的碳前体、以及诸如氨(NH3)之类的氮前体引入栅极密封间隔件层80来开始。在实施例中，以从约300sccm至约600sccm(例如，约450sccm)的流速引入硅前体，以此约4000sccm至约6000sccm(例如，约5000sccm)的流速引入碳前体，并以从约3000sccm至约6000sccm(例如，约4500sccm)的流速引入氮前体。此外，沉积可以在从约600℃至约700℃(例如，约630℃)的温度，并且在约110帕斯卡和约4650帕斯卡之间(例如，约530帕斯卡)的压力下进行。栅极密封间隔件层80的沉积工艺可以具有从4小时至8小时的持续时间，例如，约6小时。替换间隔件层122可以被形成为具有从约40％至约60％的范围内的硅原子浓度，例如，约50％；从约5％至约15％的范围内的碳原子浓度，例如，约10％；以及从约30％至约40％的范围内的氮原子浓度范围，例如，约35％。
在图28A和28B中，对替换间隔件层122执行处理以形成经处理的替换间隔件层124。在一些实施例中，处理是氧化工艺。在一些实施例中，氧化处理工艺在从约300瓦至约500瓦的偏压功率，例如，约400瓦；从约2帕斯卡至约6帕斯卡的压力，例如，约4帕斯卡；从约30℃至约50℃的温度下，例如，约40℃下执行。在一些实施例中，氧化处理工艺仅使用活性氧物质(有时称为氧自由基)。在处理之后，经处理的替换间隔件层124由SiOCN构成。在一些实施例中，经处理的替换间隔件层124具有小于或等于约3.5的k值。
在图29A和29B中，从掩模74和源极/漏极区域82的顶表面去除经处理的替换间隔件层124以形成替换栅极间隔件92。经处理的替换间隔件层124可以通过诸如各向异性蚀刻工艺之类的蚀刻工艺去除以形成替换栅极间隔件92。经处理的替换间隔件层124和气隙120形成替换栅极间隔件92。替换栅极间隔件92可由低k材料和气隙120形成，并且可以称为低k栅极间隔件92。
通过使替换栅极间隔件92由气隙和低k材料形成，可以提高FinFET器件的性能，这是由于器件的栅极和源极/漏极区域之间的电容减小。此外，由于氧未被引入层122中直到源极/漏极区域82被层122覆盖为止，因此氧不会损坏源极/漏极区域82，这些损坏会降低器件的性能。
图30A和30B示出了对图29A和29B的结构的进一步工艺。这些图之间的工艺类似于上面参考图14A到20B所示出和描述的工艺，图30A和30B是与图20A和20B等同的中间阶段，并且这里不再重复描述
图31A至35B示出了形成替换间隔件92的另一实施例。该实施例类似于图26A至30B的先前实施例，除了在该实施例中，替换间隔件92包括经凹陷的栅极间隔件86而不是空气间隔件层。在此不再重复与前述实施例类似的关于该实施例的细节。
图31A和31B是与图22A和22B等同的工艺中间阶段，并且这里不再重复描述。
在图32A和32B中，在栅极结构、栅极密封间隔件80、经凹陷的栅极间隔件86和源极/漏极区域82上方形成替换间隔件层122。替换间隔件层122类似于前述实施例的替换间隔件层122，这里不再重复描述。
在图33A和33B中，形成经处理的替换间隔件层124。经处理的替换间隔件层124类似于前述实施例的经处理的替换间隔件层124，并且这里不再重复描述。
在图34A和34B中，经处理的替换间隔件层124被图案化以形成替换栅极间隔件92，其包括经凹陷的栅极间隔件86和经处理的替换间隔件层124。经处理的替换间隔件层124的图案化类似于前述实施例的经处理的替换间隔件层124的图案化，并且这里将不再重复描述。
图35A和35B示出了对图34A和34B的结构的进一步工艺。这些图之间的工艺类似于上面参考图13A至20B所示出和描述的工艺，图35A和35B是与图20A和20B等同的中间阶段，并且这里不再重复描述。
通过使替换栅极间隔件92由低k材料形成，可以提高FinFET器件的性能，这是由于器件的栅极和源极/漏极区域之间的电容减小。此外，保护层88使得能够减小电容而不会损坏源极/漏极区域82，这些损坏会降低器件的性能。具体地，源极/漏极区域82是外延结构并且形成在栅极电极的侧壁上的间隔件92被形成为低k间隔件以减小栅极电极和源极/漏极区域82之间的电容。保护层保护源极/漏极区域并防止它们在低k间隔件92的形成期间被损坏。
以上概述了若干实施例的特征，使得本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应当理解，他们可以容易地使用本公开作为设计或修改其他工艺和结构以实现本文介绍的实施例的相同目的和/或实现本文介绍的实施例的相同优点的基础。本领域技术人员还应该认识到，这样的等同构造不脱离本公开的精神和范围，并且他们可以在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替换和变更。
示例1是一种半导体器件，包括：第一鳍，从衬底延伸；第一栅极堆叠，位于所述第一鳍的侧壁上方并且沿着所述第一鳍的侧壁被设置；第一栅极间隔件，沿着所述第一栅极堆叠的侧壁被设置；第一外延源极/漏极区域，位于所述第一鳍中并且与所述第一栅极间隔件相邻；以及保护层，位于所述第一外延源极/漏极区域和所述第一栅极间隔件之间，并且所述保护层位于所述第一栅极间隔件和所述第一栅极堆叠之间。
示例2是示例1所述的器件，其中，所述保护层是绝缘层并且与所述第一外延源极/漏极区域实体地接触。
示例3是示例1所述的器件，其中，所述第一栅极间隔件具有小于或等于3.5的电介质常数。
示例4是示例3所述的器件，其中，所述保护层具有第一部分、第二部分和第三部分，所述第一部分沿着所述第一栅极间隔件的第一侧壁延伸，所述第二部分沿着所述第一栅极间隔件的第二侧壁延伸，所述第一侧壁面向所述第一栅极堆叠，所述第二侧壁与所述第一侧壁面向相反的方向，所述保护层的第三部分沿着所述第一栅极间隔件的底表面延伸，所述第三部分从所述第一部分延伸到所述第二部分。
示例5是示例1所述的器件，还包括：蚀刻停止层，位于所述第一外延源极/漏极区域上方，并且所述保护层与所述蚀刻停止层实体地接触。
示例6是示例1所述的器件，还包括：第一栅极密封间隔件，位于所述保护层下方，所述第一栅极密封间隔件位于所述保护层和所述第一栅极堆叠之间。
示例7是示例6所述的器件，其中，所述保护层是由SiCN制成的，所述第一栅极间隔件是由SiOCN制成的，并且所述第一栅极密封间隔件是由SiCN制成的。
示例8是示例6所述的器件，还包括：第一间隔件基脚，位于所述保护层下方，所述第一间隔件基脚位于所述第一栅极密封间隔件和所述第一外延源极/漏极区域之间，所述保护层在所述第一外延源极/漏极区域上方延伸。
示例9是示例8所述的器件，其中，所述第一间隔件基脚是由SiOCN制成的，其中，所述第一间隔件基脚与所述第一栅极间隔件相比具有不同的材料成分。
示例10是一种用于形成半导体器件的方法，包括：在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；沿着所述第一栅极的侧壁形成第一低k栅极间隔件；在所述第一鳍中与所述第一低k栅极间隔件相邻地蚀刻第一凹陷；在所述第一凹陷中外延生长第一源极/漏极区域；去除所述第一低k栅极间隔件，所述去除在所述第一栅极和所述第一源极/漏极区域之间形成第二凹陷；在所述第一栅极上方、在所述第一源极/漏极区域上方、并且在所述第二凹陷中形成保护层；在所述保护层上方形成低k层；以及蚀刻所述低k层以在所述第二凹陷中形成第二低k栅极间隔件，所述第二低k栅极间隔件沿着沿所述第一栅极的侧壁延伸的所述保护层延伸。
示例11是示例10所述的方法，其中，所述保护层是绝缘层并且与所述第一源极/漏极区域实体地接触。
示例12是示例10所述的方法，还包括：在所述第一栅极、所述第二低k栅极间隔件和所述第一源极/漏极区域上方形成蚀刻停止层；在所述蚀刻停止层上方形成第一电介质层；平坦化所述第一电介质层以具有与所述第一栅极水平的顶表面；用第二栅极替换所述第一栅极；在所述第二栅极和所述第一电介质层上方形成第二电介质层；以及形成穿过所述第一电介质层和所述第二电介质层到所述第一源极/漏极区域的导电接触。
示例13是示例12所述的方法，其中，所述蚀刻停止层与所述保护层实体地接触，并且其中，所述保护层与所述第一源极/漏极区域实体地接触。
示例14是示例10所述的方法，还包括：在所述第一栅极的侧壁上并且在所述第一鳍上形成第一栅极密封间隔件，所述第一低k栅极间隔件被形成在所述第一栅极密封间隔件上。
示例15是示例14所述的方法，其中，所述保护层是由SiCN制成的，所述第一低k栅极间隔件是由SiOCN制成的，并且所述第一栅极密封间隔件是由SiCN制成的。
示例16是一种用于形成半导体器件的方法，包括：在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；沿着所述第一栅极的侧壁形成第一低k栅极间隔件；在所述第一鳍上与所述第一低k栅极间隔件相邻地外延生长第一源极/漏极区域；蚀刻所述第一低k栅极间隔件；在所述第一栅极和所述第一源极/漏极区域上方形成电介质层；对所述电介质层上执行氧处理；以及蚀刻经处理的电介质层以沿着所述第一栅极的侧壁形成第二栅极间隔件。
示例17是示例16所述的方法，其中，蚀刻所述第一低k栅极间隔件使所述第一低k栅极间隔件凹陷，所述电介质层被形成在经凹陷的第一低k栅极间隔件上方。
示例18是示例17所述的方法，其中，经凹陷的第一低k栅极间隔件是由SiOCN制成的，其中，所述第二栅极间隔件是由SiOCN制成的，经凹陷的第一低k间隔件与所述第二栅极间隔件相比具有不同的材料成分。
示例19是示例16所述的方法，其中，所述蚀刻所述第一低k栅极间隔件去除所述第一低k栅极间隔件并且形成第二凹陷，所述电介质层被形成为在所述第二凹陷上方延伸并且在所述第一源极/漏极区域和所述第一栅极之间形成气隙。
示例20是示例16所述的方法，其中，所述第二栅极间隔件与所述第一源极/漏极区域实体地接触。

Claims (10)

1.一种半导体器件，包括：
第一鳍，从衬底延伸；
第一栅极堆叠，位于所述第一鳍的侧壁上方并且沿着所述第一鳍的侧壁被设置；
第一栅极间隔件，沿着所述第一栅极堆叠的侧壁被设置；
第一外延源极/漏极区域，位于所述第一鳍中并且与所述第一栅极间隔件相邻；以及
保护层，位于所述第一外延源极/漏极区域和所述第一栅极间隔件之间，并且所述保护层位于所述第一栅极间隔件和所述第一栅极堆叠之间。
2.根据权利要求1所述的器件，其中，所述保护层是绝缘层并且与所述第一外延源极/漏极区域实体地接触。
3.根据权利要求1所述的器件，其中，所述第一栅极间隔件具有小于或等于3.5的电介质常数。
4.根据权利要求3所述的器件，其中，所述保护层具有第一部分、第二部分和第三部分，所述第一部分沿着所述第一栅极间隔件的第一侧壁延伸，所述第二部分沿着所述第一栅极间隔件的第二侧壁延伸，所述第一侧壁面向所述第一栅极堆叠，所述第二侧壁与所述第一侧壁面向相反的方向，所述保护层的第三部分沿着所述第一栅极间隔件的底表面延伸，所述第三部分从所述第一部分延伸到所述第二部分。
5.根据权利要求1所述的器件，还包括：
蚀刻停止层，位于所述第一外延源极/漏极区域上方，并且所述保护层与所述蚀刻停止层实体地接触。
6.根据权利要求1所述的器件，还包括：
第一栅极密封间隔件，位于所述保护层下方，所述第一栅极密封间隔件位于所述保护层和所述第一栅极堆叠之间。
7.根据权利要求6所述的器件，其中，所述保护层是由SiCN制成的，所述第一栅极间隔件是由SiOCN制成的，并且所述第一栅极密封间隔件是由SiCN制成的。
8.根据权利要求6所述的器件，还包括：
第一间隔件基脚，位于所述保护层下方，所述第一间隔件基脚位于所述第一栅极密封间隔件和所述第一外延源极/漏极区域之间，所述保护层在所述第一外延源极/漏极区域上方延伸。
9.一种用于形成半导体器件的方法，包括：
在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；
沿着所述第一栅极的侧壁形成第一低k栅极间隔件；
在所述第一鳍中与所述第一低k栅极间隔件相邻地蚀刻第一凹陷；
在所述第一凹陷中外延生长第一源极/漏极区域；
去除所述第一低k栅极间隔件，所述去除在所述第一栅极和所述第一源极/漏极区域之间形成第二凹陷；
在所述第一栅极上方、在所述第一源极/漏极区域上方、并且在所述第二凹陷中形成保护层；
在所述保护层上方形成低k层；以及
蚀刻所述低k层以在所述第二凹陷中形成第二低k栅极间隔件，所述第二低k栅极间隔件沿着沿所述第一栅极的侧壁延伸的所述保护层延伸。
10.一种用于形成半导体器件的方法，包括：
在从衬底向上延伸的第一鳍的侧壁上方并且沿着所述第一鳍的侧壁形成第一栅极；
沿着所述第一栅极的侧壁形成第一低k栅极间隔件；
在所述第一鳍上与所述第一低k栅极间隔件相邻地外延生长第一源极/漏极区域；
蚀刻所述第一低k栅极间隔件；
在所述第一栅极和所述第一源极/漏极区域上方形成电介质层；
对所述电介质层上执行氧处理；以及
蚀刻经处理的电介质层以沿着所述第一栅极的侧壁形成第二栅极间隔件。
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