TWI629787B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI629787B
TWI629787B TW104133660A TW104133660A TWI629787B TW I629787 B TWI629787 B TW I629787B TW 104133660 A TW104133660 A TW 104133660A TW 104133660 A TW104133660 A TW 104133660A TW I629787 B TWI629787 B TW I629787B
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TW201626563A (zh
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陳皇魁
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供了半導體結構，半導體結構包括具有第一和第二表面的半導體層、以及分別限定位於第一和第二表面上方的第一金屬閘極和第二金屬閘極的層間電介質(ILD)。第一和第二金屬閘極分別包括第一SAC硬遮罩和第二SAC硬遮罩，其中，第一和第二SAC硬遮罩分別向位於第一和第二金屬閘極下方的通道區施加相反的應力。本揭露提供了製造半導體結構的方法。該方法分別包括形成金屬閘極凹槽、在金屬閘極凹槽中形成金屬閘極和SAC硬遮罩。本揭露涉及半導體結構及其製造方法。

Description

半導體結構及其製造方法
本揭露是有關於一種半導體結構及其製造方法。
半導體積體電路(IC)產業經歷了快速發展。在IC發展過程中，功能密度(即，每晶片面積上互連器件的數量)普遍增加，而幾何尺寸(即，使用製造製程可以創建的最小的元件(或線))卻已下降。這種按比例縮小製程通常通過提高生產效率和降低相關成本而提供益處。這種按比例縮小也增加了加工和製造IC的複雜性，並且為了實現這些進步，需要IC加工和製造中的類似發展。隨著電晶體尺寸的減小，閘極氧化物的厚度必須減小以在具有減小的閘極長度的情況下維持性能。然而，為了降低閘極漏電流，使用高介電常數(高k)閘極絕緣層，其在保持與由在更大的技術世代中使用的典型的閘極氧化物所提供的相同有效電容的同時，允許更大的物理厚度。
此外，隨著技術製程世代縮小，在一些IC設計中，期望以金屬閘(MG)電極代替典型的多晶矽閘電極以在部件尺寸減小的情況下改進器件性能。形成MG電極的一種製程被稱為“後閘極”製程，其與稱為“先閘極”的另一種MG電極形成製程相反。“後閘極”製程允許後續製程的數量降低，包括必須在閘極形成之後實施的高溫處理。
因此，期望為形成在基板上的每個NFET、PFET、N-FinFET和P-FinFET提供不同配置的金屬閘極結構的方法和半導 體器件。
為了解決現有技術中存在的問題，根據本揭露的一個方面，提供了一種半導體結構，包括：半導體基板，包括第一表面和第二表面；層間電介質(ILD)，具有位於所述半導體基板的所述第一表面上方的第一凹槽和位於所述半導體基板的所述第二表面上方的第二凹槽；第一間隔件和第二間隔件，所述第一間隔件襯於所述第一凹槽的側壁上，所述第二間隔件襯於所述第二凹槽的側壁上；第一高k介電層和第二高k介電層，所述第一高k介電層接觸所述第一凹槽的底部和所述第一間隔件的側壁，所述第二高k介電層接觸所述第二凹槽的底部和所述第二間隔件的側壁；第一金屬和第二金屬，所述第一金屬接觸所述第一高k介電層的底部和側壁，所述第二金屬接觸所述第二高k介電層的底部和側壁；其中，所述第一金屬和第二金屬用於彼此不同導電類型的半導體；以及第一SAC(自對準接觸)硬遮罩和第二SAC硬遮罩，所述第一SAC硬遮罩位於所述第一金屬上，所述第二SAC硬遮罩位於所述第二金屬上。
在上述半導體結構中，所述第一SAC硬遮罩位於所述第一金屬和所述第一間隔件上。
在上述半導體結構中，所述第二SAC硬遮罩位於所述第二金屬和所述第二間隔件上。
在上述半導體結構中，所述第一SAC硬遮罩或所述第二SAC硬遮罩包括氮化物。
在上述半導體結構中，所述第一SAC硬遮罩的縱向高度和所述第二SAC硬遮罩的縱向高度基本上彼此不同。
在上述半導體結構中，所述第一金屬的縱向高度和所述第二金屬的縱向高度不同。
在上述半導體結構中，所述第一SAC硬遮罩具有上部和下部，所述第一SAC硬遮罩的所述上部和所述下部的橫向長度不同。
在上述半導體結構中，所述第二SAC硬遮罩具有上部和下部，所述第二SAC硬遮罩的所述上部和所述下部的橫向長度不同。
根據本揭露的另一方面，還提供了一種半導體結構，包括：半導體基板，包括表面；層間電介質(ILD)，具有位於所述半導體基板的所述表面上方的凹槽；第一間隔件，襯於所述凹槽的側壁上；源極/汲極區，位於所述半導體基板中，鄰近所述凹槽下方的通道區；高k介電層，接觸所述凹槽的底部和所述第一間隔件的側壁；金屬，接觸所述高k介電層的底部和側壁；以及SAC硬遮罩，位於所述金屬上，其中，所述SAC硬遮罩具有上部和下部，並且所述SAC硬遮罩的所述上部和所述下部的橫向長度不同。
在上述半導體結構中，第二間隔件在縱向方向上夾在所述第一間隔件和所述層間電介質之間，並且在橫向方向上夾在所述表面和所述層間電介質之間。
在上述半導體結構中，所述第二間隔件包括氮化物。
在上述半導體結構中，所述源極/汲極區是磊晶層。
在上述半導體結構中，所述SAC硬遮罩包括氮化物並且所述層間電介質包括氧化物。
在上述半導體結構中，所述凹槽具有上部和下部，並且所述上部的橫向長度基本上長於所述下部的橫向長度。
在上述半導體結構中，所述半導體結構是FinFET結構。
根據本揭露的又一方面，還提供了一種製造半導體結構的方法，包括：在層間電介質(ILD)中形成第一凹槽和第二凹槽；形成襯於所述第一凹槽的側壁上的第一間隔件和襯於所述第二凹槽的側壁上的第二間隔件；形成接觸所述第一凹槽的底部和所述第一間隔 件的側壁的第一高k介電層；形成接觸所述第一高k介電層的底部和側壁的第一金屬；形成接觸所述第二凹槽的底部和所述第二間隔件的側壁的第二高k介電層；形成接觸所述第二高k介電層的底部和側壁的第二金屬；以及在所述第一金屬上形成第一SAC硬遮罩和在所述第二金屬上形成第二SAC硬遮罩。
在上述方法中，包括去除位於所述第二金屬上的所述第一SAC硬遮罩。
在上述方法中，還包括回蝕刻所述第一金屬或所述第二金屬。
在上述方法中，還包括：通過使用蝕刻劑在所述層間電介質中形成接點以暴露源極/汲極區。
在上述方法中，還包括確定所述第一金屬和所述第二金屬的應力需求。
100‧‧‧半導體層
101‧‧‧ILD
101a‧‧‧第一表面
103a‧‧‧第一金屬閘極
105a‧‧‧第一金屬層
107a‧‧‧第一SAC硬遮罩
1011a‧‧‧第一源極/汲極區
1031a‧‧‧中間層
1033a‧‧‧高k介電層
1035a‧‧‧第一間隔件
101b‧‧‧第二表面
103b‧‧‧第二金屬閘極
105b‧‧‧第二金屬層
107b‧‧‧第二SAC硬遮罩
1011b‧‧‧第二源極/汲極區
1031b‧‧‧中間層
1033b‧‧‧第二高k介電層
1035b‧‧‧第二間隔件
30‧‧‧FinFET結構
31‧‧‧基板
300‧‧‧半導體鰭
300A‧‧‧頂面
300B‧‧‧側壁
301‧‧‧ILD
302‧‧‧STI
303‧‧‧金屬閘極
2013a‧‧‧犧牲閘電極
2013b‧‧‧犧牲閘電極
2037‧‧‧外部間隔件
203a‧‧‧第一金屬閘極凹槽
203b‧‧‧第二金屬閘極凹槽
1031a'‧‧‧中間層
1031b'‧‧‧中間層
2034a‧‧‧第一蓋層
2034b‧‧‧第二蓋層
2036a‧‧‧第一功函金屬層
2036b‧‧‧第二功函金屬層
2038a‧‧‧閘極填充金屬
2038b‧‧‧閘極填充金屬
905‧‧‧光阻
209a‧‧‧接點
209b‧‧‧接點
藉由參照前述說明及下列圖式，本揭露之技術特徵及優點得以獲得完全瞭解。
圖1是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖；圖2是根據本揭露的一些實施例的具有金屬閘極結構的鰭式場效應電晶體(FinFET)的透視圖；圖3是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖4是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖5是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作； 圖6是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖7是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖8是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖9是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖10是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖11是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作；圖12是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖13是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖14是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖15是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖16是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖17是根據本揭露的一些實施例的用於金屬閘極和硬遮罩的半導體結構製造方法的操作；圖18是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖； 圖19是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖；圖20是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖；圖21是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖；圖22是根據本揭露的一些實施例的具有金屬閘極和硬遮罩的半導體結構的截面圖；圖23是根據本揭露的一些實施例的具有金屬閘極、硬遮罩和接點的半導體結構的截面圖。
在以下詳細描述中，闡述了大量具體細節以提供本揭露的更透徹的理解。然而，本領域普通技術人員應當理解，可以在不具有這些具體細節的情況下實踐本揭露。在其他情況下，沒有詳細描述公知的方法、工序、部件和電路以便不模糊本揭露。應當理解，以下公開內容提供了用於實現各個實施例的不同特徵的許多不同的實施例或實例。以下描述部件和佈置的具體實例以簡化本揭露。當然，這些僅僅是實例而不在於限制。
下文中詳細討論了本揭露實施例的製造和使用。然而，應該理解，本揭露提供了許多可以在各種具體環境中實現的可應用的發明概念。所討論的具體實施例僅僅示出製造和使用本揭露的具體方式，而不用於限制本揭露的範圍。
在本揭露中，論述了具有不同應力的NMOS和PMOS的半導體結構及其製造方法。
圖1示出了具有第一金屬閘極103a和第二金屬閘極103b的半導體結構10的截面圖，其中第一金屬閘極103a的導電類型不同於 第二金屬閘極103b的導電類型。例如，如果第一金屬閘極103a是P型閘極，則第二金屬閘極103b是N型。半導體結構10具有半導體層100，其中，層間介電層(ILD)101設置在半導體層100上方。ILD 101也限定並且圍繞第一金屬閘極103a和第二金屬閘極103b。
仍參考圖1，第一金屬閘極103a和第二金屬閘極103b分隔開。如圖1所示，在一些實施例中，STI(淺溝槽隔離)區域102在半導體層100中並且位於第一金屬閘極103a和第二金屬閘極103b之間。半導體層100具有接近第一金屬閘極103a下方的通道區的第一表面101a以及接近第二金屬閘極103b下方的通道區的第二表面101b。第一源極/汲極區1011a位於半導體基板中，並且第一源極/汲極區1011a鄰近第一金屬閘極103a下方的通道區。第二源極/汲極區1011b位於半導體基板中，並且第二源極/汲極區1011b鄰近第二金屬閘極103b下方的通道區。第一SAC硬遮罩107a位於第一金屬閘極103a的頂上，並且第二SAC硬遮罩107b位於第二金屬閘極103b的頂上。
在圖1中，第一間隔件1035a設置在ILD 101和第一金屬閘極103a之間。第二間隔件1035b設置在ILD 101和第二金屬閘極103b之間。第一金屬閘極103a、第一間隔件1035a和ILD 101設置在半導體層100的第一表面101a上方。第二金屬閘極103b、第二間隔件1035b和ILD 101設置在半導體層100的第二表面101b上方。
第一高k介電層1033a接觸第一金屬閘極103a的底部和第一間隔件1035a的側壁，並且第二高k介電層1033b接觸第二金屬閘極103b的底部和第二間隔件1035b的側壁。第一金屬閘極103a包括接觸第一高k介電層1033a的第一金屬層105a。並且類似於第一金屬閘極103a，第二金屬閘極103b包括接觸第二高k介電層1033b的第二金屬層105b。然而，第一金屬層105a的導電類型可以不同於第二金屬層105b的導電類型。例如，如果第一金屬層105a是P型閘極，則第二金屬層105b 是N型閘極。
在本揭露的一些實施例中，本文中所述的半導體基板100是其上形成有各個層和器件結構的塊狀半導體基板。在一些實施例中，塊狀基板包括矽或化合物半導體，諸如GaAs、InP、Si/Ge或SiC。在半導體基板100上可以形成各個層。例如，介電層、摻雜層、多晶矽層或導電層。可以在半導體基板101上形成各種器件。例如，電晶體、電阻器和/或電容器，其可以通過互連層互連至額外的積體電路。
仍參考圖1，第一間隔件1035a圍繞第一金屬閘極103a的側壁部分，並且金屬閘極103a的底部設置在第一表面101a上方。在一些實施例中，金屬閘極103a包括位於第一高k介電層1033a的水準部分和第一表面101a之間的任選的中間層1031a。第二間隔件1035b圍繞第二金屬閘極103b的側壁部分，並且金屬閘極103b的底部設置在第二表面101b上方。並且類似於金屬閘極103a，金屬閘極103b還包括位於第二高k介電層1033b的水準部分和第二表面101b之間的任選的中間層1031b。
第一SAC硬遮罩107a和第二SAC硬遮罩107b可以配置為具有不同的特徵性能以提高電晶體的性能。例如，當第一金屬閘極103a是N型閘極時，優選具有引入到第一金屬閘極103a下方的通道區的拉伸應力，以提高載子遷移率。相反，由於第二金屬閘極103b是P型，優選具有引入到第二金屬閘極103b下方的通道區的壓縮應力，以提高載子遷移率。
在本揭露中，具有通過配置用於不同金屬閘極的SAC硬遮罩的膜性能來分別調整引入到金屬閘極103a和103b下方的通道區的應力的各種方法。例如，在SAC硬遮罩的形成過程中，第一SAC硬遮罩107a和第二SAC硬遮罩107b可以形成為不同的形狀，或通過諸如不同的壓力、等離子體密度或RF功率的不同的製程條件來形成。實施例 及其製造方法的細節將在後面給出。在一些實施例中，ILD 101包括介電材料。例如，介電材料包括氧化矽、氮化矽、氮氧化矽、自旋玻璃(SOG)、氟化石英玻璃(FSG)、碳摻雜的氧化矽(例如，SiCOH)、BLACK DIAMOND®(加利福尼亞聖克拉拉的應用材料公司)、XEROGEL®、AEROGEL®、氟化非晶碳、聚對二甲苯、BCB(雙苯並環丁烯)、FLARE®、SILK®(密西根米德蘭陶氏化學)、聚醯亞胺、其他合適的多孔聚合物材料、其他合適的介電材料、和/或它們的組合。在一些實施例中，ILD 101包括高密度等離子體(HDP)介電材料(例如，HDP氧化物)和/或高高寬比製程(HARP)介電材料(例如，HARP氧化物)。應當理解，ILD 101可以包括一種或多種介電材料和/或一個或多個介電層。如圖1所示，通過化學機械拋光(CMP)製程平坦化ILD 101直到暴露出第一金屬閘極103a和第二金屬閘極103b的頂部。CMP製程包括高選擇性以提供第一金屬閘極103a和第二金屬閘極103b、第一間隔件1035a和第二間隔件1035b以及ILD 101的基本上平坦的表面。在一些實施例中，CMP製程具有低凹陷和/或金屬腐蝕效果。
例如，在一些實施例中，第一間隔件1035a和第二間隔件1035b包括氧化矽、氮化矽、氮氧化矽、其他合適的材料、和/或它們的組合。間隔件可以通過ALD、CVD、金屬有機CVD(MOCVD)、PVD、等離子體增強CVD(PECVD)、等離子體增強ALD(PEALD)、熱氧化、它們的組合或其他適合的技術形成。
在本揭露的一些實施例中，第一高k介電層1033a和第二高k介電層1033b是由ALD、CVD、金屬有機CVD(MOCVD)、PVD、等離子體增強CVD(PECVD)、等離子體增強ALD(PEALD)、熱氧化、它們的組合或其他適合的技術形成的。在一些實施例中，第一高k介電層1033a和第二高k介電層1033b包括介於約5至約30範圍內的厚度。第一高k介電層1033a和第二高k介電層1033b包括二元或三元高-k 膜。在一些實施例中，第一高k介電層1033a和第二高k介電層1033b包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物或其他合適的材料。
在一些實施例中，第一金屬閘極層105a和第二金屬閘層105b分別包括蓋層、功函金屬層和閘極填充金屬。
蓋層包括諸如TiN、TaN的金屬氮化物或諸如碳氮化鈦的金屬碳氮化物或具有通式(M1，M2)(C，N)的另一四元層，其中M1，M2是IVa或Va族的不同金屬。在一些實施例中，蓋層的厚度介於從約2至約40的範圍內。蓋層用作阻擋件以保護高k介電層1033a和1033b。通過諸如ALD、PVD、CVD、PECVD的各種沉積技術或其他適合的技術形成蓋層。
在一些實施例中，蓋層是包括至少兩個材料層的複合膜堆疊件。例如，接近高k介電層(1033a或1033b)的一個蓋層由金屬氮化物或金屬碳氮化物的第一組分製成，而接近功函金屬層的另一蓋層是由金屬氮化物或金屬碳氮化物的第二組分製成。例如，該功函金屬層的複合膜可以是相同的材料，但原子濃度不同。例如，該功函金屬層的複合膜可以是不同的材料。
在一些實施例中，接近高k介電層(1033a或1033b)的蓋層稱為阻擋層。在一些實施例中，接近高k介電層(1033a或1033b)的蓋層的厚度介於約1至約20的範圍內。接近功函金屬層的蓋層的厚度介於約1至約20的範圍內。
在一些實施例中，功函金屬層包括諸如TiCN的金屬碳氮化物、諸如TiSiN的金屬矽氮化物、或金屬鋁化物。在一些實施例中，功函金屬層由金屬碳氮化物或金屬矽氮化物製成。在其他實施例中，功函金屬層包括TiAlN、TiAl、或TaAl。可以通過諸如ALD、PVD、CVD、 PECVD或其他適合的技術的各種沉積技術來沉積功函金屬層。在一些實施例中，功函金屬層的厚度介於約1至約100的範圍內。
在一些實施例中，在金屬閘極103a和103b中設置閘極填充金屬。閘極填充金屬包括具有介於4.2eV至4.8eV之間的獨立功函數的金屬。在一些實施例中，閘極填充金屬包括W、Al、Co、和它們的合金。在一些實施例中，閘極填充金屬的厚度介於約50至3000之間。
例如，在一些實施例中，第一SAC硬遮罩107a和第二SAC硬遮罩107b可以由CVD、PECVD、HDP、IPM或其他適合的技術形成。在一些實施例中，第一SAC硬遮罩107a和第二SAC硬遮罩107b包括介於約50至約400範圍內的厚度。在一些實施例中，第一SAC硬遮罩107a和第二SAC硬遮罩107b包括氮化物。
由於半導體器件尺寸的縮小，FinFET結構用於提高器件性能。圖2是FinFET結構30的透視圖。兩個半導體鰭300設置在基板31上並且通過STI 302分隔開。半導體鰭300可以由矽、鍺矽、鍺、或其他合適的半導體材料形成。金屬閘極303位於半導體鰭300的頂面300A和側壁300B上方。電晶體的通道(未示出)限定為沿著半導體鰭的頂面300A和側壁300B並且在半導體鰭300的源極/汲極區之間延伸。如圖2所示，ILD 301設置為覆蓋並且圍繞半導體鰭300。
在一些實施例中，半導體結構10是具有從約10nm至約40nm的通道長度Lg的平面N-MOSFET或P-MOSFET。在其他實施例中，半導體結構10是具有從約5nm至約40nm的通道長度Lg的非平面N-FinFET或P-FinFET。
圖3至圖21是根據本揭露的一些實施例的用於金屬閘極結構的半導體結構製造方法的操作。
在圖3中，犧牲閘電極2013a和2013b被覆蓋在ILD 101內。
在一些實施例中，第一中間層1031a和第二中間層1031b 由在犧牲閘電極2013a和2013b的去除或蝕刻期間具有選擇性的材料形成。中間層用作當去除犧牲閘電極2013a和2013b時的下面的半導體層100的保護層。如果中間層1031a和1031b是熱生長的電介質，則它們將僅形成在半導體層100的暴露表面上。如果中間層1031a和1031b是通過沉積操作形成的，則它們將毯式沉積到半導體層100下方的絕緣基板(未示出)上以及半導體層100上。
間隔件1035a和1035b分別形成在犧牲閘電極2013a和2013b的側壁上。外部間隔件2037的縱向部分夾在間隔件1035a、1035b和ILD 101之間。外部間隔件2037的橫向部分夾在表面101a、101b和ILD 101之間。間隔件1035a和1035b以及外部間隔件2037均可以通過毯式沉積共形介電膜以覆蓋犧牲閘電極2013a和2013b來形成。在一些實施例中，外部間隔件2037包括氮化物。
形成間隔件和外部間隔件2037的材料包括但不限於氮化矽、氧化矽、氮氧化矽或它們的組合。在本揭露的一些實施例中，間隔件是由熱壁(hot wall)、低壓化學氣相沉積(LPCVD)操作形成的氮化矽膜。可以採用各向異性蝕刻以去除毯式沉積的間隔件和外部間隔件膜的部分。
在圖4中，在形成ILD 101之後，實施諸如化學機械拋光(CMP)操作的平坦化操作。執行平坦化操作以去除位於犧牲閘電極2013a和2013b的頂面上方的過量的ILD 101，直至犧牲閘電極2013a和2013b從ILD 101暴露出來。
在圖5中，通過去除第一犧牲閘電極2013a和中間層1031a形成第一金屬閘極凹槽203a。通過去除第二犧牲閘電極2013b和中間層1031b形成第二金屬閘極凹槽203b。在一些實施例中，犧牲閘電極2013a和2013b由多晶矽形成。通過利用包括四甲基氫氧化銨和水的濕蝕刻劑去除多晶矽犧牲閘電極2013a和2013b。
在本揭露的實施例中，濕蝕刻劑溶液包括約10-35%體積的四甲基氫氧化銨。在本揭露的實施例中，在蝕刻期間將四甲基氫氧化銨溶液加熱至在60攝氏度至95攝氏度之間的溫度。在本揭露的實施例中，在蝕刻製程期間施加諸如超聲波或兆聲波的聲波能量。聲波能量向蝕刻劑提供攪動，這使得蝕刻殘留物從改變的犧牲閘電極2013a、2013b移除，從而允許新的蝕刻劑進入溝槽以分別蝕刻犧牲閘電極2013a和2013b。
在本揭露的一些實施例中，用於第一犧牲閘電極2013a的蝕刻劑對中間層1031a具有選擇性，並且用於第二犧牲閘電極2013b的蝕刻劑對中間層1031b具有選擇性(即，不蝕刻或僅輕微蝕刻中間層1031a和1031b)，從而使得中間層1031a和1031b分別用作用於犧牲閘電極2013a和2013b蝕刻的蝕刻停止層。以這種方式，第一金屬閘極凹槽203a的下面的通道區和第二金屬閘極凹槽203b的下面的通道區可以免受蝕刻劑的影響。在一些實施例中，犧牲閘電極與中間層電介質之間的蝕刻選擇性為至少10：1是所期望的。
進行下一步操作，去除中間層1031a和1031b。在本揭露的實施例中，中間層1031a和1031b是氧化物並且可以利用包括氫氟酸水溶液的蝕刻劑去除。在本揭露的實施例中，使用具有1-2%的體積的HF的蝕刻劑溶液。
參考圖6，在金屬閘極凹槽203a和203b的底部上形成中間層1031a’和1031b’。以共形的方式在第一金屬閘極凹槽203a內部和ILD 101的頂上形成第一高k介電層1033a。類似地，以共形的方式在第二金屬閘極凹槽203b內部和ILD 101的頂上形成第二高k介電層1033b。在一些實施例中，中間層1031a’和1031b’對設計者而言是可選擇的，從而使得可直接形成接近半導體層100的通道區的高k介電層1033a和1033b。
在本揭露的實施例中，分別生長厚度介於約5至50之間的高k介電層1033a和1033b。在本揭露的實施例中，高k介電層1033a和1033b是沉積的電介質，諸如但不限於金屬氧化物電介質，諸如五氧化鉭(Ta2O5)和氧化鈦(TiO2)、氧化鉭、氧化鉿、氧化鋯、氧化鋁、氧化鑭、氧化鑭鋁和它們的矽酸鹽或其他高k電介質，諸如PZT和BST。可以通過諸如但不限於化學氣相沉積(CVD)或原子層沉積(ALD)的技術形成高k介電膜。
參考圖7，第一蓋層2034a形成在第一高k介電層1033a上，並且第二蓋層2034b形成在第二高k介電層1033b上。在一些實施例中，蓋層2034a和2034b包括厚度介於約1至約30範圍內的TiN或TaN。蓋層2034a和2034b用作阻擋件以保護高k介電層1033a和1033b。可以通過諸如ALD、PVD、CVD、PECVD或其他適合的技術的各種沉積技術形成蓋層2034a和2034b。
在一些實施例中，蓋層2034a和2034b包括複合膜堆疊件。例如，複合膜堆疊件可以由任意兩個金屬碳氮化物層TiN和TaN製成。在一些實施例中，TiN或TaN可以具有從約1至約20的厚度。
圖8示出了在第一金屬閘極凹槽203a中形成第一功函金屬層2036a和在第二金屬閘極凹槽203b中形成第二功函金屬層2036b之後的截面圖。設計者可以使用本領域中的圖案化技術以分別形成功函金屬2036a和2036b。
為了簡化的目的，將包括第一功函金屬層2036a的電晶體定義為第一電晶體，並且將包括第二功函金屬層2036b的電晶體定義為第二電晶體。分別形成在金屬閘極凹槽203a和203b中的功函金屬層2036a和2036b使得第一和第二電晶體具有相反的導電類型。例如，如果第一電晶體作為P型電晶體，則第二電晶體作為N型電晶體。
在一些實施例中，通過原子層沉積、物理汽相沉積、化 學氣相沉積、濺射、或其他合適的操作在蓋層2034a和2034b上形成功函金屬層2036a和2036b。在一些實施例中，功函金屬層2036a和2036b包括合適的金屬化合物，諸如金屬碳氮化物、金屬鋁化物、金屬矽氮化物、TiN、TiSiN、TiAlN、TiAl、TaAl、TaN、或Ru。在一些實施例中，功函金屬層2036a和2036b包括諸如TiN/WN的多金屬層結構。
在一些實施例中，通過ALD操作在功函金屬層2036a或2036b內摻雜鋁原子。在其他實施例中，在形成功函金屬層2036a或2036b之後，執行鋁離子注入操作以調整金屬閘電極的閾值電壓或功函數。
參考圖9，閘極凹槽形成為具有諸如2038a和2038b的填充金屬。在一些實施例中，填充金屬過填充凹槽。在一些實施例中，將包括Al、W、WN、TaN或Ru的單一金屬濺射到金屬閘極凹槽203a和203b內，和隨後通過CMP操作(未示出)以去除過量的閘極填充金屬2038a/2038b。在一些實施例中，功函金屬層2036a/2036b、蓋層2034a/2034b、和高k介電層1033a/1033b也從ILD 101的頂面去除。在一些實施例中，閘極填充金屬2038a和2038b包括諸如TaN、TiN、W、WN、和WCN或它們的任何組合的複合膜堆疊結構。
為簡化起見，在填充閘極填充金屬2038a和2038b後，將包括第一功函金屬層2036a的金屬閘極結構定義為第一金屬閘極，並且將包括第二功函金屬層2036b的金屬閘極結構定義為第二金屬閘極。在圖10中，回蝕刻第一和第二金屬閘極的上部以限定位於第一金屬閘極和第二金屬閘極中的溝槽。在一些實施例中，第一和第二金屬閘極的回蝕刻製程是濕蝕刻製程。在一些實施例中，在濕蝕刻製程中使用的蝕刻劑是磷酸。
在圖11中，第一SAC硬遮罩107a形成在ILD 101上並且覆蓋金屬閘極中的溝槽。如圖12所示，去除第一SAC硬遮罩107a的一部 分以達到預定的高度，從而使得第一SAC硬遮罩107a的至少部分保留在溝槽中。
參考圖13，在第一SAC硬遮罩107a和ILD 101的部分上形成光阻905，從而使得暴露出第二金屬閘極的至少一部分。在圖14中，去除第二金屬閘極中的第一SAC硬遮罩107a。
圖15至圖17示出了在金屬閘極上形成第二SAC硬遮罩的操作。在圖15中，去除光阻905。在圖16中，形成第二SAC硬遮罩107b以毯式覆蓋金屬閘極和ILD 101。如圖17所示，去除過量的第二SAC硬遮罩107b並且僅部分保留在第二金屬閘極的溝槽中。
由於第一SAC硬掩107a和第二硬遮罩107b分別形成，因此可以獨立地控制每個硬遮罩的性能。器件設計者可以首先決定需要什麼類型的應力來提高每個器件的性能，然後確定採用用於相應的金屬閘極的什麼類型的SAC硬遮罩。換句話說，合適的SAC硬遮罩用作應力提供件並且可以根據設計者的偏好選擇性地施加在金屬閘極上。
例如，在一些實施例中，使用PECVD(等離子體增強化學氣相沉積)製程以形成第一SAC硬遮罩107a。PECVD製程可以具有介於200瓦至3000瓦範圍內的RF功率以形成氮化矽膜，從而將拉伸應力引入到第一金屬閘極下方的通道區。對於第二SAC硬遮罩107b，使用HDP(高密度等離子體)製程以形成膜，從而將壓縮應力引入到第二金屬閘極下方的通道區。
對於一些實施例，可以擴展SAC硬遮罩以覆蓋金屬閘極的更多的區域。如圖18所示，將SAC硬遮罩設計為覆蓋間隔件1035a和1035b的一部分。在金屬閘極上的增大的覆蓋度提供了引入至金屬閘極下方的通道區內的更大的應力。
為了用SAC硬遮罩覆蓋間隔件1035a和1035b的部分，利用如圖10所示的類似的操作以形成暴露間隔件1035a和1035b的部分的 溝槽。由此，形成如圖18中所示的擴展的SAC硬遮罩以覆蓋間隔件1035a和1035b。
也可以調整在圖10中形成的溝槽(203a和203b)以在不同的金屬閘極之間具有不同深度，以在其間形成具有不同縱向高度的SAC硬遮罩。例如，如圖19所示，第一SAC硬掩107a大於第二SAC硬遮罩107b。在一些實施例中，可以通過SAC硬遮罩的縱向高度調整引入金屬閘極下方的通道區內的應力。
另一種實現第一和第二金屬閘極的不同的縱向高度的可選方法可以通過如圖16至圖17中的CMP操作實現，並且選擇性地蝕刻期望的金屬閘極。因此，如圖20所示，選擇的金屬閘極比未選擇的金屬閘極具有更低的縱向高度。
另一種調整金屬閘極下方的不同通道區的應力的方法是改變SAC硬遮罩的形狀。如圖21所示，對於一些實施例，SAC硬遮罩107a和107b分別形成為不同的形狀。具有橫向較長下部的SAC硬遮罩可以將拉伸應力引入到金屬閘極下方的通道區，如圖21中所示的第一SAC硬遮罩107a。具有橫向較長上部的SAC硬遮罩可以將壓縮應力引入到金屬閘極下方的通道區，如圖21中所示的第二SAC硬遮罩107b。
為了實現兩個SAC硬遮罩的不同形狀，在圖10所示的操作期間，可以設計不同的橫向側壁蝕刻以在不同的步驟中去除間隔件1035a和1035b，從而在閘極之間具有不同的溝槽形狀。因此，隨後的SAC硬遮罩可以形成為閘極之間的不同的形狀。
如圖22所示，對於一些實施例，第一金屬閘極凹槽203a和第二金屬閘極凹槽203b(在圖22未示出)均具有較長的上部並且使得隨後形成的金屬閘極和SAC硬遮罩擁有橫向上部。在一些情況下，具有如圖22所示的錐形形狀的SAC硬遮罩具有引入到金屬閘極下方的通道區的壓縮應力。
如圖23所示，在一些實施例中，形成接點209a和209b以暴露源極/汲極區1011a和1011b。用於蝕刻ILD 101以暴露源極/汲極區1011a和1011b的蝕刻劑在SAC硬遮罩和ILD 101之間具有蝕刻選擇性。在一些實施例中，SAC硬遮罩包括氮化物並且ILD 101包括氧化物。
在一些實施例中，源極/汲極區1011a和1011b具有突出部分。
在一些實施例中，突出的源極/汲極區1011a和1011b的至少一個是磊晶層。
而且，本申請的範圍並不僅限於本說明書中描述的製程、機器、製造、材料組分、裝置、方法和步驟的特定實施例。作為本領域普通技術人員根據本揭露應很容易理解，根據本揭露可以利用現有的或今後開發的用於執行與本文所述相應實施例基本上相同的功能或者獲得基本上相同的結果的製程、機器、製造、材料組分、裝置、方法或步驟。
因此，所附權利要求預期將這樣的製程、機器、製造、材料組分、裝置、方法或步驟包括在其範圍內。此外，每條權利要求構成單獨的實施例，並且多個權利要求和實施例的組合在本揭露的範圍內。

Claims (10)

  1. 一種半導體結構，包括：半導體基板，包括第一表面和第二表面；層間電介質(ILD)，具有位於所述半導體基板的所述第一表面上方的第一凹槽和位於所述半導體基板的所述第二表面上方的第二凹槽；第一間隔件和第二間隔件，所述第一間隔件襯於所述第一凹槽的側壁上，所述第二間隔件襯於所述第二凹槽的側壁上；第一高k介電層和第二高k介電層，所述第一高k介電層接觸所述第一凹槽的底部和所述第一間隔件的側壁，所述第二高k介電層接觸所述第二凹槽的底部和所述第二間隔件的側壁；第一金屬和第二金屬，所述第一金屬接觸所述第一高k介電層的底部和側壁，所述第二金屬接觸所述第二高k介電層的底部和側壁；其中，所述第一金屬和第二金屬用於彼此不同導電類型的半導體；第一SAC(自對準接觸)硬遮罩和第二SAC硬遮罩，所述第一SAC硬遮罩位於所述第一金屬上，所述第二SAC硬遮罩位於所述第二金屬上；以及該第一SAC硬遮罩所具有的特徵性能為引入一拉伸應力至該第一金屬下的一N型通道區，及該第二SAC硬遮罩所具有的特徵性能為引入一壓縮應力至該第二金屬下的一P型通道區。
  2. 根據權利要求1所述的半導體結構，其中，所述第一SAC硬遮罩位於所述第一金屬和所述第一間隔件上。
  3. 根據權利要求1所述的半導體結構，其中，所述第二SAC硬遮罩位於所述第二金屬和所述第二間隔件上。
  4. 根據權利要求1所述的半導體結構，其中，所述第一SAC硬遮罩或所述第二SAC硬遮罩包括氮化物。
  5. 根據權利要求1所述的半導體結構，其中，所述第一SAC硬遮罩的縱向高度和所述第二SAC硬遮罩的縱向高度基本上彼此不同。
  6. 根據權利要求1所述的半導體結構，其中，所述第一金屬的縱向高度和所述第二金屬的縱向高度不同。
  7. 根據權利要求1所述的半導體結構，其中，所述第一SAC硬遮罩具有上部和下部，所述第一SAC硬遮罩的所述上部和所述下部的橫向長度不同。
  8. 根據權利要求1所述的半導體結構，其中，所述第二SAC硬遮罩具有上部和下部，所述第二SAC硬遮罩的所述上部和所述下部的橫向長度不同。
  9. 一種半導體結構，包括：半導體基板，包括表面；層間電介質(ILD)，具有位於所述半導體基板的所述表面上方的凹槽；第一間隔件，襯於所述凹槽的側壁上；源極/汲極區，位於所述半導體基板中，鄰近所述凹槽下方的通道區；高k介電層，接觸所述凹槽的底部和所述第一間隔件的側壁；金屬，接觸所述高k介電層的底部和側壁；以及SAC硬遮罩，位於所述金屬上，其中，所述SAC硬遮罩具有上部和下部，並且所述SAC硬遮罩的所述上部和所述下部的橫向長度不同，具有能對該通道區引入一應力的特徵性能。
  10. 一種製造半導體結構的方法，包括：在層間電介質(ILD)中形成第一凹槽和第二凹槽；形成襯於所述第一凹槽的側壁上的第一間隔件和襯於所述第二凹槽的側壁上的第二間隔件；形成接觸所述第一凹槽的底部和所述第一間隔件的側壁的第一高k介電層；形成接觸所述第一高k介電層的底部和側壁的第一金屬；形成接觸所述第二凹槽的底部和所述第二間隔件的側壁的第二高k介電層；形成接觸所述第二高k介電層的底部和側壁的第二金屬；以及在所述第一金屬上形成第一SAC硬遮罩；移除該第二金屬上的該第一SAC硬遮罩；和在所述第二金屬上形成第二SAC硬遮罩，其中該第一SAC硬遮罩和該第二SAC硬遮罩具有特徵性能，能對該第一金屬和該第二金屬底下的通道區域引入相反的應力。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269917B2 (en) 2016-10-19 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls
US9876010B1 (en) * 2016-11-03 2018-01-23 Globalfoundries Inc. Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure
CN108258033B (zh) * 2016-12-29 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
TWI726128B (zh) * 2017-07-17 2021-05-01 聯華電子股份有限公司 半導體元件及其製作方法
US10269803B2 (en) * 2017-08-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid scheme for improved performance for P-type and N-type FinFETs
US10957543B2 (en) * 2017-09-29 2021-03-23 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method of dielectric layer
US10475788B2 (en) * 2017-11-24 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with capping layer and method for forming the same
KR102392845B1 (ko) 2017-11-28 2022-04-29 삼성전자주식회사 반도체 장치
US10804378B2 (en) * 2017-11-29 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device fabrication with improved epitaxial source/drain proximity control
US11462436B2 (en) * 2017-11-30 2022-10-04 Intel Corporation Continuous gate and fin spacer for advanced integrated circuit structure fabrication
US10347540B1 (en) * 2017-12-14 2019-07-09 International Business Machines Corporation Gate cut using selective deposition to prevent oxide loss
US10692778B2 (en) 2018-08-01 2020-06-23 International Business Machines Corporation Gate-all-around FETs having uniform threshold voltage
US11024550B2 (en) * 2018-08-16 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201118952A (en) * 2009-11-19 2011-06-01 Taiwan Semiconductor Mfg A method for fabricating a fin-like field effect transistor device
CN102386082A (zh) * 2010-08-31 2012-03-21 台湾积体电路制造股份有限公司 半导体元件的形成方法
US20120181630A1 (en) * 2011-01-14 2012-07-19 International Business Machines Corporation Replacement gate with reduced gate leakage current
US20130015525A1 (en) * 2011-07-11 2013-01-17 International Business Machines Corporation Cmos with dual raised source and drain for nmos and pmos
TW201421550A (zh) * 2012-11-30 2014-06-01 Globalfoundries Us Inc 製造具有低電阻金屬閘極結構之積體電路的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605511B1 (ko) 2004-09-21 2006-07-28 삼성전자주식회사 반도체 장치 내 적어도 하나의 금속 게이트 패턴의형성방법들
US7151023B1 (en) 2005-08-01 2006-12-19 International Business Machines Corporation Metal gate MOSFET by full semiconductor metal alloy conversion
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US9142462B2 (en) * 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US9023696B2 (en) * 2011-05-26 2015-05-05 Globalfoundries Inc. Method of forming contacts for devices with multiple stress liners
US9076889B2 (en) * 2011-09-26 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Replacement gate semiconductor device
US8507979B1 (en) 2012-07-31 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit with metal gate
US9257348B2 (en) * 2013-08-06 2016-02-09 Globalfoundries Inc. Methods of forming replacement gate structures for transistors and the resulting devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201118952A (en) * 2009-11-19 2011-06-01 Taiwan Semiconductor Mfg A method for fabricating a fin-like field effect transistor device
CN102386082A (zh) * 2010-08-31 2012-03-21 台湾积体电路制造股份有限公司 半导体元件的形成方法
US20120181630A1 (en) * 2011-01-14 2012-07-19 International Business Machines Corporation Replacement gate with reduced gate leakage current
US20130015525A1 (en) * 2011-07-11 2013-01-17 International Business Machines Corporation Cmos with dual raised source and drain for nmos and pmos
TW201421550A (zh) * 2012-11-30 2014-06-01 Globalfoundries Us Inc 製造具有低電阻金屬閘極結構之積體電路的方法

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