TW201725628A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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Publication number
TW201725628A
TW201725628A TW105100229A TW105100229A TW201725628A TW 201725628 A TW201725628 A TW 201725628A TW 105100229 A TW105100229 A TW 105100229A TW 105100229 A TW105100229 A TW 105100229A TW 201725628 A TW201725628 A TW 201725628A
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Taiwan
Prior art keywords
layer
shallow trench
epitaxial layer
trench isolation
fin structure
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TW105100229A
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English (en)
Inventor
洪慶文
劉盈成
吳家榮
李怡慧
黃志森
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聯華電子股份有限公司
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Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW105100229A priority Critical patent/TW201725628A/zh
Priority to US15/008,462 priority patent/US20170194212A1/en
Priority to CN201610065037.1A priority patent/CN106952955A/zh
Publication of TW201725628A publication Critical patent/TW201725628A/zh

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一鰭狀結構以及一第二鰭狀結構於基底上，形成一第一磊晶層於第一鰭狀結構上以及一第二磊晶層於第二鰭狀結構上，接著形成一遮蓋層於第一磊晶層及第二磊晶層上，其中第一磊晶層及第二磊晶層之間之一距離係介於遮蓋層厚度的二倍至遮蓋層厚度的四倍。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，由指一種形成接觸洞時於磊晶層與淺溝隔離之間留下遮蓋層的方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行的鰭狀場效電晶體元件製程中，鰭狀結構與後續磊晶層的搭配仍存在許多瓶頸，進而影響整個元件的漏電流及整體電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，然後形成一第一鰭狀結構以及一第二鰭狀結構於基底上，形成一第一磊晶層於第一鰭狀結構上以及一第二磊晶層於第二鰭狀結構上，接著形成一遮蓋層於第一磊晶層及第二磊晶層上，其中第一磊晶層及第二磊晶層之間之一距離係介於遮蓋層厚度的二倍至遮蓋層厚度的四倍。
本發明另一實施例揭露一種半導體元件，其包含：一基底，一鰭狀結構設於基底上，一淺溝隔離設於基底上並環繞鰭狀結構，一磊晶層設於鰭狀結構上以及一遮蓋層設於磊晶層及淺溝隔離之間。
請參照第1圖至第7圖，第1圖至第7圖為本發明較佳實施例製作一半導體元件之方法示意圖，其中第2圖為第1圖中虛線部分之立體示意圖，第2圖至第3圖為本發明製作半導體元件之立體示意圖，第4圖至第6圖為第3圖中沿著切線AA'之剖面示意圖，第6圖又為第7圖中沿著切線BB’之剖面示意圖。如第1圖至第2圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一NMOS電晶體區或PMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離16，且部分的鰭狀結構14上另分別設有複數個虛置閘極或閘極結構18。需注意的是，為了凸顯鰭狀結構與閘極結構的設置位置與結構態樣，第2圖僅繪示單一閘極結構橫跨單一鰭狀結構的實施例。
鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing, CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之淺溝隔離(圖未示)。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一淺溝隔離以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構，故可省略前述製作淺溝隔離的步驟。
閘極結構18之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先於鰭狀結構14上形成一較佳包含介質層20與多晶矽材料22所構成的閘極結構18，然後於閘極結構18側壁形成側壁子24。在本實施例中，側壁子24可為一單一側壁子或複合式側壁子，其可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。
接著可先去除部分鰭狀結構14，再利用磊晶成長製程形成一磊晶層26於閘極結構18兩側的鰭狀結構14上，其中磊晶層26可包含鍺化矽(SiGe)、碳化矽(SiC)或磷化矽(SiP)等，但不侷限於此，端視所製作電晶體的型式與元件特性需求而定。值得注意的是，本實施例中成長於鰭狀結構14上的各磊晶層26呈現約略菱形，且各磊晶層26較佳包含一倒V型上表面28以及一V型下表面30。
如第3圖與第4圖所示，隨後形成一遮蓋層32於磊晶層26上，其中遮蓋層32較佳為一接觸洞蝕刻停止層(contact etch stop layer, CESL)，其可具有應力，且較佳選自由SiN、SiCN以及SiCON所構成的群組。另外在本實施例中，磊晶層26之間之一距離係介於遮蓋層32厚度的二倍至遮蓋層厚度的四倍。
接著形成一介電層34或層間介電層於遮蓋層32、淺溝隔離16與鰭狀結構14上，並進行一平坦化製程，例如利用CMP去除部分介電層34與部分遮蓋層32以暴露出由多晶矽材料22所構成的閘極電極，使閘極電極上表面與介電層34上表面齊平。其中介電層34可由任何包含氧化物之絕緣材料所構成，例如本實施例之介電層34較佳包含一由可流動式化學氣相沉積(FCVD)所形成的氧化層、一由高密度電漿(high-density plasma, HDP)沉積製程所形成的氧化層以及一四乙氧基矽烷(Tetraethyl orthosilicate, TEOS)所構成的氧化層，但不侷限於此。
隨後進行一金屬閘極置換製程將閘極結構18轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構18中的多晶矽材料22，以於介電層34中形成複數個凹槽(圖未示)。
之後依序形成一高介電常數介電層36以及至少包含U型功函數金屬層38與低阻抗金屬層40的導電層於各凹槽內，並再搭配進行一平坦化製程使U型高介電常數介電層36、U型功函數金屬層38與低阻抗金屬層40的表面與介電層34表面齊平。
在本實施例中，高介電常數介電層36包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2 O3 )、氧化鑭(lanthanum oxide，La2 O3 )、氧化鉭(tantalum oxide，Ta2 O5 )、氧化釔(yttrium oxide，Y2 O3 )、氧化鋯(zirconium oxide，ZrO2 )、鈦酸鍶（strontium titanate oxide， SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide，HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate , PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層38較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層38可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層38可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層38與低阻抗金屬層40之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層40則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。接著可選擇性去除部分高介電常數介電層36、部分功函數金屬層38與部分低阻抗金屬層40形成凹槽(圖未示)，然後再填入一硬遮罩(圖未示)於凹槽內並使硬遮罩與介電層34表面齊平，其中硬遮罩可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。
接著進行一接觸插塞製程搭配金屬矽化物製程形成一金屬矽化物於磊晶層26表面以及一接觸插塞電連接閘極結構18兩側的源極/汲極區域與磊晶層26。首先，如第5圖所示，可利用圖案化遮罩(圖未示)進行一蝕刻製程，例如較佳利用一非等向性或乾蝕刻製程去除閘極結構18之間的部分介電層34以形成接觸洞42暴露磊晶層26表面與部分淺溝隔離16。需注意的是，本實施例形成接觸洞42時較佳不去除所有的介電層34與遮蓋層32，並使部分遮蓋層32與部分介電層34殘留於磊晶層26V型下表面30與淺溝隔離16之間。
更具體而言，殘留於磊晶層26V型下表面30與淺溝隔離16之間的遮蓋層32較佳為V型，且所殘留遮蓋層32的V型較佳與磊晶層26的V型下表面30呈90度。此外所殘留的遮蓋層32較佳與所殘留的介電層34一同切齊磊晶層26倒V型上表面28與V型下表面30的交界處。
如第6圖所示，然後依序沉積一第一金屬層44與第二金屬層46於接觸洞42中，其中第一金屬層44與第二金屬層46較佳共形地(conformally)形成於磊晶層26表面及接觸洞42的內側側壁。在本實施例中，第一金屬層44較佳選自鈦、鈷、鎳及鉑等所構成的群組，且最佳為鈦，而第二金屬層46則較佳包含氮化鈦、氮化鉭等金屬化合物。
在連續沉積第一金屬層44與第二金屬層46之後，依序進行一第一熱處理製程與一第二熱處理製程以形成一金屬矽化物48於磊晶層26上。在本實施例中，第一熱處理製程包含一常溫退火(soak anneal)製程，其溫度較佳介於500℃至600℃，且最佳為550℃，而其處理時間則較佳介於10秒至60秒，且最佳為30秒。第二熱處理製程包含一峰值退火(spike anneal)製程，其溫度較佳介於600℃至950℃，且最佳為600℃，而其處理較佳時間則較佳介於100毫秒至5秒，且最佳為5秒。
迨進行兩次熱處理製程後，形成一第三金屬層50並填滿接觸洞42。在本實施例中，第三金屬層50較佳包含鎢，但不侷限於此。最後進行一平坦化製程，例如以CMP製程去除部分第三金屬層50、部分第二金屬層46及部分第一金屬層44，甚至可視製程需求接著去除部分介電層34，以形成接觸插塞52電連接磊晶層26。至此即完成本發明較佳實施例一半導體元件的製作。
請再參照第6圖，第6圖另揭露本發明較佳實施例之一半導體元件結構。如第6圖所示，半導體元件主要包含一基底12、至少一鰭狀結構14設於基底12上、一淺溝隔離16設於基底12上並環繞鰭狀結構14、一磊晶層26設於各鰭狀結構14上、一遮蓋層32與介電層34設於磊晶層26與淺溝隔離16之間、以及一接觸插塞52設於磊晶層26上並接觸淺溝隔離16、遮蓋層32與介電層34。
更具體而言，各磊晶層26包含一倒V型上表面28以及一V型下表面30，遮蓋層32與介電層34是設於V型下表面30與淺溝隔離16之間，其中介電層34直接接觸遮蓋層32並較佳與遮蓋層32一同切齊磊晶層26倒V型上表面28與V型下表面30的交界處，遮蓋層32較佳為V型且與磊晶層26的V型下表面30呈現約90度。
從更細部來看，接觸插塞52包含第一金屬層44、第二金屬層46與第三金屬層50，接觸插塞52較佳同時接觸淺溝隔離16、設於磊晶層26V型下表面30與淺溝隔離16之間的遮蓋層32以及設於磊晶層26V型下表面30與淺溝隔離16之間的介電層34。另外本實施例之遮蓋層32較佳為一接觸洞蝕刻停止層，其可具有應力且較佳選自由SiN、SiCN以及SiCON所構成的群組。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧淺溝隔離
18‧‧‧閘極結構
20‧‧‧介質層
22‧‧‧多晶矽材料
24‧‧‧側壁子
26‧‧‧磊晶層
28‧‧‧倒V型上表面
30‧‧‧V型下表面
32‧‧‧遮蓋層
34‧‧‧介電層
36‧‧‧高介電常數介電層
38‧‧‧功函數金屬層
40‧‧‧低阻抗金屬層
42‧‧‧接觸洞
44‧‧‧第一金屬層
46‧‧‧第二金屬層
48‧‧‧金屬矽化物
50‧‧‧第三金屬層
52‧‧‧接觸插塞
第1圖為本發明較佳實施例製作一半導體元件之上視圖。 第2圖至第3圖為本發明製作一半導體元件之立體示意圖。 第4圖至第6圖為第3圖中沿著切線AA'之剖面示意圖。 第7圖為本發明較佳實施例製作一半導體元件之上視圖。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧淺溝隔離
26‧‧‧磊晶層
28‧‧‧倒V型上表面
30‧‧‧V型下表面
32‧‧‧遮蓋層
34‧‧‧介電層
44‧‧‧第一金屬層
46‧‧‧第二金屬層
48‧‧‧金屬矽化物
50‧‧‧第三金屬層
52‧‧‧接觸插塞

Claims (17)

  1. 一種製作半導體元件的方法，包含：      提供一基底；      形成一第一鰭狀結構以及一第二鰭狀結構於該基底上；      形成一第一磊晶層於該第一鰭狀結構上以及一第二磊晶層於該第二鰭狀結構上；以及      形成一遮蓋層於該第一磊晶層及該第二磊晶層上，其中該第一磊晶層及該第二磊晶層之間之一距離係介於該遮蓋層厚度的二倍至該遮蓋層厚度的四倍。
  2. 如申請專利範圍第1項所述之方法，另包含：      形成一淺溝隔離於該基底上並環繞該第一鰭狀結構及該第二鰭狀結構；      形成該第一磊晶層於該第一鰭狀結構上以及該第二磊晶層於該第二鰭狀結構上；以及      形成該遮蓋層於該第一磊晶層、該第二磊晶層及該淺溝隔離上。
  3. 如申請專利範圍第2項所述之方法，其中該第一磊晶層包含一倒V型上表面以及一V型下表面。
  4. 如申請專利範圍第3項所述之方法，另包含：      形成一介電層於該第一磊晶層、該第二磊晶層及該淺溝隔離上；      去除部分該介電層以形成一接觸洞暴露該第一磊晶層、該第二磊晶層及部分該淺溝隔離並使部分該遮蓋層殘留於該V型下表面及該淺溝隔離之間。
  5. 如申請專利範圍第4項所述之方法，其中殘留於該V型下表面及該淺溝隔離之間之該遮蓋層係為V型。
  6. 如申請專利範圍第4項所述之方法，另包含形成一接觸插塞於該接觸洞內，其中該接觸插塞接觸該淺溝隔離及設於該V型下表面及該淺溝隔離之間之該遮蓋層。
  7. 如申請專利範圍第4項所述之方法，另包含使剩餘之該介電層設於該V型下表面及該淺溝隔離之間。
  8. 如申請專利範圍第7項所述之方法，另包含形成一接觸插塞於該接觸洞內，其中該接觸插塞接觸該淺溝隔離及設於該V型下表面及該淺溝隔離之間之該介電層。
  9. 一種半導體元件，包含：      一基底；      一鰭狀結構設於該基底上；      一淺溝隔離設於該基底上並環繞該鰭狀結構；      一磊晶層設於該鰭狀結構上；以及      一遮蓋層設於該磊晶層及該淺溝隔離之間。
  10. 如申請專利範圍第9項所述之半導體元件，其中該磊晶層包含一倒V型上表面以及一V型下表面。
  11. 如申請專利範圍第10項所述之半導體元件，其中該遮蓋層是設於該V型下表面及該淺溝隔離之間。
  12. 如申請專利範圍第11項所述之半導體元件，其中該遮蓋層係為V型。
  13. 如申請專利範圍第10項所述之半導體元件，另包含一介電層設於該V型下表面及該淺溝隔離之間。
  14. 如申請專利範圍第13項所述之半導體元件，其中該介電層接觸該遮蓋層。
  15. 如申請專利範圍第13項所述之半導體元件，另包含一接觸插塞設於該磊晶層上並接觸該淺溝隔離及設於該V型下表面及該淺溝隔離之間之該介電層。
  16. 如申請專利範圍第10項所述之半導體元件，另包含一接觸插塞設於該磊晶層上並接觸該淺溝隔離及設於該V型下表面及該淺溝隔離之間之該遮蓋層。
  17. 如申請專利範圍第9項所述之半導體元件，其中該遮蓋層是選自由SiN、SiCN以及SiCON所構成的群組。
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US11271083B2 (en) * 2019-09-27 2022-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, FinFET device and methods of forming the same
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