WO2015054915A1 - 一种非对称超薄soimos晶体管结构及其制造方法 - Google Patents

一种非对称超薄soimos晶体管结构及其制造方法 Download PDF

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Publication number
WO2015054915A1
WO2015054915A1 PCT/CN2013/085541 CN2013085541W WO2015054915A1 WO 2015054915 A1 WO2015054915 A1 WO 2015054915A1 CN 2013085541 W CN2013085541 W CN 2013085541W WO 2015054915 A1 WO2015054915 A1 WO 2015054915A1
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vacancy
semiconductor layer
layer
gate
source
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PCT/CN2013/085541
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French (fr)
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尹海洲
张珂珂
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中国科学院微电子研究所
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Priority to US14/904,711 priority Critical patent/US20160155844A1/en
Publication of WO2015054915A1 publication Critical patent/WO2015054915A1/zh

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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66568—Lateral single gate silicon transistors
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Definitions

  • Asymmetric ultra-thin SOIMOS transistor structure and manufacturing method thereof Asymmetric ultra-thin SOIMOS transistor structure and manufacturing method thereof
  • the present invention relates to a semiconductor device structure and a method of fabricating the same, and, in particular, to an asymmetric ultra-thin SOIMOS transistor structure and a method of fabricating the same.
  • SOI Silicon On Insulator
  • SOI technology is recognized as one of the mainstream semiconductor technologies of the 21st century.
  • SOI technology effectively overcomes the shortcomings of bulk silicon materials, fully exploits the potential of silicon integrated circuit technology, and is gradually becoming the mainstream technology for manufacturing high-speed, low-power, high-integration and high-reliability ultra-large-scale integrated circuits.
  • the channel portion in order to enhance the gate-to-channel control ability and better suppress the short channel effect, it is desirable that the channel portion be as narrow as possible.
  • the channel thickness is less than 10 nm, since the carrier mobility decreases as the channel thickness decreases, the device performance is more severely affected.
  • the channel portion near the source end is particularly affected. Severe, and at the drain end, the effect of channel width on mobility has no major effect due to the effect of high field saturation.
  • Drain Induction Barrier Lower is a non-ideal effect in short-channel devices, that is, when the channel length is reduced, the source-drain voltage is increased to make the source and drain regions PN
  • the power line in the channel can pass from the drain region to the source region, and the source barrier height is lowered, so that the number of carriers injected into the channel from the source region is increased, and the drain current is increased.
  • the influence of the DIBL becomes more and more serious, the transistor threshold voltage is lowered, the device voltage gain is lowered, and the integration of the VLSI is also limited.
  • the present invention provides an asymmetric ultra-thin SOIMOS transistor structure and a fabrication method thereof, the channel region of which is close to the source
  • the thickness of the end portion is 1 to 3 times the thickness of the portion near the drain end
  • the length of the thin channel portion is 1 to 3 times the length of the thick channel portion. That is to say, near the source end, the influence of the channel width on the mobility is mainly considered, and the channel width is large; and in the vicinity of the drain end, since the channel width has little effect on the carrier mobility, In order to reduce the influence of DIBL, the channel width is small.
  • the present invention effectively suppresses the adverse effects of the short channel effect and improves the device performance. Summary of the invention
  • the present invention provides an asymmetric ultra-thin SOIMOS transistor structure and a fabrication method thereof, which effectively suppresses the short channel effect of the device and improves device performance.
  • the method for manufacturing an asymmetric ultra-thin SOIMOS transistor provided by the present invention includes:
  • step c wherein, in step c, the length of the first vacancy is equal to the length of the source region on the semiconductor layer, and the thickness of the first vacancy is equal to the thickness of the semiconductor layer.
  • step c wherein, in the step c, the method of removing the semiconductor layer on the side of the source region on the semiconductor layer to form the first vacancy is anisotropic etching.
  • step d the thickness of the second vacancy is 1 to 3 times the thickness of the semiconductor layer.
  • the length of the second vacancy extending below the gate stack is about 1/4 ⁇ 2/3 of the length of the gate stack.
  • the method of removing the insulating material under the source region and the channel near the source region to form the second vacancy is a directional etching.
  • the method of filling the semiconductor layer at the first vacancy and the second vacancy is selective epitaxial growth.
  • step b wherein, in step b, the following steps may be used instead: g. forming a gate dielectric layer on the substrate, forming a dummy gate structure on the gate dielectric layer; h. two in the dummy gate structure The source and drain extension regions are formed on the side.
  • the method may further include the steps of: i. thickening the semiconductor layer on one side of the drain region until the top of the drain region is flush with the top of the source region.
  • the method may further include the steps of: removing the dummy gate structure to form dummy gate vacancies; k. depositing a gate stack in the dummy gate vacancies.
  • the present invention provides an asymmetric ultra-thin SOIMOS transistor structure, including: an insulating layer;
  • Source and drain regions located in the bottom of both sides of the gate stack
  • the thickness of the channel region near the source end portion is 1 to 3 times the thickness of the portion near the drain end.
  • the asymmetric ultra-thin SOIMOS transistor structure has a large width at a position near the source end of the channel portion, which reduces the influence of the channel width on the mobility; and the width near the drain end is small,
  • the effect of DIBL is effectively reduced without affecting the carrier mobility.
  • the invention effectively suppresses the adverse effect of the short channel effect and improves the device property.
  • 1 to 7 are cross-sectional views showing respective stages of fabrication of the ultrathin SOI device in accordance with an embodiment of the present invention.
  • the present invention provides an asymmetric ultra-thin SOIMOS transistor structure, comprising: an insulating layer 200; a semiconductor layer 300 above the insulating layer 200; a gate above the semiconductor layer 300. a dielectric layer 301; a gate stack 304 over the gate dielectric layer 301; a channel region under the gate stack 304; a source located in the bottom of the gate stack 304 a drain region; and an interlayer dielectric layer covering the gate stack 304 and the source and drain regions; wherein a thickness of the channel region near the source end portion is 1 to 3 times a thickness near the drain end portion.
  • the length of the thick channel portion is 1/4 to 2/3 of the total length of the channel.
  • the substrate is formed by a substrate layer 100, an insulating layer 200, and a semiconductor layer 300 by SOI fabrication techniques, which may be oxygen injection isolation techniques, laser recrystallization techniques, bonding techniques, and/or hydrogen injection smarts. Stripping technology, etc.
  • the base layer 100 is not necessary, that is, only the insulating layer 200 and the semiconductor layer 300 may constitute the SOI substrate.
  • the insulating layer 200 is an oxide layer formed on the underlying layer 100, and is preferably silicon dioxide having a thickness of 5 nm to 200 nm.
  • the semiconductor layer 300 is preferably a thin single crystal silicon layer or a single crystal silicon germanium alloy having a thickness of 5 to 20 nm, such as 8 nm, 10 nm, or the like.
  • the gate dielectric layer 301 is preferably made of silicon oxynitride or silicon oxide or a high K material. Its equivalent oxidation thickness is from 0.5 nm to 5 nm.
  • the gate structure includes a conductive gate stack 304 and a pair of insulating dielectric spacers 303 on either side of the gate stack 304.
  • the gate stack 304 may be only a metal gate or a metal/polysilicon composite gate with silicide on the upper surface of the polysilicon.
  • the semiconductor channel region is located on the surface of the insulating substrate 200.
  • the preferred material is a single crystal silicon or a single crystal germanium alloy film having a thickness of 5 to 20 nm. This region is extremely lightly doped or even undoped. In the case of doping, the doping type is opposite to that of the source and drain regions.
  • the source and drain regions are respectively located on both sides of the gate stack 304, within the semiconductor layer 300 above the insulating layer 200.
  • the thickness of the source region is greater than the thickness of the drain region.
  • the thickness of the channel portion on the side close to the source region is larger than the thickness of the channel on the side near the drain end, which is 10 nm to 60 nm.
  • the asymmetric ultra-thin SOIMOS transistor structure has a large width at a portion near the source end of the channel portion, which reduces the influence of the channel width on the mobility; and the width near the drain end is small,
  • the effect of DIBL is effectively reduced without affecting the carrier mobility.
  • the present invention effectively suppresses the adverse effects of the short channel effect and improves the device property.
  • the village floor used is SOI material.
  • the SOI material is made by bonding and back etching techniques. It consists of a base layer 100, a buried oxide layer 200, and a single crystal silicon film 300.
  • the thickness of the buried oxide layer is about 75 nm to 200 nm.
  • the single crystal silicon film 300 has an initial thickness of 5 to 20 nm, and if it is too thick, it can be thinned to a desired thickness by thermal oxidation and BOE etching techniques.
  • the substrate may also be an insulating material such as sapphire or glass.
  • a gate dielectric layer 301 is formed on the substrate.
  • the gate dielectric layer 301 may be a thermal oxide layer, including silicon oxide or silicon oxynitride; or a high-k dielectric such as HfA10N, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, A1 2 0 3 , One of La 2 O 3 , Zr0 2 , LaA10 or a combination thereof, the gate dielectric layer 301 may have a thickness of 1 nm to 10 nm. For example 3 nm, 5 nm or 8 nm.
  • the gate dielectric layer 301 can be formed by processes such as thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
  • a dummy gate structure 302 is formed on the gate dielectric layer.
  • the dummy gate structure 302 may be a single layer or a plurality of layers.
  • the dummy gate structure 302 may comprise a polymer material, amorphous silicon, polysilicon or TiN, and may have a thickness of 10 nm to 200 nm.
  • the dummy gate structure includes polysilicon and dioxide. Specifically, the polysilicon is filled in the gate vacancies by chemical vapor deposition, and the height is slightly lower than the sidewall 10-20 nm, and then a polysilicon is formed.
  • the layer of the silicon dioxide dielectric layer may be formed by epitaxial growth, oxidation, CVD or the like.
  • the gate electrode pattern is formed by photolithography and etching of the deposited dummy gate stack by a conventional CMOS process, and then the exposed portion of the gate dielectric layer 301 is etched away by using the gate electrode pattern as a mask. A portion of the semiconductor layer 300 covered by the gate dielectric layer forms a channel region of the transistor. It should be noted that, unless otherwise specified, the deposition of various dielectric materials in the embodiments of the present invention may be performed by the above-described method of forming a gate dielectric layer or the like, and thus will not be described again.
  • the village substrate 300 on both sides of the dummy gate structure 302 is shallowly doped to form a lightly doped source and drain region, and Halo implantation may be performed to form a Halo implantation region.
  • the shallow doping impurity type is the same as the device type, and the Halo implanted impurity type is opposite to the device type.
  • sidewall spacers 303 are formed on sidewalls of the gate stack for spacing the gates. Specifically, a silicon nitride spacer layer of a thickness of 40 nm to 80 nm is deposited by LPCVD, and then a silicon nitride spacer 303 having a width of 35 nm to 75 nm is formed on both sides of the gate electrode by a guest technique.
  • the sidewall spacers 303 may also be formed of silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 303 may have a multi-layered structure.
  • the spacer 303 may also be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • the semiconductor material on the side of the source region on the semiconductor layer 300 is removed to form a first vacancy 001.
  • the semiconductor layer 300 on the exposed source side is anisotropically etched by using a photoresist covering the gate dielectric layer and the semiconductor structure on the drain side, since the thickness of the semiconductor layer is 5 nm to 20 nm.
  • the etching method is generally dry etching. After the etching is completed, a first vacancy 001 is formed, the length of the first vacancy 001 is equal to the length of the source region on the semiconductor layer 300, and the thickness of the first vacancy 001 is equal to the thickness of the semiconductor layer 300.
  • the insulating material under the source region and the channel near the source region on the insulating layer 300 is removed to form a second vacancy 002.
  • the insulating layer 200 under the first vacancy 001 is isotropically etched until the desired second vacancy 002 is obtained.
  • the etching method is generally dry and/or wet etching.
  • the thickness of the second vacancy 002 is 1 ⁇ 3 times the thickness of the semiconductor layer 300, and the length of the second vacancy 002 extending below the gate stack 304 is about 1/4 ⁇ 2/3 of the length of the gate 302.
  • the semiconductor structure after the formation of the second vacancy 002 is as shown in FIG. 2.
  • the formed first vacancy 001 and second vacancy 002 are filled with a semiconductor material silicon or a silicon germanium alloy.
  • the filling method is a selective epitaxial method. Specifically, a mask is formed on a portion other than the source region of the semiconductor structure, and the mask may be silicon dioxide or silicon nitride, etc., so as to be located above the second vacancy 002 near the source region.
  • the channel portion on the side is a seed crystal, and single crystal silicon or single crystal germanium silicon is epitaxially grown until the source region reaches a desired thickness.
  • the mask is then removed.
  • hydrogen chloride can be used as the etching gas.
  • the thickness of the grown semiconductor layer is higher than the surface of the original first vacancy 001 before etching (ie, the bottom of the gate dielectric layer) of 20 nm to 100 nm.
  • the semiconductor layer 300 on one side of the drain region is subjected to a thickening process.
  • a preferred thickening method is a selective epitaxial method in which a semiconductor layer having a bit-drain region is used as a seed crystal, and single crystal silicon or single crystal germanium silicon is epitaxially grown until the thickness of the drain region is flush with the source region.
  • Another method that can be employed is conventional low pressure chemical deposition (LPCVD).
  • a silicon dioxide dielectric layer having a thickness of 10 nm to 35 nm is deposited, and the dielectric layer is used as a buffer layer, and ions are implanted into the source and drain regions.
  • the dopant is boron or boron fluoride or indium or gallium.
  • the dopant is scale or arsenic or antimony.
  • the doping concentration is 5el0 19 cm- 3 ⁇ lel0 2G cm- 3 .
  • the dummy gate structure 302 is removed to form dummy gate vacancies.
  • the removal of the dummy gate structure 302 can be removed by wet etching and/or dry etching. In one embodiment, plasma etching is employed.
  • the gate stack 304 is formed in the gate vacancies.
  • the gate stack 304 may be only a metal gate or a metal/polysilicon composite gate with a silicide on the upper surface of the polysilicon.
  • a work function metal layer is deposited on the gate dielectric layer 301, and then a metal conductor layer is formed on the work function metal layer.
  • the work function metal layer can be TiN, TaN, etc. Made of materials, the thickness ranges from 3 nm to 15 nm.
  • the metal conductor layer may be in a one-layer or multi-layer structure.
  • the material may be one of TaN, TaC, TiN, TaAlN, TiAlN, ⁇ 1 ⁇ , TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x or a combination thereof. Its thickness range is an example. It can be 1 Onm -40nm, such as 20nm or 3 Onm.
  • the conventional CMOS subsequent process including depositing a passivation layer, opening a contact hole, and metallization, etc., can be made to form the ultrathin SOI MOS transistor, as shown in FIG.

Abstract

本发明提供了一种非对称超薄SOIMOS晶体管的制造方法，包括：a. 提供由绝缘层（200）和半导体层（300）组成的衬底； b. 在所述衬底上形成栅极叠层（304）；c. 去除半导体层（300）上源区一侧的半导体材料，形成第一空位（001）；d. 去除绝缘层（200）上源区及靠近源区的沟道下方的绝缘材料，形成第二空位（002）；e. 在第一空位（001）和第二空位（002）处填充半导体材料，并与第二空位（002）上方的半导体材料相连；f.进行源漏区注入。与现有技术相比，本发明有效地抑制了短沟道效应的不良影响，提高了器件性能。

Description

一种非对称超薄 SOIMOS晶体管结构及其制造方法
[0001]本申请要求了 2013年 10月 14 日提交的、 申请号为 201310478396.6、 发明名称为 "一种非对称超薄 SOIMOS晶体管结构及其制造方法"的中国专 利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及一种半导体器件结构及其制造方法， 具体地， 涉及一种非 对称超薄 SOIMOS晶体管结构及其制造方法。 技术背景
[0003] SOI (Silicon On Insulator) 是指绝缘体上硅技术， SOI 技术是公认的 二十一世纪的主流半导体技术之一。 SOI 技术有效地克服了体硅材料的不 足， 充分发挥了硅集成电路技术的潜力， 正逐渐成为制造高速、 低功耗、 高 集成度和高可靠超大规模集成电路的主流技。
[0004】在 MOSFET结构中， 为了增强栅对沟道的控制能力， 更好的抑制短 沟道效应， 希望沟道部分越窄越好。 然而， 在沟道厚度小于 10nm以后， 由 于载流子迁移率随着沟道厚度的减小而降低， 器件性能会受到较严重的影 响， 特別地， 在靠近源端的沟道部分所受影响尤为严重， 而在漏端， 由于高 场饱和作用的影响， 沟道宽度对迁移率的影响不起主要作用。
[0005]漏端感应势垒降低效应（Drain Induction Barrier Lower)是短沟道器件 中存在的一种非理想效应， 即当沟道长度减小， 源漏电压增加而使得源区和 漏区 PN结耗尽区靠近时， 沟道中的电力线可以从漏区穿越到源区， 并导致 源端势垒高度降低，从而使源区注入沟道的载流子数目增加，漏端电流增大。 随着沟道长度的进一步减小， DIBL的影响越来越严重， 使晶体管阔值电压 降低， 器件电压增益下降， 同时也限制了超大规模集成电路集成度的提高。 为了降低 DIBL的影响， 希望沟道宽度， 尤其是靠近漏端的沟道宽度越窄越 好。 [0006]因此， 为了平衡沟道宽度对载流子迁移率和 DIBL效应的影响， 优化 器件性能， 本发明提供了一种非对称超薄 SOIMOS晶体管结构及其制作方 法， 其沟道区靠近源端部分的厚度是靠近漏端部分的厚度的 1至 3倍， 且其 薄沟道部分的长度是厚沟道部分的长度的 1至 3倍。 也就是说， 在靠近源端 的地方， 主要考虑沟道宽度对迁移率的影响， 沟道宽度较大； 而在靠近漏端 的地方， 由于沟道宽度对载流子迁移率的影响不大， 因此为了降低 DIBL的 影响， 沟道宽度较小。 与现有技术相比， 本发明有效地抑制了短沟道效应的 不良影响， 提高了器件性能。 发明内容
[0007]本发明提供了一种非对称超薄 SOIMOS晶体管结构及其制作方法，有 效抑制了器件的短沟道效应， 提高了器件性能。 具体地， 本发明提供的一种 非对称超薄 SOIMOS晶体管的制造方法， 包括：
a. 提供由绝缘层和半导体层组成的村底；
b. 在所述村底上形成栅极叠层；
c 去除半导体层上源区一侧的半导体材料， 形成第一空位；
d. 去除绝缘层上源区及靠近源区的沟道下方的绝缘材料，形成第二空位； e. 在第一空位和第二空位处填充半导体材料， 并与第二空位上方的半导 体材料相连；
f. 进行源漏区注入。
[0008]其中，在步骤 c中，所述第一空位的长度等于半导体层上源区的长度， 所述第一空位的厚度等于半导体层的厚度。
[0009】其中， 在步骤 c中， 所述去除半导体层上源区一侧的半导体层， 形成 第一空位的方法是各向异性刻蚀。
[0010】其中， 在步骤 d中， 所述第二空位的厚度为半导体层厚度的 1~3倍。
[0011】其中， 在步骤 d中， 所述第二空位延伸至栅极叠层下方的长度约为栅 极叠层长度的 1/4~2/3。 [0012】其中， 在步骤 d中， 所述去除绝缘层上源区及靠近源区的沟道下方的 绝缘材料， 形成第二空位的方法是各向 1§]性刻蚀。
[0013】其中， 在步骤 e中， 所述在第一空位和第二空位处填充半导体层的方 法是选择性外延生长。
[0014]其中， 在所述步骤 b可用以下步骤代替： g. 在所述村底上形成栅极介 质层，在所述栅极介质层上形成伪栅结构； h. 在伪栅结构的两侧形成源漏扩 展区。
[0015】其中， 在所述步骤 f之后还可包括步骤： i. 对漏区一侧的半导体层进 行加厚， 直至漏区顶部与源区顶部平齐。
[0016】其中， 在所述步骤 f之后还可包括步骤： j . 去除所述伪栅结构， 形成 伪栅空位； k. 在伪栅空位中淀积栅极叠层。
[0017】相应的， 本发明提供了一种非对称超薄 SOIMOS晶体管结构， 包括： 绝缘层；
位于所述绝缘层上方的半导体层；
位于所述半导体层上方的栅极介质层；
位于所述栅极介质层上方的栅极叠层；
位于所述栅极叠层下方的沟道区；
位于所述栅极叠层两侧村底中的源漏区；
以及覆盖栅极叠层和源漏区的层间介质层；
其中， 所述沟道区靠近源端部分的厚度是靠近漏端部分的厚度的 1至 3 倍。
[0018]根据本发明提供的非对称超薄 SOIMOS晶体管结构，在沟道部分靠近 源端的位置宽度较大， 降低了沟道宽度对迁移率的影响； 而在靠近漏端的地 方宽度较小， 在不影响载流子迁移率的情况下， 有效降低 DIBL的影响。 与 现有技术相比， 本发明有效地抑制了短沟道效应的不良影响， 提高了器件性 月匕 o 附图说明
[0019]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
图 1〜图 7为根据本发明的一个具体实施方式中该超薄 SOI器件各个制 造阶段的剖面图。
附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0020】为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0021】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明， 而不能解释为对本发明的限制。
[0022]如图 7所示， 本发明提供了一种非对称超薄 SOIMOS晶体管结构， 包 括： 绝缘层 200 ; 位于所述绝缘层 200上方的半导体层 300 ; 位于所述半导 体层 300上方的栅极介质层 301； 位于所述栅极介质层 301上方的栅极叠层 304 ; 位于所述栅极叠层 304下方的沟道区； 位于所述栅极叠层 304两侧村 底中的源漏区； 以及覆盖栅极叠层 304和源漏区的层间介质层； 其中， 所述 沟道区靠近源端部分的厚度是靠近漏端部分的厚度的 1至 3倍。所述厚沟道 部分的长度是沟道总长度的 1/4~2/3。
[0023]该村底由基体层 100、绝缘层 200和半导体层 300通过 SOI 制造技术 形成， 所述 SOI制造技术可以是注氧隔离技术、 激光再结晶技术、 键合技术 和 /或注氢智能剥离技术等。基底层 100非必须， 即， 仅绝缘层 200和半导体 层 300也可构成所述 SOI村底。绝缘层 200是形成于基底层 100之上的氧化 层， 首选是二氧化硅， 其厚度为 5nm~200nm。 半导体层 300首选是一薄的 单晶硅层， 也可以是单晶的锗硅合金， 其厚度为 5~20nm，如 8nm、 10nm等。 [0024]栅介质层 301优选材料为氮氧化硅， 也可为氧化硅或高 K材料。其等 效氧化厚度为 0.5nm~5nm。
[0025]栅结构包括导电的栅极叠层 304和一对位于该栅极叠层 304两侧的绝 缘介质侧墙 303。 栅极叠层 304可以只为金属栅极， 也可以为金属 /多晶硅复 合栅极， 其中多晶硅上表面上具有硅化物。
[0026]半导体沟道区位于绝缘村底 200的表面， 其优选材料为单晶硅或单晶 锗合金薄膜， 其厚度为 5~20nm。 该区域是极轻摻杂甚至未摻杂的。 在摻杂 的情况下， 其摻杂类型与源漏区摻杂相反。
[0027]源区和漏区分別位于栅极叠层 304两侧， 绝缘层 200上方的半导体层 300内。 源区的厚度大于漏区的厚度。 靠近源区一侧的沟道部分厚度大于靠 近漏端一侧的沟道厚度， 为 10nm~60nm。
[0028]根据本发明提供的非对称超薄 SOIMOS晶体管结构，在沟道部分靠近 源端的地方宽度较大， 降低了沟道宽度对迁移率的影响； 而在靠近漏端的地 方宽度较小， 在不影响载流子迁移率的情况下， 有效降低 DIBL的影响。 与 现有技术相比， 本发明有效地抑制了短沟道效应的不良影响， 提高了器件性 月匕。
[0029】下面结合附图对本发明的制作方法进行详细说明， 包括以下步骤。 需 要说明的是， 本发明各个实施例的附图仅是为了示意的目的， 因此没有必要 按比例绘制。
[0030]首先提供村底。 所用村底为 SOI材料。 该 SOI材料由键合和背面腐 蚀技术制成。 由基底层 100、 隐埋氧化层 200和单晶硅膜 300组成。 隐埋氧 化层厚度约为 75nm~200nm。 单晶硅膜 300起始厚度为 5~20nm， 如果过厚， 可由热氧化和 BOE腐蚀技术减薄至所需厚度。 基底也可以是蓝宝石或玻璃 等绝缘材料。
[0031]在所述村底上形成栅极介质层 301。 所述栅极介质层 301可以是热氧 化层， 包括氧化硅、 氮氧化硅；也可为高 K介质， 例如 HfA10N、 HfSiAlON, HfTaAlON, HfTiAlON, HfON、 HfSiON、 HfTaON、 HfTiON、 A1203、 La203、 Zr02、 LaA10中的一种或其组合，栅极介质层 301的厚度可以为 lnm-10nm， 例如 3nm、 5nm或 8nm。 可以采用热氧化、 化学气相沉积 （CVD) 或原子层 沉积 （ALD) 等工艺来形成栅极介质层 301。
[0032】接下来， 在所述栅极介质层上形成伪栅结构 302。 所述伪栅结构 302 可以是单层的， 也可以是多层的。 伪栅结构 302可以包括聚合物材料、 非晶 硅、 多晶硅或 TiN， 厚度可以为 10nm~200nm。 本实施例中， 伪栅结构包括 多晶硅和二氧化， 具体的， 采用化学汽相淀积的方法在栅极空位中填充多晶 硅， 其高度略低于侧墙 10~20nm， 接着在多晶硅上方形成一层二氧化硅介质 层， 形成方法可以是外延生长、 氧化、 CVD等。 接着采用常规 CMOS工艺 光刻和刻蚀所淀积的伪栅叠层形成栅电极图形， 然后以栅电极图形为掩膜腐 蚀掉栅极介质层 301的棵露部分。半导体层 300中被栅极介质层所覆盖的部 分形成晶体管的沟道区。 需说明地是， 以下若无特別说明， 本发明实施例中 各种介质材料的淀积均可采用上述所列举的形成栅介质层相 1¾或类似的方 法， 故不再赘述。
[0033]接下来， 对伪栅结构 302两侧的村底 300进行浅摻杂， 以形成轻摻杂 源漏区， 还可以进行 Halo注入， 以形成 Halo注入区。 其中浅摻杂的杂质类 型与器件类型一致， Halo注入的杂质类型与器件类型相反。
[0034】可选地， 在栅极堆叠的侧壁上形成侧墙 303， 用于将栅极隔开。 具体 的， 用 LPCVD淀积 40nm~80nm厚的牺牲侧墙介质层氮化硅， 接着用会客 技术在栅电极两侧形成宽度为 35nm~75nm的氮化硅侧墙 303。 侧墙 303还 可以由氧化硅、 氮氧化硅、碳化硅及其组合， 和 /或其他合适的材料形成。侧 墙 303可以具有多层结构。 侧墙 303还可以通过包括沉积刻蚀工艺形成， 其 厚度范围可以是 10nm -lOOnm, 如 30nm、 50nm或 80nm。
[0035】接下来， 去除半导体层 300上源区一侧的半导体材料， 形成第一空位 001。 具体的， 利用光刻胶覆盖栅极介质层以及漏端一侧的半导体结构， 对 暴露出的源端一侧的半导体层 300进行各向异性刻蚀， 由于半导体层厚度为 5nm~20nm， 刻蚀方法一般为干法刻蚀。 刻蚀完成之后形成第一空位 001， 所述第一空位 001的长度等于半导体层 300上源区的长度，所述第一空位 001 的厚度等于半导体层 300的厚度。 [0036]接下来， 去除绝缘层 300上源区及靠近源区的沟道下方的绝缘材料， 形成第二空位 002。 具体的， 对第一空位 001下方的绝缘层 200进行各向同 性刻蚀， 直至得到所需第二空位 002。 刻蚀方法一般为干法和 /或湿法刻蚀。 所述第二空位 002的厚度为半导体层 300厚度的 1~3倍， 所述第二空位 002 延伸至栅极叠层 304下方的长度约为栅极 302长度的 1/4~2/3。第二空位 002 形成之后的半导体结构图如图 2所示。
[0037】接下来， 如图 3所示， 用半导体材料硅或者锗硅合金填充所形成的第 一空位 001和第二空位 002。 填充方法是选择性外延法， 具体的， 在半导体 结构源区以外的部分上形成掩膜， 所述掩膜可以是二氧化硅或氮化硅等， 以 位于第二空位 002上方靠近源区一侧的沟道部分为籽晶， 外延生长单晶硅或 单晶锗硅， 直至源区达到所需厚度。 之后去除掩膜。 其中， 刻蚀气体可选用 氯化氢。为了减小源区的寄生电阻，生长的半导体层厚度高于原第一空位 001 被刻蚀前的表面 （即栅极介质层底部） 20nm~100nm。
[0038】同样的， 如图 4所示， 为了减小漏区的寄生电阻， 对漏区的一侧的半 导体层 300进行加厚处理。 优选的加厚方法是是选择性外延法， 即， 以位漏 区的半导体层为籽晶， 外延生长单晶硅或单晶锗硅， 直至漏区厚度与源区平 齐。 另一可以采用的方法是常规低压化学淀积法 （LPCVD) 。
[0039]源漏区半导体材料形成后， 淀积一层厚度为 10nm~35nm厚的二氧化 硅介质层， 并以该介质层为緩冲层， 离子注入源漏区。 对 P型晶体而言， 摻 杂剂为硼或氟化硼或铟或镓等。 对 N型晶体而言， 摻杂剂为鱗或砷或銻等。 摻杂浓度为 5el019cm-3~lel02G cm-3。完成摻杂之后的半导体结构如图 5所示。
[0040】接下来， 去除所述伪栅结构 302， 形成伪栅空位。 去除伪栅结构 302 可以采用湿刻和 /或干刻除去。 在一个实施例中， 采用等离子体刻蚀。
[0041]接下来，如图 6所示，在栅极空位中形成栅极叠层 304。 栅极叠层 304 可以只为金属栅极，也可以为金属 /多晶硅复合栅极， 其中多晶硅上表面上具 有硅化物。
[0042】具体的， 优选的， 在栅极介质层 301上先沉积功函数金属层， 之后再 在功函数金属层之上形成金属导体层。 功函数金属层可以采用 TiN、 TaN等 材料制成， 其厚度范围为 3nm~15nm。金属导体层可以为一层或者多层结构。 其材料可以为 TaN、 TaC、 TiN、 TaAlN、 TiAlN、 ΜοΑ1Ν、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax中的一种或其组合。 其厚度 范围例 。可以为 1 Onm -40nm， 如 20nm或 3 Onm。
[0043]最后进入常规 CMOS后续工艺， 包括淀积钝化层、开接触孔以及金属 化等， 即可制成所述超薄 SOI MOS晶体管， 如图 7所示。
[0044] 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0045]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发 明可以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种非对称超薄 SOIMOS晶体管的制造方法， 包括：
a.提供由绝缘层 （200) 和半导体层 （300) 组成的村底；
b. 在所述村底上形成栅极叠层 （304) ；
c 去除半导体层 (300)上源区一侧的半导体材料， 形成第一空位 (001) ; d. 去除绝缘层 (200)上源区及靠近源区的沟道下方的绝缘材料， 形成第 二空位 (；002 )；
e. 在第一空位 (001)和第二空位 (002)处填充半导体材料， 并与第二空位 (002)上方的半导体材料相连；
f.进行源漏区注入。
2、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 c中， 所述第一 空位（001 )的长度等于半导体层（300)上源区的长度， 所述第一空位（001 ) 的厚度等于半导体层 （300) 的厚度。
3、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 c中， 所述去除 半导体层 （300) 上源区一侧的半导体层， 形成第一空位 （001 ) 的方法是各 向异性刻蚀。
4、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 d中， 所述第二 空位 （002) 的厚度为半导体层 （300) 厚度的 1~3倍。
5、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 d中， 所述第二 空位 （002) 延伸至栅极叠层 （304) 下方的长度约为栅极叠层 （304) 长度 的 1/4~2/3。
6、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 d中， 所述去除 绝缘层（200)上源区及靠近源区的沟道下方的绝缘材料，形成第二空位（002 ) 的方法是各向同性刻蚀。
7、 根据权利要求 1所述的制造方法， 其特征在于， 在步骤 e中， 所述在第 一空位 （001 ) 和第二空位 （002) 处填充半导体层 （300) 的方法是选择性 外延生长。
8、 根据权利要求 1所述的制造方法， 其特征在于， 在所述步骤 b可用以下 步骤代替：
g. 在所述村底上形成栅极介质层 （301 ) ， 在所述栅极介质层 （301 ) 上形成伪栅结构 （302) ；
h. 在伪栅结构 （302) 的两侧形成源漏扩展区。
9、 根据权利要求 1所述的制造方法， 其特征在于， 在所述步骤 f之后还可 包括步骤：
i. 对漏区一侧的半导体层 (300)进行加厚， 直至漏区顶部与源区顶部平 齐。
10、 根据权利要求 8所述的制造方法， 其特征在于， 在所述步骤 f之后还可 包括步骤：
j. 去除所述伪栅结构 （302)， 形成伪栅空位；
k. 在伪栅空位中淀积栅极叠层 (304)。
11、 一种非对称超薄 SOIMOS晶体管结构， 包括：
绝缘层 (200) ；
位于所述绝缘层 （200) 上方的半导体层 （300) ；
位于所述半导体层 （300) 上方的栅极介质层 （301 ) ；
位于所述栅极介质层 （301 ) 上方的栅极叠层 （304) ；
位于所述栅极叠层 （304) 下方的沟道区；
位于所述栅极叠层 （304) 两侧村底中的源漏区；
以及覆盖栅极叠层 （304) 和源漏区的层间介质层；
其中， 所述沟道区靠近源端部分的厚度是靠近漏端部分的厚度的 1至 3 倍。
12、根据权利要求 11所述的非对称超薄 SOIMOS晶体管结构，其特征在于， 所述厚沟道部分的长度是沟道总长度的 1/4~2/3。
PCT/CN2013/085541 2013-10-14 2013-10-21 一种非对称超薄soimos晶体管结构及其制造方法 WO2015054915A1 (zh)

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
US9876110B2 (en) * 2014-01-31 2018-01-23 Stmicroelectronics, Inc. High dose implantation for ultrathin semiconductor-on-insulator substrates
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121093A (en) * 1998-09-30 2000-09-19 Intel Corporation Method of making asymmetrical transistor structures
US20080073669A1 (en) * 2005-10-26 2008-03-27 International Business Machines Corporation Structure and method for manufacturing high performance and low leakeage field effect transistor
CN101740613A (zh) * 2008-11-12 2010-06-16 海力士半导体有限公司 用于防止或减小短沟道效应的晶体管及其制造方法
CN102569391A (zh) * 2010-12-24 2012-07-11 中国科学院微电子研究所 Mos晶体管及其制作方法
CN103189985A (zh) * 2010-11-04 2013-07-03 国际商业机器公司 不对称异质结构fet及制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
US6372559B1 (en) * 2000-11-09 2002-04-16 International Business Machines Corporation Method for self-aligned vertical double-gate MOSFET
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6919238B2 (en) * 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121093A (en) * 1998-09-30 2000-09-19 Intel Corporation Method of making asymmetrical transistor structures
US20080073669A1 (en) * 2005-10-26 2008-03-27 International Business Machines Corporation Structure and method for manufacturing high performance and low leakeage field effect transistor
CN101740613A (zh) * 2008-11-12 2010-06-16 海力士半导体有限公司 用于防止或减小短沟道效应的晶体管及其制造方法
CN103189985A (zh) * 2010-11-04 2013-07-03 国际商业机器公司 不对称异质结构fet及制造方法
CN102569391A (zh) * 2010-12-24 2012-07-11 中国科学院微电子研究所 Mos晶体管及其制作方法

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