WO2013159416A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2013159416A1
WO2013159416A1 PCT/CN2012/075913 CN2012075913W WO2013159416A1 WO 2013159416 A1 WO2013159416 A1 WO 2013159416A1 CN 2012075913 W CN2012075913 W CN 2012075913W WO 2013159416 A1 WO2013159416 A1 WO 2013159416A1
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Prior art keywords
buried
layer
contact plug
type
doping
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PCT/CN2012/075913
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English (en)
French (fr)
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尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Priority to US14/397,586 priority Critical patent/US9548317B2/en
Publication of WO2013159416A1 publication Critical patent/WO2013159416A1/zh

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    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • Fully depleted silicon-on-insulator (FDSOI) devices have the characteristics of short channel control, good subthreshold characteristics, low leakage, and small random fluctuations. It is considered to be a replacement for the traditional body at 32 nm and below. A preferred structure for a silicon device.
  • Fully depleted silicon-on-insulator devices generally with an ultra-thin silicon film (50nm) SOI structure, reducing the thickness of the buried oxide layer BOX (50nm) can further improve device performance, reduce the effects of self-heating effects, fringe fields, etc. .
  • the Ultra-Thin Body and BOX (UTBB) SOI device can increase the back-gate regulation by introducing a formation on the back side of the ultra-thin buried oxide layer, thereby reducing the source/drain area electric field coupling and increasing the threshold value. Voltage control has broad application prospects in low power applications. However, the back gate electrode extraction and the corresponding wiring inevitably increase the circuit area and increase the cost. Therefore, for UTBB SOI devices, how to trade off between device performance and cost becomes an important issue to be solved. Summary of the invention
  • the present invention is directed to at least solving the above technical drawbacks, and provides a manufacturer of a semiconductor device.
  • the method and its structure electrically connect the buried stratum to the source region, and it is not necessary to separately extract the buried stratum, thereby saving the device area.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising the steps of:
  • a village bottom which includes a base layer, a buried isolation layer, a buried formation, an ultra-thin insulating buried layer, and a surface active layer from bottom to top;
  • Another aspect of the present invention also provides a semiconductor structure including a substrate, a gate stack, a sidewall, a source region, a drain region, and a buried formation contact plug, wherein:
  • the bottom of the village includes a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer, and a surface active layer in order from bottom to top;
  • the gate stack is located on a surface active layer of the village bottom
  • the sidewall spacer is located on a sidewall of the gate stack
  • the source and drain regions are located on both sides of the gate stack and are embedded in the surface active layer of the village bottom;
  • the buried formation contact plug is connected to the source region, located at a side of the source region away from the gate stack, and penetrates the surface active layer and the ultra-thin insulating buried layer of the village bottom, and The buried formations are connected.
  • the present invention has the following advantages:
  • the buried ground layer is electrically connected to the source region, which enhances the ability of the semiconductor device to control the threshold voltage, reduces the short channel effect, improves device performance, and does not have to be separate for the buried layer. Leading out, saving the device area and tubeizing the process.
  • FIG. 1 is a flow chart of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to 12 are schematic cross-sectional views of the semiconductor structure at various stages of fabrication in the process of fabricating a semiconductor structure in accordance with the method illustrated in FIG. 1. detailed description
  • first and second features are formed in direct contact
  • additional features formed between the first and second features. Embodiments such that the first and second features may not be in direct contact.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIGS. 2 through 12 are schematic cross-sectional views showing stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with an embodiment of the present invention.
  • the method of forming the semiconductor structure of Fig. 1 will be specifically described below with reference to Figs. 2 through 12. It is to be understood that the drawings of the embodiments of the present invention are for the purpose of illustration
  • a village bottom 100 is provided.
  • the bottom 100 includes a base layer 101, a buried isolation layer 102, a buried ground layer 103, and an ultra-thin insulation buried in order from bottom to top.
  • the substrate used in the present invention is an ultra-thin body and BOX (UTBB) SOI structure.
  • the base layer 101 provides mechanical support for the layers located thereon.
  • the base layer 101 is single crystal silicon.
  • the base layer 101 may also include other basic semiconductors such as germanium, or other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the base layer 101 can be, but is not limited to, a few hundred meters, such as a thickness ranging from 0.1 mm to 1 mm.
  • the material of the buried isolation layer 102 and the ultra-thin insulating buried layer 104 is SiO 2 , silicon nitride, A1 2 0 3 or any other suitable insulating material, typically, the buried isolation layer 102
  • the thickness ranges from 50 nm to 300 nm, and the thickness of the ultra-thin insulating buried layer 104 ranges from 5 nm to 50 nm.
  • the material of the buried formation 103 and the surface active layer 105 is silicon, germanium or other compound semiconductor, for example, silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Buried formation
  • the thickness of 103 is 5 nm to 30 nm, and the thickness of the surface active layer 105 is 5 nm to 50 nm.
  • step S101 further comprising forming an isolation region, such as a shallow trench isolation (STI) structure 120, in the substrate 100 to electrically isolate the continuous semiconductor device, as shown in FIG.
  • the shallow trench isolation (STI) structure 120 penetrates the buried ground layer 103, the ultra-thin insulating buried layer 104, and the surface active layer 105, and is in contact with the buried isolation layer 102.
  • step S102 is performed to perform ion implantation doping on the buried ground layer 103.
  • a photoresist 130 is coated on the substrate to expose and develop the photoresist.
  • Ion implantation is then performed using the photoresist 130 as a mask.
  • the concentration of the ion implantation is peaked in the buried formation 103, and the surface active layer 105 is not damaged.
  • an annealing treatment is performed to obtain a heavily doped buried formation 103.
  • the doping concentration of the buried ground layer 103 can be designed according to the threshold voltage of the device, and the range is 10 18 ⁇ 10 2Q cm - 3 .
  • the doping type of the buried ground layer is N type;
  • the doping type of the buried formation is P type.
  • step S103 is performed to form a gate stack, a sidewall spacer 230, a drain region 310, and a source region 320 on the substrate 100.
  • a gate stack is formed on the substrate, and the gate stack package A gate dielectric layer 210 and a gate 220 are included.
  • the gate stack may further include a capping layer (not shown) over the gate, such as by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof. Formed to protect the top region of the gate 220 from damage during subsequent processing.
  • the gate dielectric layer 210 is located on the surface active layer 105 of the substrate 100, and may be a high-k dielectric, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , One of Zr0 2 , LaAlO or a combination thereof. In another embodiment, it may also be a thermal oxide layer including silicon oxide or silicon oxynitride; the gate dielectric layer 210 may have a thickness of 1 nm to 10 nm, such as 5 nm or 8 nm.
  • a gate 220 is formed on the gate dielectric layer 210, and the gate 220 may be heavily doped polysilicon formed by deposition, or a shape success function metal layer (for NMOS, such as TaC, TiN, TaTbN, TaErN) , TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , etc., for PMOS, such as MoN x , TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuO x ), which may have a thickness of 1 nm to 20 nm, a port of 3 nm, 5 nm, 8 nm, 10 nm, 12 nm or 15 nm, and further forms heavily doped polysilicon, Ti, Co, Ni, Al, W on the work function metal layer
  • the gate electrode 220 is formed by
  • the gate stack includes a gate 220 (in this case, a dummy gate) and a gate dielectric carrying the gate.
  • Layer 210 Forming a gate 220 on the gate dielectric layer 210 by depositing, for example, polysilicon, polycrystalline SiGe, amorphous silicon, doped or undoped silicon oxide and silicon nitride, silicon oxynitride, silicon carbide, or even metal The time is a dummy gate), and the thickness thereof may be 10 nm to 80 nm.
  • the method further includes forming a capping layer on the gate 220 (in this case, a dummy gate), for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof to protect the dummy gate.
  • the top region of the pole 220 prevents the top region of the gate 220 (which is now a dummy gate) from reacting with the deposited metal layer in a subsequent process of forming a contact layer.
  • the gate stack may also be devoid of the gate dielectric layer 210, but in a subsequent process step, after removing the dummy gate, a gate dielectric layer 210 is formed prior to filling the work function metal layer.
  • drain region 310 and source region 320 can be P-type doped Si; for NMOS, drain region 310 and source region 320 can be N-doped Si.
  • the semiconductor structure Annealing is performed to activate the impurities in the drain region 310 and the source region 320, and the annealing may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the drain region 310 and the source region 320 may also be formed after forming the sidewall spacer 230, and after forming the gate stack, the source/drain extension region is formed in a low energy injection manner (not shown in the figure) .
  • the sidewall spacers 230 are formed on sidewalls of the gate stack for spacing the gate stacks apart.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • the sidewall spacer 230 may be formed by a deposition-etching process including a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • step S104 is performed to form a mask layer 400 covering the gate stack and the source/drain regions on the substrate 100, and the mask layer 400 is etched to expose The source region 320.
  • the material of the mask layer 400 is silicon oxide, silicon nitride or silicon oxynitride, which is formed on the substrate by a suitable method such as chemical vapor deposition or sputtering.
  • a photoresist 410 covering the mask layer 400 is formed first, and the photoresist 410 is exposed and developed to be patterned, and the mask layer 400 is etched to expose the source region 320. .
  • step S105 is performed to etch the source region 320 and the ultra-thin insulating buried layer 104 under the source region 320 to form an opening 500 exposing the buried layer 103, and removing the photoresist. 410.
  • the source region 320 and the ultra-thin insulating buried layer 104 are separately etched by dry etching RIE or wet etching to form the opening 500.
  • step S106 is performed to fill the opening 500 by epitaxy to form the contact plug 510 of the buried formation 103.
  • the buried layer 103 at the bottom of the opening 500 is a seed layer, and epitaxial growth is performed to form a contact plug 510.
  • the material of the buried formation contact plug 510 may be Si, Ge, SiGe, SiC.
  • the method further includes doping the buried formation contact plug 510 by in-situ doping or ion implantation during the epitaxial process.
  • the buried formation contact plug has a doping concentration of 10 18 ⁇ 10 2 Q cm - 3 , and has the same doping type as the buried formation 103 and the source region 320 .
  • the doping type of the buried formation contact plug is N-type; for the PMOS, the doping type of the buried formation contact plug is P-type.
  • 12 is a cross-sectional view of the semiconductor structure after the mask layer 400 is removed. It can be seen that the buried formation contact plug 510 is connected to the source region 320 at a side of the source region 320 away from the gate stack. And The surface active layer 105 and the ultra-thin insulating buried layer 104 of the village bottom 100 are connected to the buried ground layer 103.
  • a metal silicide on the source/drain regions; depositing an interlayer dielectric layer to cover the source/drain regions and the gate stack; Etching the interlayer dielectric layer exposes source/drain regions to form contact holes, filling the contact holes with metal; and subsequent multilayer metal interconnects and the like.
  • the dummy gate is removed, and a metal gate or the like is formed.
  • the present invention also provides a semiconductor structure, as shown in FIG. 12, including a substrate 100, a gate stack, a sidewall spacer 230, a drain region 310, a source region 320, and a buried formation contact plug 510.
  • the bottom 100 includes a base layer 101, a buried isolation layer 102, a buried ground layer 103, an ultra-thin insulating buried layer 104, and a surface active layer 105 in order from the bottom to the top, and is an ultra-thin ultra-thin buried oxide layer (Ultra-Thin Body and BOX, UTBB) SOI structure;
  • the gate stack is located on the surface active layer 105 of the substrate 100;
  • the sidewall spacer 230 is located on the sidewall of the gate stack;
  • the source region 320 and the drain A region 310 is located on both sides of the gate stack and embedded in the surface active layer 105 of the substrate 100;
  • the buried formation contact plug 510 is connected to the source region 320, and is
  • One side of the gate stack is connected to the buried ground layer 103 through the surface active layer 105 and the ultra-thin insulating buried layer 103 of the substrate 100.
  • the thickness of the buried ground layer 103 is 5 nm to 30 nm
  • the thickness of the ultra-thin insulating buried layer 104 is 5 nm to 50 nm
  • the thickness of the surface active layer 105 is 5 nm to 50 nm.
  • the buried ground layer 103, the buried ground contact plug 510, and the source region 320 have the same doping type.
  • the doping type is N-type
  • for the PMOS the doping type is P-type.
  • the material of the buried formation contact plug 510 is Si, Ge, SiGe, SiC, and the stress of the channel region of the semiconductor structure can be further adjusted by selecting a suitable material to improve the current driving capability.
  • the buried formation 103 serves as a back gate to control the threshold voltage of the semiconductor structure to improve device performance.
  • the buried formation 103 is electrically connected to the source region 320 by the buried formation contact plug 510, so that the potential of the buried formation 103 is kept as constant as possible, and it is not necessary to separately use the buried formation 103 as a lead-out and wiring, thereby saving device area and cost.

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Abstract

提供一种半导体结构的制造方法及一种半导体结构。该方法包括以下步骤：提供衬底（100），所述衬底（100）从下至上依次包括基底层（101）、掩埋隔离层（102）、掩埋地层（103）、超薄绝缘埋层（104）、表面有源层（105）；对所述掩埋地层（103）进行离子注入掺杂；在所述衬底（100）上形成栅极堆叠、侧墙（230）、源区（320）和漏区（310）；在所述衬底（100）上形成覆盖所述栅极堆叠、源区（320）和漏区（310）的掩膜层（400），刻蚀所述掩膜层（400）以暴露出所述源区（320）；刻蚀所述源区（320）以及源区（320）之下的超薄绝缘埋层（104），形成暴露出所述掩埋地层（103）的开口（500）；通过外延填充所述开口（500），以形成所述掩埋地层（103）的接触塞（510）。本发明通过形成掩埋地层（103）接触塞（510），将掩埋地层（103）与源区（320）电学连接，增强了半导体器件对阈值电压的控制能力，减小了短沟道效应，提高了器件性能，同时不必对掩埋地层（103）做单独引出，节省了器件面积，简化了工艺。

Description

一种半导体结构及其制造方法
[0001]本申请要求了 2012年 4月 28日提交的、 申请号为 201210134597.X、 发明名称为 "一种半导体结构及其制造方法" 的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造领域， 尤其涉及一种半导体结构及其制造方法。 背景技术
[0003]为了提高集成电路芯片的性能和集成度， 器件特征尺寸按照摩尔定 律不断缩小， 目前已经进入纳米尺度。 传统平面体硅 CMOS技术在集成度 提高的同时， 无法兼顾器件性能提高和功耗减小。 器件参数随机涨落以及 阈值电压无法按比例缩小等， 进一步限制了器件整体性能的提升。 在 45nm 及其以下技术节点， 短沟道效应的急剧增加也使得器件进一步按比例缩小 更为困难。
[0004]全耗尽绝缘体上硅（FDSOI ) 器件具有短沟道控制非常好、 亚阈值 特性好、 漏电少、 随机掺杂涨落影响小等特点， 被认为是 32nm及其以下 节点替代传统体硅器件的优选结构。 全耗尽绝缘体上硅器件， 一般具有超 薄硅膜（ 50nm ) 的 SOI结构， 减小埋氧层 BOX的厚度（ 50nm ) 可以 进一步提高器件的性能， 减小自加热效应、 边缘场等的影响。 此外这种超 薄体超薄埋氧层 （ Ultra-Thin Body and BOX, UTBB ) SOI器件， 通过在超 薄埋氧层背面引入地层增加背栅调控， 可以减小源 /漏区电场耦合， 增加对 阈值电压的控制， 在低功耗应用上具有广阔的应用前景。 但是， 背栅电极 引出和相应的布线， 不可避免地会增加电路面积， 增加成本。 因而对于 UTBB SOI 器件， 如何在器件性能和成本之间进行折中， 成为一个亟待解 决的重要问题。 发明内容
[0005]本发明旨在至少解决上述技术缺陷， 提供一种半导体器件的制造方 法及其结构， 将掩埋地层与源区电学连接， 不必对掩埋地层做单独引出， 节省器件面积。
[0006]为达上述目的， 本发明提供了一种半导体结构的制造方法， 该方法 包括以下步骤：
( a ) 提供村底， 所述村底从下至上依次包括基底层、 掩埋隔离层、 掩埋 地层、 超薄绝缘埋层、 表面有源层；
( b ) 对所述掩埋地层进行离子注入掺杂；
( c ) 在所述村底上形成栅极堆叠、 侧墙和源 /漏区；
( d ) 在所述村底上形成覆盖所述栅极堆叠和源 /漏区的掩膜层， 刻蚀所述 掩膜层以暴露出所述源区；
( e ) 刻蚀所述源区以及源区之下的超薄绝缘埋层， 形成暴露出所述掩埋 地层的开口；
( f ) 通过外延填充所述开口， 以形成所述掩埋地层的接触塞。
[0007]本发明另一方面还提出一种半导体结构， 包括村底、 栅极堆叠、 侧 墙、 源区、 漏区、 掩埋地层接触塞， 其中：
[0008]所述村底从下至上依次包括基底层、 掩埋隔离层、 掩埋地层、 超薄 绝缘埋层、 表面有源层；
[0009]所述栅极堆叠位于所述村底的表面有源层之上；
[0010]所述侧墙位于所述栅极堆叠的侧壁上；
[0011]所述源区和漏区位于所述栅极堆叠的两侧并嵌于所述村底的表面有 源层中；
[0012]所述掩埋地层接触塞与所述源区相连， 位于所述源区远离所述栅极 堆叠的一侧， 并贯穿所述村底的表面有源层和超薄绝缘埋层， 与所述掩埋 地层相连。
[0013]与现有技术相比， 本发明具有如下优点：
[0014]通过形成掩埋地层接触塞， 将掩埋地层与源区电学连接， 增强了半 导体器件对阈值电压的控制能力， 减小了短沟道效应， 提高了器件性能， 同时不必对掩埋地层做单独引出， 节省了器件面积， 筒化了工艺。 附图说明
[0015]本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 其中：
[0016]图 1 是根据本发明的半导体结构的制造方法的一个具体实施方式的 流程图；
[0017]图 2至图 12为根据图 1示出的方法制造半导体结构过程中该半导体结 构在各个制造阶段的剖面结构示意图。 具体实施方式
[0018]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似 功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本 发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同的实施 例或例子用来实现本发明的不同结构。 为了筒化本发明的公开， 下文中对 特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在 于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论各种实施例和 /或 设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应用于性和 /或其他材 料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包 括第一和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成 在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
[0019]图 1为根据本发明的半导体结构制造方法的流程图， 图 2至图 12为根 据本发明的一个实施例按照图 1 所示流程制造半导体结构的各个阶段的剖面 示意图。 下面将结合图 2至图 12对图 1中形成半导体结构的方法进行具体地 描述。 需要说明的是， 本发明实施例的附图仅是为了示意的目的， 因此没 有必要按比例绘制。
[0020]参考图 1和图 2, 在步骤 S101 中， 提供村底 100, 所述村底 100从 下至上依次包括基底层 101、 掩埋隔离层 102、 掩埋地层 103、 超薄绝缘埋 层 104、 表面有源层 105。
[0021]本发明中采用的村底为超薄体超薄埋氧层 ( Ultra- Thin Body and BOX, UTBB ) SOI结构。所述基底层 101为位于其上的各层提供机械支撑。 在本实施例中， 所述基底层 101 为单晶硅。 在其他实施例中， 所述基底层 101 还可以包括其他基本半导体例如锗， 或其他化合物半导体， 例如， 碳 化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 所述基底层 101 的厚度可以 约为但不限于几百 米， 例如 0.1mm- lmm的厚度范围。
[0022]所述掩埋隔离层 102和所述超薄绝缘埋层 104的材料为 Si02、 氮化 硅、 A1203或者其他任何合适的绝缘材料， 典型地， 所述掩埋隔离层 102的 厚度范围为 50nm~300nm,所述超薄绝缘埋层 104的厚度范围为 5nm~50nm。
[0023]所述掩埋地层 103和所述表面有源层 105的材料为硅、 锗或其他化 合物半导体， 例如， 碳化硅、 砷化镓、 砷化铟或者磷化铟。 所述掩埋地层
103的厚度为 5nm~30nm, 所述表面有源层 105的厚度为 5nm~50nm。
[0024]特别地， 在步骤 S101中， 还包括在所述村底 100中形成隔离区， 例 如浅沟槽隔离（STI)结构 120, 以便电隔离连续的半导体器件， 如图 3所示， 所述浅沟槽隔离（STI)结构 120贯穿所述掩埋地层 103、 超薄绝缘埋层 104、 表面有源层 105 , 与所述掩埋隔离层 102相接。
[0025]参考图 1和图 4, 执行步骤 S102, 对所述掩埋地层 103进行离子注 入掺杂。 具体地， 在所述村底上覆盖一层光刻胶 130, 对所述光刻胶进行 曝光显影。 然后以光刻胶 130为掩膜， 进行离子注入。 通过调整离子注入 的粒子能量、 电压、 注入剂量等参数， 使得离子注入的浓度峰值在所述掩 埋地层 103中， 并对所述表面有源层 105不会造成损伤。 随后， 进行退火 处理， 得到重掺杂的掩埋地层 103。 所述掩埋地层 103 的掺杂浓度可以根 据器件阈值电压的要求进行设计， 其范围为 1018 ~ 102Qcm-3, 对于 NMOS , 所述掩埋地层的掺杂类型为 N型； 对于 PMOS , 所述掩埋地层的掺杂类型 为 P型。
[0026]随后， 执行步骤 S103 , 在所述村底 100上形成栅极堆叠、 侧墙 230、 漏区 310和源区 320。
[0027]首先， 如图 5 所示， 在所述村底上形成栅极堆叠， 所述栅极堆叠包 括栅介质层 210和栅极 220。 可选地， 所述栅极堆叠还可以包括覆盖在所 述栅极上的覆盖层 （未在图中示出） ， 例如通过沉积氮化硅、 氧化硅、 氮 氧化硅、 碳化硅及其组合形成， 用以保护栅极 220的顶部区域， 防止其在 后续的工艺中受到破坏。所述栅介质层 210位于村底 100的表面有源层 105 之上， 可以为高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO、 A1203、 La203、 Zr02、 LaAlO中的一种或其组合。 在另一个实施例 中， 还可以是热氧化层， 包括氧化硅、 氮氧化硅； 所述栅极介质层 210的 厚度可以为 lnm~10nm, 如 5nm或 8nm。 而后在所述栅介质层 210上形成 栅极 220, 所述栅极 220可以是通过沉积形成的重掺杂多晶硅， 或是先形成 功函数金属层（对于 NMOS, 例如 TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax等， 对于 PMOS , 例如 MoNx, TiSiN, TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ),其厚度可以为 lnm-20nm, ^口 3nm、 5nm、 8nm、 10nm、 12nm或 15nm, 再在所述功函数金属层上形成重 掺杂多晶硅、 Ti、 Co、 Ni、 Al、 W或其合金等而形成栅极 220。
[0028]在本发明的另外一些实施例中， 也可采用后栅工艺 （gate last ), 此 时，栅极堆叠包括栅极 220 (此时为伪栅）和承载所述栅极的栅介质层 210。 在所述栅介质层 210上通过沉积例如多晶硅、 多晶 SiGe、 非晶硅， 掺杂或 未掺杂的氧化硅及氮化硅、 氮氧化硅、 碳化硅， 甚至金属形成栅极 220 (此 时为伪栅）， 其厚度可以为 10nm~80nm。 可选地， 还包括在所述栅极 220 (此时为伪栅）上形成覆盖层， 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护伪栅极 220的顶部区域， 防止栅极 220 (此 时为伪栅） 的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反 应。 在另一个采用后栅工艺实施例中， 栅极堆叠也可以没有栅介质层 210, 而是后续工艺步骤中， 除去所述伪栅后， 在填充功函数金属层之前形成栅 介质层 210。
[0029]随后， 如图 6所示， 以所述栅极堆叠为掩膜， 向表面有源层 105 中 注入 P型或 N型杂质，进而在所述栅极堆叠两侧形成漏区 310和源区 320。 对于 PMOS来说， 漏区 310和源区 320可以是 P型掺杂的 Si; 对于 NMOS 来说， 漏区 310和源区 320可以是 N型掺杂的 Si。 然后对所述半导体结构 进行退火， 以激活漏区 310和源区 320中的杂质， 退火可以采用包括快速 退火、 尖峰退火等其他合适的方法形成。 可选地， 所述漏区 310和源区 320 也可以在形成侧墙 230之后形成， 而在形成栅极堆叠之后， 以低能注入的 方式形成源 /漏延伸区 （未在图中画出）。
[0030]如图 7所示， 所述侧墙 230形成于栅堆叠的侧壁上， 用于将栅堆叠 隔开。 侧墙 230可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 及其组合， 和 /或其他合适的材料形成。 侧墙 230可以具有多层结构。 侧墙 230可以通 过包括沉积-刻蚀工艺形成， 其厚度范围可以是 10nm -lOOnm, 如 30nm、 50nm或 80nm。
[0031]参考图 8和图 9, 执行步骤 S104, 在所述村底 100上形成覆盖所述 栅极堆叠和源 /漏区的掩膜层 400, 刻蚀所述掩膜层 400以暴露出所述源区 320。 如图 8所示， 所述掩膜层 400的材料为氧化硅、 氮化硅、 氮氧化硅， 通过化学气相淀积、 溅射等合适的方法形成在所述村底上。 随后如图 9所 示， 先形成一层覆盖所述掩膜层 400的光刻胶 410, 对光刻胶 410进行曝 光显影图形化， 刻蚀所述掩膜层 400, 从而暴露出源区 320。
[0032]参考图 10, 执行步骤 S105 , 刻蚀所述源区 320以及源区 320之下的 超薄绝缘埋层 104, 形成暴露出所述掩埋地层 103的开口 500, 去除所述光 刻胶 410。 具体地， 包括采用干法刻蚀 RIE或湿法腐蚀， 分别刻蚀源区 320 和超薄绝缘埋层 104, 以形成开口 500。
[0033]然后，参考图 11和 12,执行步骤 S106,通过外延填充所述开口 500, 以形成所述掩埋地层 103的接触塞 510。 以所述开口 500底部的掩埋地层 103为籽晶层， 进行外延生长， 形成接触塞 510。 所述掩埋地层接触塞 510 的材料可以是 Si、 Ge、 SiGe、 SiC。 在步骤 S106中， 还包括对掩埋地层接 触塞 510进行掺杂， 方法包括在外延过程中原位掺杂或离子注入。 所述掩 埋地层接触塞的掺杂浓度为 1018 ~ 102Qcm—3,与所述掩埋地层 103、源区 320 具有相同的掺杂类型。 对于 NMOS, 所述掩埋地层接触塞的掺杂类型为 N 型； 对于 PMOS , 所述掩埋地层接触塞的掺杂类型为 P型。 图 12为去掉掩 膜层 400之后的半导体结构剖面图， 可以看到， 所述掩埋地层接触塞 510 与所述源区 320相连， 位于所述源区 320远离所述栅极堆叠的一侧， 并贯 穿所述村底 100的表面有源层 105和超薄绝缘埋层 104, 与所述掩埋地层 103相连。
[0034]随后按照常规半导体制造工艺的步骤完成该半导体结构的制造， 例 如， 在源 /漏区上形成金属硅化物； 沉积层间介质层以覆盖所述源 /漏区和栅 极堆叠； 刻蚀所述层间介质层暴露源 /漏区以形成接触孔， 在所述接触孔中 填充金属； 以及后续的多层金属互连等工艺步骤。 或者， 在替代栅工艺中， 去除伪栅极， 形成金属栅等工艺步骤。
[0035]本发明还提供了一种半导体结构， 如图 12所示， 包括村底 100、 栅 极堆叠、 侧墙 230、 漏区 310、 源区 320、 掩埋地层接触塞 510。 其中所述 村底 100从下至上依次包括基底层 101、 掩埋隔离层 102、 掩埋地层 103、 超薄绝缘埋层 104和表面有源层 105 ,是超薄体超薄埋氧层（ Ultra-Thin Body and BOX, UTBB ) SOI结构； 所述栅极堆叠位于所述村底 100的表面有源 层 105之上； 所述侧墙 230位于所述栅极堆叠的侧壁上； 所述源区 320和 漏区 310位于所述栅极堆叠的两侧并嵌于所述村底 100的表面有源层 105 中； 所述掩埋地层接触塞 510与所述源区 320相连， 位于所述源区 320远 离所述栅极堆叠的一侧， 并贯穿所述村底 100的表面有源层 105和超薄绝 缘埋层 103 , 与所述掩埋地层 103 相连。 所述掩埋地层 103 的厚度为 5nm~30nm, 超薄绝缘埋层 104的厚度为 5nm~50nm, 表面有源层 105的厚 度为 5nm~50nm。 所述掩埋地层 103、 掩埋地层接触塞 510、 源区 320具有 相同的掺杂类型， 对于 NMOS , 其掺杂类型为 N型； 对于 PMOS , 其掺杂 类型为 P型。 所述掩埋地层接触塞 510的材料为 Si、 Ge、 SiGe、 SiC, 通 过选择合适的材料可以进一步调整半导体结构沟道区的应力， 提高电流驱 动能力。 掩埋地层 103作为背栅对该半导体结构的阈值电压进行控制， 提 高器件性能。 掩埋地层 103通过掩埋地层接触塞 510电学连接到源区 320, 使得掩埋地层 103的电位尽量保持固定， 不必单独为掩埋地层 103做引出 端和布线， 节省了器件面积和成本。
[0036]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明 的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种 变化、替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理解在保 持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0037]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领 域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的工 艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述 的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它 们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制造、 物质 组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
(a)提供村底， 所述村底从下至上依次包括基底层、 掩埋隔离层、 掩 埋地层、 超薄绝缘埋层、 表面有源层；
(b) 对所述掩埋地层进行离子注入掺杂；
(c) 在所述村底上形成栅极堆叠、 侧墙和源 /漏区；
(d) 在所述村底上形成覆盖所述栅极堆叠和源 /漏区的掩膜层， 刻蚀 所述掩膜层以暴露出所述源区；
( e )刻蚀所述源区以及源区之下的超薄绝缘埋层， 形成暴露出所述掩 埋地层的开口；
(f) 通过外延填充所述开口， 以形成所述掩埋地层的接触塞。
2、 根据权利要求 1所述的方法， 其中步骤（a) 中， 所述掩埋地层的 厚度为 5nm~30nm, 超薄绝缘埋层的厚度为 5nm~50nm, 表面有源层的厚度 为 5nm~50nm。
3、 根据权利要求 1所述的方法， 其中步骤 （b) 中， 所述掩埋地层的 掺杂浓度为 1018~ 102Qcm—3,对于 NMOS,所述掩埋地层的掺杂类型为 N型； 对于 PMOS, 所述掩埋地层的掺杂类型为 P型。
4、 根据权利要求 1所述的方法， 其中步骤 （d) 中， 所述掩膜层的材 料为氧化硅、 氮化硅、 氮氧化硅及其组合。
5、 根据权利要求 1 所述的方法， 其中步骤 （f) 中， 还包括对所述接 触塞进行掺杂， 掺杂方法包括在外延过程中原位掺杂或离子注入。
6、 根据权利要求 1或 5所述的方法， 其中步骤（f) 中， 所述接触塞 的掺杂浓度为 1018~ 102Qcm- 3,对于 NMOS,所述接触塞的掺杂类型为 N型； 对于 PMOS, 所述接触塞的掺杂类型为 P型。
7、 根据权利要求 1 所述的方法， 其中步骤 （f) 中， 所述接触塞的材 料为 Si、 Ge、 SiGe或 SiC。
8、 一种半导体结构， 该结构包括村底、 栅极堆叠、 侧墙、 源区、 漏区、 掩埋地层接触塞， 其中： 所述村底从下至上依次包括基底层、 掩埋隔离层、 掩埋地层、 超薄绝 缘埋层、 表面有源层；
所述栅极堆叠位于所述村底的表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区和漏区位于所述栅极堆叠的两侧并嵌于所述村底的表面有源 层中；
所述掩埋地层接触塞与所述源区相连， 位于所述源区远离所述栅极堆 叠的一侧， 并贯穿所述村底的表面有源层和超薄绝缘埋层， 与所述掩埋地 层相连。
9、 根据权利要求 8所述的半导体结构， 其中， 所述掩埋地层的掺杂浓 度为 1018 ~ 102Qcm—3, 对于 NMOS , 所述掩埋地层的掺杂类型为 N型； 对于 PMOS , 所述掩埋地层的掺杂类型为 P型。
10、 根据权利要求 8所述的半导体结构， 其中， 所述掩埋地层接触塞 的掺杂浓度为 1018 ~ 102Qcm—3 , 对于 NMOS , 所述掩埋地层接触塞的掺杂类 型为 N型； 对于 PMOS , 所述掩埋地层接触塞的掺杂类型为 P型。
11、 根据权利要求 8所述的半导体结构， 其中， 所述掩埋地层接触塞 的材料为 Si、 Ge、 SiGe或 SiC。
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