CN103377946B - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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CN103377946B
CN103377946B CN201210134597.XA CN201210134597A CN103377946B CN 103377946 B CN103377946 B CN 103377946B CN 201210134597 A CN201210134597 A CN 201210134597A CN 103377946 B CN103377946 B CN 103377946B
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contact plug
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尹海洲
朱慧珑
骆志炯
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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：提供衬底，所述衬底从下至上依次包括基底层、掩埋隔离层、掩埋地层、超薄绝缘埋层、表面有源层；对所述掩埋地层进行离子注入掺杂；在所述衬底上形成栅极堆叠、侧墙和源/漏区；在所述衬底上形成覆盖所述栅极堆叠和源/漏区的掩膜层，刻蚀所述掩膜层以暴露出所述源区；刻蚀所述源区以及源区之下的超薄绝缘埋层，形成暴露出所述掩埋地层的开口；通过外延填充所述开口，以形成所述掩埋地层的接触塞。相应地，本发明还提供了一种半导体结构。本发明通过形成掩埋地层接触塞，将掩埋地层与源区电学连接，增强了半导体器件对阈值电压的控制能力，减小了短沟道效应，提高了器件性能，同时不必对掩埋地层做单独引出，节省了器件面积，简化了工艺。

Description

一种半导体结构及其制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定律不断缩小，目前已经进入纳米尺度。传统平面体硅CMOS技术在集成度提高的同时，无法兼顾器件性能提高和功耗减小。器件参数随机涨落以及阈值电压无法按比例缩小等，进一步限制了器件整体性能的提升。在45nm及其以下技术节点，短沟道效应的急剧增加也使得器件进一步按比例缩小更为困难。
全耗尽绝缘体上硅(FDSOI)器件具有短沟道控制非常好、亚阈值特性好、漏电少、随机掺杂涨落影响小等特点，被认为是32nm及其以下节点替代传统体硅器件的优选结构。全耗尽绝缘体上硅器件，一般具有超薄硅膜(≤50nm)的SOI结构，减小埋氧层BOX的厚度(≤50nm)可以进一步提高器件的性能，减小自加热效应、边缘场等的影响。此外这种超薄体超薄埋氧层(Ultra-ThinBodyandBOX，UTBB)SOI器件，通过在超薄埋氧层背面引入地层增加背栅调控，可以减小源/漏区电场耦合，增加对阈值电压的控制，在低功耗应用上具有广阔的应用前景。但是，背栅电极引出和相应的布线，不可避免地会增加电路面积，增加成本。因而对于UTBBSOI器件，如何在器件性能和成本之间进行折中，成为一个亟待解决的重要问题。
发明内容
本发明旨在至少解决上述技术缺陷，提供一种半导体器件的制造方法及其结构，将掩埋地层与源区电学连接，不必对掩埋地层做单独引出，节省器件面积。
为达上述目的，本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：
(a)提供衬底，所述衬底从下至上依次包括基底层、掩埋隔离层、掩埋地层、超薄绝缘埋层、表面有源层；
(b)对所述掩埋地层进行离子注入掺杂；
(c)在所述衬底上形成栅极堆叠、侧墙和源/漏区；
(d)在所述衬底上形成覆盖所述栅极堆叠和源/漏区的掩膜层，刻蚀所述掩膜层以暴露出所述源区；
(e)刻蚀所述源区以及源区之下的超薄绝缘埋层，形成暴露出所述掩埋地层的开口；
(f)通过外延填充所述开口，以形成所述掩埋地层的接触塞。
本发明另一方面还提出一种半导体结构，包括衬底、栅极堆叠、侧墙、源区、漏区、掩埋地层接触塞，其中：
所述衬底从下至上依次包括基底层、掩埋隔离层、掩埋地层、超薄绝缘埋层、表面有源层；
所述栅极堆叠位于所述衬底的表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区和漏区位于所述栅极堆叠的两侧并嵌于所述衬底的表面有源层中；
所述掩埋地层接触塞与所述源区相连，位于所述源区远离所述栅极堆叠的一侧，并贯穿所述衬底的表面有源层和超薄绝缘埋层，与所述掩埋地层相连。
与现有技术相比，本发明具有如下优点：
通过形成掩埋地层接触塞，将掩埋地层与源区电学连接，增强了半导体器件对阈值电压的控制能力，减小了短沟道效应，提高了器件性能，同时不必对掩埋地层做单独引出，节省了器件面积，简化了工艺。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图；
图2至图12为根据图1示出的方法制造半导体结构过程中该半导体结构在各个制造阶段的剖面结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
图1为根据本发明的半导体结构制造方法的流程图，图2至图12为根据本发明的一个实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。下面将结合图2至图12对图1中形成半导体结构的方法进行具体地描述。需要说明的是，本发明实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参考图1和图2，在步骤S101中，提供衬底100，所述衬底100从下至上依次包括基底层101、掩埋隔离层102、掩埋地层103、超薄绝缘埋层104、表面有源层105。
本发明中采用的衬底为超薄体超薄埋氧层(Ultra-ThinBodyandBOX，UTBB)SOI结构。所述基底层101为位于其上的各层提供机械支撑。在本实施例中，所述基底层101为单晶硅。在其他实施例中，所述基底层101还可以包括其他基本半导体例如锗，或其他化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。典型地，所述基底层101的厚度可以约为但不限于几百微米，例如0.1mm-1mm的厚度范围。
所述掩埋隔离层102和所述超薄绝缘埋层104的材料为SiO2、氮化硅、Al2O3或者其他任何合适的绝缘材料，典型地，所述掩埋隔离层102的厚度范围为50nm～300nm，所述超薄绝缘埋层104的厚度范围为5nm～50nm。
所述掩埋地层103和所述表面有源层105的材料为硅、锗或其他化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。所述掩埋地层103的厚度为5nm～30nm，所述表面有源层105的厚度为5nm～50nm。
特别地，在步骤S101中，还包括在所述衬底100中形成隔离区，例如浅沟槽隔离(STI)结构120，以便电隔离连续的半导体器件，如图3所示，所述浅沟槽隔离(STI)结构120贯穿所述掩埋地层103、超薄绝缘埋层104、表面有源层105，与所述掩埋隔离层102相接。
参考图1和图4，执行步骤S102，对所述掩埋地层103进行离子注入掺杂。具体地，在所述衬底上覆盖一层光刻胶130，对所述光刻胶进行曝光显影。然后以光刻胶130为掩膜，进行离子注入。通过调整离子注入的粒子能量、电压、注入剂量等参数，使得离子注入的浓度峰值在所述掩埋地层103中，并对所述表面有源层105不会造成损伤。随后，进行退火处理，得到重掺杂的掩埋地层103。所述掩埋地层103的掺杂浓度可以根据器件阈值电压的要求进行设计，其范围为1018～1020cm-3，对于NMOS，所述掩埋地层的掺杂类型为N型；对于PMOS，所述掩埋地层的掺杂类型为P型。
随后，执行步骤S103，在所述衬底100上形成栅极堆叠、侧墙230、漏区310和源区320。
首先，如图5所示，在所述衬底上形成栅极堆叠，所述栅极堆叠包括栅介质层210和栅极220。可选地，所述栅极堆叠还可以包括覆盖在所述栅极上的覆盖层(未在图中示出)，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护栅极220的顶部区域，防止其在后续的工艺中受到破坏。所述栅介质层210位于衬底100的表面有源层105之上，可以为高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合。在另一个实施例中，还可以是热氧化层，包括氧化硅、氮氧化硅；所述栅极介质层210的厚度可以为1nm～10nm，如5nm或8nm。而后在所述栅介质层210上形成栅极220，所述栅极220可以是通过沉积形成的重掺杂多晶硅，或是先形成功函数金属层(对于NMOS，例如TaC，TiN，TaTbN，TaErN，TaYbN，TaSiN，HfSiN，MoSiN，RuTax，NiTax等，对于PMOS，例如MoNx，TiSiN，TiCN，TaAlC，TiAlN，TaN，PtSix，Ni3Si，Pt，Ru，Ir，Mo，HfRu，RuOx)，其厚度可以为1nm-20nm，如3nm、5nm、8nm、10nm、12nm或15nm，再在所述功函数金属层上形成重掺杂多晶硅、Ti、Co、Ni、Al、W或其合金等而形成栅极220。
在本发明的另外一些实施例中，也可采用后栅工艺(gatelast)，此时，栅极堆叠包括栅极220(此时为伪栅)和承载所述栅极的栅介质层210。在所述栅介质层210上通过沉积例如多晶硅、多晶SiGe、非晶硅，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅，甚至金属形成栅极220(此时为伪栅)，其厚度可以为10nm～80nm。可选地，还包括在所述栅极220(此时为伪栅)上形成覆盖层，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护伪栅极220的顶部区域，防止栅极220(此时为伪栅)的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在另一个采用后栅工艺实施例中，栅极堆叠也可以没有栅介质层210，而是后续工艺步骤中，除去所述伪栅后，在填充功函数金属层之前形成栅介质层210。
随后，如图6所示，以所述栅极堆叠为掩膜，向表面有源层105中注入P型或N型杂质，进而在所述栅极堆叠两侧形成漏区310和源区320。对于PMOS来说，漏区310和源区320可以是P型掺杂的Si；对于NMOS来说，漏区310和源区320可以是N型掺杂的Si。然后对所述半导体结构进行退火，以激活漏区310和源区320中的杂质，退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。可选地，所述漏区310和源区320也可以在形成侧墙230之后形成，而在形成栅极堆叠之后，以低能注入的方式形成源/漏延伸区(未在图中画出)。
如图7所示，所述侧墙230形成于栅堆叠的侧壁上，用于将栅堆叠隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅、及其组合，和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙230可以通过包括沉积-刻蚀工艺形成，其厚度范围可以是10nm～100nm，如30nm、50nm或80nm。
参考图8和图9，执行步骤S104，在所述衬底100上形成覆盖所述栅极堆叠和源/漏区的掩膜层400，刻蚀所述掩膜层400以暴露出所述源区320。如图8所示，所述掩膜层400的材料为氧化硅、氮化硅、氮氧化硅，通过化学气相淀积、溅射等合适的方法形成在所述衬底上。随后如图9所示，先形成一层覆盖所述掩膜层400的光刻胶410，对光刻胶410进行曝光显影图形化，刻蚀所述掩膜层400，从而暴露出源区320。
参考图10，执行步骤S105，刻蚀所述源区320以及源区320之下的超薄绝缘埋层104，形成暴露出所述掩埋地层103的开口500，去除所述光刻胶410。具体地，包括采用干法刻蚀RIE或湿法腐蚀，分别刻蚀源区320和超薄绝缘埋层104，以形成开口500。
然后，参考图11和12，执行步骤S106，通过外延填充所述开口500，以形成所述掩埋地层103的接触塞510。以所述开口500底部的掩埋地层103为籽晶层，进行外延生长，形成接触塞510。所述掩埋地层接触塞510的材料可以是Si、Ge、SiGe、SiC。在步骤S106中，还包括对掩埋地层接触塞510进行掺杂，方法包括在外延过程中原位掺杂或离子注入。所述掩埋地层接触塞的掺杂浓度为1018～1020cm-3，与所述掩埋地层103、源区320具有相同的掺杂类型。对于NMOS，所述掩埋地层接触塞的掺杂类型为N型；对于PMOS，所述掩埋地层接触塞的掺杂类型为P型。图12为去掉掩膜层400之后的半导体结构剖面图，可以看到，所述掩埋地层接触塞510与所述源区320相连，位于所述源区320远离所述栅极堆叠的一侧，并贯穿所述衬底100的表面有源层105和超薄绝缘埋层104，与所述掩埋地层103相连。
随后按照常规半导体制造工艺的步骤完成该半导体结构的制造，例如，在源/漏区上形成金属硅化物；沉积层间介质层以覆盖所述源/漏区和栅极堆叠；刻蚀所述层间介质层暴露源/漏区以形成接触孔，在所述接触孔中填充金属；以及后续的多层金属互连等工艺步骤。或者，在替代栅工艺中，去除伪栅极，形成金属栅等工艺步骤。
本发明还提供了一种半导体结构，如图12所示，包括衬底100、栅极堆叠、侧墙230、漏区310、源区320、掩埋地层接触塞510。其中所述衬底100从下至上依次包括基底层101、掩埋隔离层102、掩埋地层103、超薄绝缘埋层104和表面有源层105，是超薄体超薄埋氧层(Ultra-ThinBodyandBOX，UTBB)SOI结构；所述栅极堆叠位于所述衬底100的表面有源层105之上；所述侧墙230位于所述栅极堆叠的侧壁上；所述源区320和漏区310位于所述栅极堆叠的两侧并嵌于所述衬底100的表面有源层105中；所述掩埋地层接触塞510与所述源区320相连，位于所述源区320远离所述栅极堆叠的一侧，并贯穿所述衬底100的表面有源层105和超薄绝缘埋层103，与所述掩埋地层103相连。所述掩埋地层103的厚度为5nm～30nm，超薄绝缘埋层104的厚度为5nm～50nm，表面有源层105的厚度为5nm～50nm。所述掩埋地层103、掩埋地层接触塞510、源区320具有相同的掺杂类型，对于NMOS，其掺杂类型为N型；对于PMOS，其掺杂类型为P型。所述掩埋地层接触塞510的材料为Si、Ge、SiGe、SiC，通过选择合适的材料可以进一步调整半导体结构沟道区的应力，提高电流驱动能力。掩埋地层103作为背栅对该半导体结构的阈值电压进行控制，提高器件性能。掩埋地层103通过掩埋地层接触塞510电学连接到源区320，使得掩埋地层103的电位尽量保持固定，不必单独为掩埋地层103做引出端和布线，节省了器件面积和成本。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (11)

1.一种半导体结构的制造方法，该方法包括以下步骤：
(a)提供衬底，所述衬底从下至上依次包括基底层、掩埋隔离层、掩埋地层、超薄绝缘埋层、表面有源层；其中，所述超薄绝缘埋层的厚度范围为5nm～50nm；
(b)对所述掩埋地层进行离子注入掺杂；
(c)在所述衬底上形成栅极堆叠、侧墙和源/漏区；
(d)在所述衬底上形成覆盖所述栅极堆叠和源/漏区的掩膜层，刻蚀所述掩膜层以暴露出所述源区；
(e)刻蚀所述源区以及源区之下的绝缘埋层，形成暴露出所述掩埋地层的开口；
(f)通过外延填充所述开口，以形成所述掩埋地层的接触塞。
2.根据权利要求1所述的方法，其中步骤(a)中，所述掩埋地层的厚度为5nm～30nm，表面有源层的厚度为5nm～50nm。
3.根据权利要求1所述的方法，其中步骤(b)中，所述掩埋地层的掺杂浓度为1018～1020cm-3，对于NMOS，所述掩埋地层的掺杂类型为N型；对于PMOS，所述掩埋地层的掺杂类型为P型。
4.根据权利要求1所述的方法，其中步骤(d)中，所述掩膜层的材料为氧化硅、氮化硅、氮氧化硅及其组合。
5.根据权利要求1所述的方法，其中步骤(f)中，还包括对所述接触塞进行掺杂，掺杂方法包括在外延过程中原位掺杂或离子注入。
6.根据权利要求1或5所述的方法，其中步骤(f)中，所述接触塞的掺杂浓度为1018～1020cm-3，对于NMOS，所述接触塞的掺杂类型为N型；对于PMOS，所述接触塞的掺杂类型为P型。
7.根据权利要求1所述的方法，其中步骤(f)中，所述接触塞的材料为Si、Ge、SiGe或SiC。
8.一种半导体结构，该结构包括衬底、栅极堆叠、侧墙、源区、漏区、掩埋地层接触塞，其中：
所述衬底从下至上依次包括基底层、掩埋隔离层、掩埋地层、超薄绝缘埋层、表面有源层；其中，所述超薄绝缘埋层的厚度范围为5nm～50nm；
所述栅极堆叠位于所述衬底的表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区和漏区位于所述栅极堆叠的两侧并嵌于所述衬底的表面有源层中，其中所述源区完全位于所述侧墙下方；
所述掩埋地层接触塞与所述源区直接相连，位于所述源区远离所述栅极堆叠的一侧，并贯穿所述衬底的表面有源层和绝缘埋层，与所述掩埋地层相连。
9.根据权利要求8所述的半导体结构，其中，所述掩埋地层的掺杂浓度为1018～1020cm-3，对于NMOS，所述掩埋地层的掺杂类型为N型；对于PMOS，所述掩埋地层的掺杂类型为P型。
10.根据权利要求8所述的半导体结构，其中，所述掩埋地层接触塞的掺杂浓度为1018～1020cm-3，对于NMOS，所述掩埋地层接触塞的掺杂类型为N型；对于PMOS，所述掩埋地层接触塞的掺杂类型为P型。
11.根据权利要求8所述的半导体结构，其中，所述掩埋地层接触塞的材料为Si、Ge、SiGe或SiC。
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