CN103681509A - 一种半导体结构的制造方法 - Google Patents

一种半导体结构的制造方法 Download PDF

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CN103681509A
CN103681509A CN201210362169.2A CN201210362169A CN103681509A CN 103681509 A CN103681509 A CN 103681509A CN 201210362169 A CN201210362169 A CN 201210362169A CN 103681509 A CN103681509 A CN 103681509A
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尹海洲
朱慧珑
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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：a）提供SOI衬底，在所述SOI衬底上形成栅极堆叠；b）对源区和漏区进行非晶化注入，其中源区非晶化注入中的工艺温度高于漏区非晶化注入中的工艺温度；c）进行源/漏区掺杂；d）退火，激活杂质，并使源/漏区的非晶化区域重结晶。步骤b）的源区非晶化注入中，工艺温度高于50℃，并且漏区非晶化注入中，工艺温度低于-30℃。本发明通过在源区下方产生缺陷，为体区积累的电荷提供泄放通道，减小浮体效应的影响，提高器件的可靠性。

Description

一种半导体结构的制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构的制造方法。
背景技术
为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定律不断缩小，目前已经进入纳米尺度。随着器件体积的缩小，功耗与漏电流成为最关注的问题。采用绝缘体上硅SOI（Silicon on Insulator）制备的CMOS器件具有高速、低功耗、高集成度、抗辐照和无自锁效应等许多优点，已成为深亚微米及纳米级MOS器件的优选结构。
根据体区是否耗尽，SOI器件分为部分耗尽和全耗尽两种类型。一般来说，全耗尽SOI器件的顶层硅膜比较薄，而且阈值电压不容易控制。因此，目前部分耗尽SOI器件依然是普遍采用的经济有效的解决方案。部分耗尽SOI器件由于体区未完全耗尽，体区处于悬空状态，碰撞电离产生的电荷无法迅速移走，导致出现浮体效应。对于SOI NMOS器件，沟道电子在漏端碰撞电离产生的电子空穴对，空穴流向体区，在体区积累，抬高体区电势，使得NMOS的阈值电压降低而增加漏电流，导致器件的输出特性曲线出现翘曲，对器件和电路性能以及可靠性产生不利影响。对于PMOS器件，空穴电离率较低，碰撞电离产生的电子-空穴对远低于NMOS，浮体效应的影响弱一些。
为了解决浮体效应，通常采用体接触的方法，在体区制作电学引出，连接到固定电位（源端或地），从而为体区积累的电荷提供泄放通道，降低体区电势。但是，这样会导致工艺流程更加复杂，增加器件制作成本，降低了部分电学性能并增大了器件面积。
发明内容
本发明旨在至少解决上述技术缺陷，提供一种方法，减小SOI器件的浮体效应，提高半导体器件的性能和可靠性。
为达上述目的，本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：
a）提供SOI衬底，在所述SOI衬底上形成栅极堆叠；
b）对源区和漏区进行非晶化注入，其中源区非晶化注入中的工艺温度高于漏区非晶化注入中的工艺温度；
c）进行源/漏区掺杂；
d）退火，激活杂质，并使源/漏区的非晶化区域重结晶。
其中，在本发明的一个实施例中，步骤b）的源区非晶化注入中，工艺温度高于50℃，而漏区非晶化注入中，工艺温度低于-30℃。
优选地，所述源区和漏区非晶化注入的离子为硅或锗，工艺温度低于-30℃，注入深度为50~70nm。
根据本发明提供的制造方法，在完成退火后，漏区的非晶化区域重结晶，几乎没有缺陷残留，而源区非晶化在相对较高的温度下进行，退火后残留许多缺陷，这些缺陷可以在源区和体区之间提供电荷泄放通道，减小浮体效应的影响，提高器件的可靠性。同时，由于只是在源/漏区制作时增加了工艺步骤，并未影响标准的半导体工艺流程，而且也不必在体区制作电学引出，不会增大器件面积。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图；
图2至图7为根据图1示出的方法制造半导体结构过程中该半导体结构在各个制造阶段的剖面、平面俯视结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
图1为根据本发明的半导体结构制造方法的流程图，图2至图7为根据本发明的一个实施例按照图1所示流程制造半导体结构的各个阶段的剖面示意图。下面将结合图2至图7对图1中形成半导体结构的方法进行具体地描述。需要说明的是，本发明实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参考图2至图3，在步骤S101中，提供SOI衬底100，在所述SOI衬底100上依次形成栅极堆叠、源/漏延伸区230和240以及侧墙250。
如图2所示，所述SOI衬底100包括基底层101、位于所述基底层101之上的绝缘层102以及位于所述绝缘层102之上的器件层103。
在本实施例中，所述基底层101为单晶硅。在其他实施例中，所述基底层101还可以包括其他基本半导体例如锗，或其他化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。典型地，所述基底层101的厚度可以约为但不限于几百微米，例如0.2mm-1mm的厚度范围。所述绝缘层102可以为SiO2、氮化硅、Al2O3或者其他任何合适的绝缘材料，典型地，所述绝缘层102的厚度范围为10nm~300nm。
所述器件层103可以为所述基底层101包括的半导体中的任何一种。在本实施例中，所述器件层103为单晶硅。在其他实施例中，所述器件层103还可以包括其他基本半导体或者化合物半导体。典型地，所述器件层103的厚度范围是10nm~100nm。
随后，如图3所示，在所述SOI衬底100上形成栅极堆叠、源/漏延伸区230和240以及侧墙250。
所述栅极堆叠包括栅介质层210和栅极220。可选地，所述栅极堆叠还可以包括覆盖在所述栅极上的覆盖层（未在图中示出），例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护栅极220的顶部区域，防止其在后续的工艺中受到破坏。所述栅介质层210位于SOI衬底100的表面器件层103之上，可以为高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合。在另一个实施例中，还可以是热氧化层，包括氧化硅、氮氧化硅；所述栅极介质层210的厚度可以为1nm~10nm，如5nm或8nm。而后在所述栅介质层210上形成栅极220，所述栅极220可以是通过沉积形成的重掺杂多晶硅，或是先形成功函数金属层（对于NMOS，例如TaC,TiN,TaTbN,TaErN,TaYbN,TaSiN,HfSN,MoSiN,RuTax,NiTax等，对于PMOS，例如MoNx,TiSiN,TiCN,TaAlC,TiAlN,TaN,PtSix,Ni3Si,Pt,Ru,Ir,Mo,HfRu,RuOx），其厚度可以为1nm-20nm，如3nm、5nm、8nm、10nm、12nm或15nm，再在所述功函数金属层上形成重掺杂多晶硅、Ti、Co、Ni、Al、W或其合金等而形成栅极220。
在本发明的另外一些实施例中，也可采用后栅工艺（gate last），此时，栅极堆叠包括栅极220（此时为伪栅）和承载所述栅极的栅介质层210。在所述栅介质层210上通过沉积例如多晶硅、多晶SiGe、非晶硅，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅，甚至金属形成栅极220（此时为伪栅），其厚度可以为10nm~80nm。可选地，还包括在所述栅极220（此时为伪栅）上形成覆盖层，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护伪栅极220的顶部区域，防止栅极220（此时为伪栅）的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在另一个采用后栅工艺实施例中，栅极堆叠也可以没有栅介质层210，而是后续工艺步骤中，除去所述伪栅后，在填充功函数金属层之前形成栅介质层210。
形成所述栅极堆叠之后，以所述栅极堆叠为掩膜，向器件层103中注入P型或N型杂质，进而在所述栅极堆叠两侧形成源/漏延伸区230和240。对于PMOS来说，源延伸区230和漏延伸区240掺杂类型为P型；对于NMOS来说，源延伸区230和漏延伸区240掺杂类型为N型。
随后在所述栅极堆叠的侧壁形成侧墙250，用于将栅极堆叠隔开。侧墙250可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙250可以具有多层结构。侧墙250可以通过包括沉积-刻蚀工艺形成，其厚度范围可以是10nm~100nm，如30nm、50nm或80nm。
参考图4，执行步骤S102，源区非晶化注入。首先，进行一次光刻，用光刻胶将漏区覆盖。随后，对裸露的源延伸区230进行非晶化注入，形成如图4所示的源极非晶化区310。注入的离子为硅或锗，工艺温度高于在漏区进行非晶化注入时的工艺温度，例如高于50℃。通过调整注入的剂量、能量等参数，使得注入深度控制在50~70nm。
参考图5，执行步骤S103，漏区非晶化注入。进行一次光刻，用光刻胶将源区覆盖。随后，对裸露的漏延伸区240进行非晶化注入，形成如图5所示的漏极非晶化区320。注入的离子为硅或锗，工艺温度低于在源区进行非晶化注入时的工艺温度，例如低于-30℃，可选地采用液氮冷却控制工艺温度，较低的工艺温度可以减小可能产生注入缺陷的区域，从而明显地减少后续工艺中产生的缺陷。通过调整注入的剂量、能量等参数，使得注入深度控制在50~70nm。
上述在源区和漏区进行非晶化处理的步骤可以交换次序进行。即，可以先覆盖源区按照上述漏区的注入工艺参数进行漏区的注入，然后覆盖漏区按照上述源区的注入工艺进行源区的注入。
上述非晶化处理的步骤也可以在形成栅极堆叠之后，并且在形成源/漏延伸区230和240以及侧墙250之前执行。
参考图6，执行步骤S104，进行源区410和漏区420掺杂。以栅极堆叠和侧墙250为掩膜，向衬底中注入P型或N型杂质，从而形成源区410和漏区420。对于PMOS，源区410和漏区420为P型掺杂，注入离子为B或BF2；对于NMOS，源区410和漏区420为N型掺杂，注入离子为P或As。由于在步骤S102和S103中，对源/漏区进行了非晶化注入，在源/漏区掺杂注入过程中，可以非常有效地阻止硼等杂质离子的异常扩散。
随后，执行步骤S105，退火，激活杂质，并使源/漏区的非晶化区域重结晶。退火可以采用包括快速退火、尖峰退火等其他合适的方法，工艺温度高于900℃。退火之后，漏极非晶化区320重结晶，同时由于漏区非晶化注入工艺温度较低，产生的缺陷较少，因而退火之后，漏区的缺陷也非常少。对于源区，退火之后，源极非晶化区域310重结晶，但是由于源区非晶化注入在相对高一些的温度下进行，所产生的缺陷不能完全在退火过程中消除，在源区有一定数量的残留，形成缺陷区510，如图7所示。这些缺陷可以在源区410和器件层103体区之间形成电荷的泄放通道，从而减小SOI器件的浮体效应，提高器件的可靠性。同时，由于只是在源/漏区制作时增加了工艺步骤，并未影响标准的半导体工艺流程，而且也不必在体区制作电学引出，不会增大器件面积。
随后按照常规半导体制造工艺的步骤完成该半导体结构的制造，例如，在源/漏区上形成金属硅化物；沉积层间介质层以覆盖所述源/漏区和栅极堆叠；刻蚀所述层间介质层暴露源/漏区以形成接触孔，在所述接触孔中填充金属；以及后续的多层金属互连等工艺步骤。或者，在替代栅工艺中，去除伪栅极，形成金属栅等工艺步骤。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (9)

1.一种半导体结构的制造方法，该方法包括以下步骤：
a）提供SOI衬底，在所述SOI衬底上形成栅极堆叠；
b）对源区和漏区进行非晶化注入，其中源区非晶化注入中的工艺温度高于漏区非晶化注入中的工艺温度；
c）进行源/漏区掺杂；
d）退火，激活杂质，并使源/漏区的非晶化区域重结晶。
2.根据权利要求1所述的方法，其中：
步骤b）的源区非晶化注入中，工艺温度高于50℃；以及漏区非晶化注入中，工艺温度低于-30℃。
3.根据权利要求1所述的方法，其中在步骤a）形成栅极堆叠之后还形成源/漏延伸区以及侧墙。
4.根据权利要求1所述的方法，步骤b）中，还包括，在源区非晶化注入之前，将漏区覆盖。
5.根据权利要求1所述的方法，步骤b）中，还包括，在漏区非晶化注入之前，将源区覆盖。
6.根据权利要求1所述的方法，步骤d）中，对于NMOS器件，所述源/漏区的掺杂类型为n型，注入离子为P或As；对于PMOS器件，所述源/漏区的掺杂类型为p型，注入离子为B或BF2。
7.根据权利要求1所述的方法，步骤d）中，退火温度高于900℃。
8.根据权利要求1所述的方法，所述步骤b）中对源区和漏区交换次序进行非晶化注入。
9.根据权利要求1-8中的任何一项所述的方法，所述步骤b）的所述非晶化注入的离子为硅或锗，注入深度为50~70nm。
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