CN103377930B - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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Abstract
本发明提供了一种半导体结构的制造方法,该方法包括:提供SOI衬底,并在所述SOI衬底上形成栅极结构;以所述栅极结构为掩模对半导体结构进行应力引发离子的注入,在栅极结构的两侧形成位于所述SOI衬底的BOX层之下的应力引发区。相应地,本发明还提供了一种根据上述方法形成的半导体结构。本发明提供的半导体结构及其制造方法在接地层形成应力引发区,所述应力引发区为半导体器件的沟道提供了有利应力,有助于提升半导体器件的性能。
Description
技术领域
本发明涉及半导体领域,具体地说涉及一种半导体结构及其制造方法。
背景技术
随着半导体器件制造技术的发展,具有更高性能和更强功能的集成电路要求更大的元件密度,而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小,因此半导体器件制造过程中对工艺控制的要求较高。
半导体器件通过按比例缩小来实现工作速度的提升。MOS晶体管的沟道长度也在不断地按比例缩短,但当MOS晶体管的沟道长度变得非常短时,所谓的短沟道效应(SCE),以及漏极感应势垒降低效应(Drain-InducedBarrierLowering,DIBL)给半导体器件微型化设置了严重的障碍。
由于短沟道效应会使器件性能劣化,甚至无法正常工作,因此减小短沟道效应是半导体器件研究制造中的重要课题。半导体器件内部的机械应力被广泛地用于调节器件的性能,通过在沟道施加应力的方法,可以有效减小短沟道效应。
常用的增加应力的方法是在源漏区进行操作,以便在沟道上形成拉伸或压缩应力。例如,在通用硅技术中,晶体管沟道沿着硅的{110}取向。在这种布置中,当沟道受到沿着沟道方向的压缩应力和/或沿着与沟道垂直方向的拉伸应力时,空穴的迁移率提高;而当沟道受到沿着沟道方向的拉伸应力和/或沿着与沟道垂直方向的压缩应力时,电子的迁移率增高。因此在半导体器件的沟道区引入应力,可以提高器件的性能。
使用SOI衬底代替硅衬底也可以达到减小短沟道效应和提高器件性能的效果。绝缘体上硅(SiliconOnInsulator,SOI)技术是在顶部体硅层和衬底体硅层之间引入了一层埋氧层。通过在绝缘体上形成半导体薄膜,SOI材料具有了体硅所无法比拟的优点:可以实现集成电路中元器件的介质隔离,彻底消除了体硅CMOS电路中的寄生闩锁效应;采用这种材料制成的集成电路还具有寄生电容小、集成密度高、速度快、工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势,因此可以说SOI将有可能成为深亚微米的低压、低功耗集成电路的主流技术。
同时,SOI的异质结构为建造具有超薄硅体器件创造了机会。通过由硅电介质界面建立的天然静电屏障,超薄SOI提供一种控制短沟道效应的可选手段。
目前,有技术采用在超薄SOIMOS晶体管(Ultrathin-SOIMOSFET)的超薄BOX层之下形成一个接地层来减小短沟道效应,并控制功耗。但是如果能在此种结构的半导体器件中引入应力则可以进一步减小短沟道效应并提高半导体器件的性能。
发明内容
本发明的目的在于提供一种半导体结构及其制造方法,通过在接地层形成应力引发区,对使用超薄SOI衬底制造形成的半导体器件的沟道区引入有利应力,提高所述半导体器件的性能。
一方面,本发明提供了一种半导体结构的制造方法,该方法包括:
(a)提供SOI衬底,并在所述SOI衬底上形成栅极结构;
(b)以所述栅极结构为掩模对半导体结构进行应力引发离子的注入,在栅极结构的两侧形成位于所述SOI衬底的BOX层之下的应力引发区。
相应地,本发明还提供了一种半导体结构,该半导体结构包括:
SOI衬底,包括SOI层、BOX层和体硅层;
形成于SOI层中的源/漏区和在源/漏区下方的体硅层中的应力引发区。
本发明提供的半导体结构及其制造方法在超薄SOI衬底上形成接地层,之后再接地层中进行离子注入和退火操作,形成应力引发区,所述应力引发区为半导体器件的沟道提供了有利应力,有助于提升半导体器件的性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1为根据本发明的半导体结构的制造方法的一个具体实施方式的流程图;
图2~图9是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
由于本发明提供的半导体结构具有几种优选结构,下面提供一种优选结构并进行概述。
实施例一:
参考图9,图9示出了一种半导体结构,该半导体结构包括SOI衬底、接地层140、栅极结构200、源/漏区160、源/漏延伸区170和应力引发区150,其中:
所述SOI衬底包括SOI层100、BOX层110和体硅层130;
所述栅极结构200形成在所述SOI层100之上;
所述源/漏区160和源/漏延伸区170形成于所述SOI层100之中;
所述接地层140位于所述体硅层130中,所述BOX层110的下方;
所述应力引发区150形成在所述栅极结构200两侧的所述SOI衬底内BOX层110的下方。
此外,在栅极结构200的两侧还形成侧墙210。
所述SOI衬底至少具有三层结构,分别是:体硅层130、体硅层130之上的BOX层110,以及覆盖在BOX层110之上的SOI层100。其中,所述BOX层110的材料可以选用晶体或者非晶体氧化物、氮化物或其任意组合。优选地,通常选用SiO2。SOI层100的材料是单晶硅、Ge或III-V族化合物(如SiC、砷化镓、砷化铟或磷化铟等)。本发明中选用的SOI衬底是具有超薄SOI层100和超薄BOX层110的SOI衬底,其中超薄SOI层100的厚度范围为5~20nm,例如5nm、15nm或20nm;超薄BOX层110的厚度范围为5~30nm,例如5nm、20nm或30nm。
可选的,还可以在SOI衬底中还形成隔离区120,用于将所述SOI层100分割为独立的区域,用于后续加工形成晶体管结构所用。隔离区120的材料是绝缘材料,例如可以选用SiO2、Si3N4或其组合。隔离区120的宽度可以视半导体结构的设计需求决定。
在前栅工艺中,栅极结构200包括栅极介质层和栅极堆叠;在后栅工艺中,栅极结构200包括伪栅和承载伪栅的栅介质层。侧墙210可以由氮化硅、氧化硅、氮氧化硅、碳化硅和/或其他合适的材料形成。侧墙210可以具有多层结构。侧墙210可以通过沉积-刻蚀工艺形成,其厚度范围大约是10nm-100nm。
在SOI层100内通过离子注入的方式形成源/漏区160和源/漏延伸区170。例如,对于PMOS来说,源/漏区160和源/漏延伸区170可以是P型掺杂,对于NMOS来说,源/漏区160和源/漏延伸区170可以是N型掺杂。
接地层140形成于体硅层130内,例如,对于PFET和NFET分别采用n型和p型掺杂。应力引发区150采用碳掺杂形成于接地层140内。应力引发区150的位置在源/漏区160的下方(隔着BOX层),有利于为沟道区引入拉应力,显著提高NFET的性能。
下文中将结合本发明提供的半导体结构的制造方法对上述实施例进行进一步的阐述。
请参考图1,图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图,该方法包括:
步骤S101,提供SOI衬底,并在所述SOI衬底上形成栅极结构200;
步骤S102,以所述栅极结构200为掩模对半导体结构进行应力引发离子的注入,在栅极结构的两侧形成位于所述SOI衬底的BOX层110之下的应力引发区150。
下面结合图2至图9对步骤S101至步骤S102进行说明,图2至图9是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。需要说明的是,本发明各个实施例的附图仅是为了示意的目的,因此没有必要按比例绘制。
参考图2~图8,执行步骤S101,提供SOI衬底,并在所述SOI衬底上形成栅极结构200。
首先参考图2,其中,所述SOI衬底至少具有三层结构,分别是:体硅层130、体硅层130之上的BOX层110,以及覆盖在BOX层110之上的SOI层100。其中,所述BOX层110的材料通常选用SiO2。SOI层100的材料是单晶硅、Ge或III-V族化合物(如SiC、砷化镓、砷化铟或磷化铟等)。本发明中选用的SOI衬底是具有超薄SOI层100和超薄BOX层110的SOI衬底,其中SOI层100的厚度范围为5~20nm,例如5nm、15nm、20nm;BOX层110的厚度范围为5~30nm,例如5nm、20nm、30nm。
之后在该SOI衬底中还形成隔离区120,用于将所述SOI层100分割为独立的区域,用于后续加工形成晶体管结构所用,如图3所示。隔离区120的材料是绝缘材料,例如可以选用SiO2、Si3N4或其组合,隔离区120的宽度可以视半导体结构的设计需求决定。
形成隔离区120之后,通过离子注入的方式形成接地层140,参考图4。控制注入能量使得所述接地层形成于BOX层110之下。例如,对于PFET和NFET分别采用n型和p型掺杂。
接下来参考图5,在所述SOI衬底上(具体而言是在SOI层100上)形成栅极结构200,在前栅工艺中,该栅极结构200的形成过程例如:形成覆盖SOI层100的栅极介质层、覆盖栅极介质层的栅金属层、覆盖栅金属层的栅电极层、覆盖栅电极层的氧化物层、覆盖氧化物层的氮化物层、以及覆盖氮化物层并用于绘图以刻蚀出栅极堆叠的光刻胶层。其中,栅极介质层的材料可以是热氧化层,包括氧化硅或氮氧化硅,也可为高K介质,例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,其厚度在1nm~4nm之间;栅金属层的材料可以选用TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTa中的一种或其组合,其厚度在5nm~20nm之间;栅电极层的材料可以选用Poly-Si,其厚度在20nm~80nm之间;氧化物层的材料是SiO2,其厚度在5nm~10nm之间;氮化物层的材料是Si3N4,其厚度在10nm~50nm之间;光刻胶层的材料可是烯类单体材料、含有叠氮醌类化合物的材料或聚乙烯月桂酸酯材料等。上述多层结构中除所述光刻胶层以外,可以通过化学气相沉积(Chemicalvapordeposition,CVD)、高密度等离子体CVD、ALD(原子层淀积)、等离子体增强原子层淀积(PEALD)、脉冲激光沉积(PLD)或其他合适的方法依次形成在SOI层100上。光刻胶层构图后可以刻蚀上述多层结构形成如图3所示的栅极结构200(在所述SOI衬底上形成栅极线)。
在后栅工艺中,栅极结构200包括伪栅和承载伪栅的栅介质层,可以在随后的步骤中进行替代栅工艺,移除伪栅以形成所需的栅极堆叠结构。
在栅极结构200形成之后,进行退火以控制接地层140的掺杂分布,以便调节器件的开启电压。
在进行退火之后,通过低能注入的方式在所述SOI层100中形成源/漏延伸区170,参考图6。可以向所述SOI层100中注入P型或N型掺杂物或杂质。即,如果要制作的半导体器件为NMOS,则向所述SOI层100中掺杂N型杂质,例如硼和铟。如果所述半导体器件为PMOS,则向所述SOI层100中掺杂P型杂质,例如砷和磷。然后对所述半导体结构进行退火,以激活源/漏延伸区170中的掺杂。在一个实施例中,也可以不形成源/漏延伸区170。
随后,在栅极结构200的侧壁上形成侧墙210,用于将栅极结构200隔开,参考图7。侧墙210可以由氮化硅、氧化硅、氮氧化硅、碳化硅和/或其他合适的材料形成。侧墙210可以具有多层结构。侧墙210可以通过沉积-刻蚀工艺形成,其厚度范围大约是10nm~100nm,如30nm、50nm或80nm。
形成侧墙210之后形成源/漏区160。如图8所示,源/漏区160可以通过向SOI层100中注入P型或N型掺杂物或杂质而形成,例如,对于PMOS来说,源/漏区160可以是P型掺杂,对于NMOS来说,源/漏区160可以是N型掺杂。源/漏区160可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成。在本实施例中,源/漏区160形成于SOI层100内部,在其他一些实施例中,源/漏区160可以是通过选择性外延生长所形成的提升的源漏极结构,其外延部分的顶部高于栅极堆叠底部(本说明书中所指的栅极堆叠底部意指栅极堆叠与SOI层100的交界线)。
执行步骤S102,以所述栅极结构200为掩模对半导体结构进行应力引发离子的注入,在栅极结构的两侧形成位于所述SOI衬底的BOX层110之下的应力引发区150。
参考图9,形成应力引发区150。首先以所述栅极结构200为掩模对所述接地层140进行碳注入,通过传统的离子注入工艺进行碳注入,控制其深度达到BOX层下方,从而形成应力引发区150。之后进行高温退火,以修复由于注入引起的损伤,例如可以采用激光退火、闪光退火等。在一个实施例中,可以采用瞬间退火工艺对半导体结构进行退火,例如在大约1200℃以上的高温下进行激光退火。
如图所示,应力引发区150形成在所述形成在栅极结构两侧的BOX层下方的衬底内。应力引发区150的形成可以为沟道区引入拉应力,显著提高n型半导体器件的性能。
本发明提供的半导体结构及其制造方法在超薄SOI衬底上的接地层中形成应力引发区,为半导体器件的沟道提供了有利应力,在减小短沟道效应的同时,显著提高了半导体器件的性能。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (13)
1.一种半导体结构的制造方法,包括:
(a)提供SOI衬底,并在所述SOI衬底上形成栅极结构(200);
(b)以所述栅极结构(200)为掩模对半导体结构进行应力引发离子的注入,在栅极结构的两侧形成位于所述SOI衬底的BOX(110)层之下的应力引发区(150)。
2.根据权利要求1所述方法,还包括:
在步骤(a)中形成所述栅极结构(200)后,在所述栅极结构(200)的侧壁上形成侧墙(210)。
3.根据权利要求1所述方法,还包括:
在步骤(a)之前通过离子注入和退火工艺形成接地层(140)。
4.根据权利要求1所述方法,其特征在于,所述SOI衬底的SOI层(100)的厚度范围为5~20nm。
5.根据权利要求1所述方法,其特征在于,所述BOX层(110)的厚度范围为5~30nm。
6.根据权利要求1所述方法,还包括在形成栅极结构(200)之后在栅极结构的两侧形成源/漏延伸区(170)。
7.根据权利要求2所述方法,还包括在所述栅极结构(200)的侧壁形成侧墙(210)之后在所述栅极结构(200)的两侧形成源漏区(160)。
8.根据权利要求1所述方法,还包括在进行应力引发离子的注入之后进行退火。
9.根据权利要求1所述方法,其中应力引发离子为碳离子。
10.根据权利要求1所述方法,其中栅极结构(200)为替代栅工艺中的伪栅结构。
11.一种半导体结构,包括:
SOI衬底,包括SOI层(100)、BOX层(110)和体硅层(130);
形成于SOI层(100)中的源/漏区(160)和在源/漏区(160)下方的通过离子注入到体硅层中形成的应力引发区(150)。
12.根据权利要求11所述的半导体结构,其特征在于,所述SOI衬底的SOI层(100)的厚度范围为5~20nm。
13.根据权利要求11所述的半导体结构,其特征在于,所述BOX层(110)的厚度范围为5~30nm。
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US6887751B2 (en) * | 2003-09-12 | 2005-05-03 | International Business Machines Corporation | MOSFET performance improvement using deformation in SOI structure |
CN1914722A (zh) * | 2004-03-31 | 2007-02-14 | 国际商业机器公司 | 制作应变绝缘体上硅结构的方法及用此方法形成的绝缘体上硅结构 |
CN1728402A (zh) * | 2004-07-30 | 2006-02-01 | 国际商业机器公司 | 超薄型本体超陡后退阱(ssrw)场效应晶体管器件 |
CN101060134A (zh) * | 2006-04-20 | 2007-10-24 | 国际商业机器公司 | Mosfet器件及其制造方法 |
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US9263581B2 (en) | 2016-02-16 |
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US20150076602A1 (en) | 2015-03-19 |
CN103377930A (zh) | 2013-10-30 |
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