CN104576376A - 一种mosfet结构及其制造方法 - Google Patents

一种mosfet结构及其制造方法 Download PDF

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CN104576376A
CN104576376A CN201310476449.0A CN201310476449A CN104576376A CN 104576376 A CN104576376 A CN 104576376A CN 201310476449 A CN201310476449 A CN 201310476449A CN 104576376 A CN104576376 A CN 104576376A
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gate stack
substrate
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source
semiconductor layer
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尹海洲
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Institute of Microelectronics of CAS
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Priority to US14/905,440 priority patent/US9496342B2/en
Priority to PCT/CN2013/085664 priority patent/WO2015051564A1/zh
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Abstract

本发明提供一种MOSFET结构及其制造方法，所述制造方法包括：a.提供衬底（100）、伪栅叠层（200）、外延保护层（101）以及牺牲侧墙（205）；b.用掩膜板覆盖伪栅叠层（200）及其一侧的衬底（100），在衬底上形成空位（102）；c.在所述半导体结构上逐层生长半导体层（300），以填充空位(102)；d.去除所述外延保护层（101）以及牺牲侧墙（205），在所述半导体结构上依次形成源漏扩展区、侧墙（201）、源漏区以及层间介质层（500）；e.去除伪栅叠层（200）以形成伪栅空位，在所述伪栅空位中形成栅极叠层。本发明的方法所制造的MOSFET结构可以显著减小漏端感应势垒降低效应对器件性能的影响。

Description

一种MOSFET结构及其制造方法
技术领域
本发明涉及一种MOSFET结构及其制造方法。更具体而言，涉及一种用于降低关态漏电流的MOSFET结构及其制造方法。
技术背景
在MOSFET结构中，为了增强栅对沟道的控制能力，更好的抑制短沟道效应，希望沟道部分越窄越好。然而，在沟道厚度小于10nm以后，由于载流子迁移率随着沟道厚度的减小而降低，器件性能会受到较严重的影响，特别地，在靠近源端的沟道部分所受影响尤为严重，而在漏端，由于高场饱和作用的影响，沟道宽度对迁移率的影响不起主要作用。
漏端感应势垒降低效应（Drain Induction Barrier Lower）是短沟道器件中存在的一种非理想效应，即当沟道长度减小，源漏电压增加而使得源区和漏区PN结耗尽区靠近时，沟道中的电力线可以从漏区穿越到源区，并导致源端势垒高度降低，从而使源区注入沟道的载流子数目增加，漏端电流增大。随着沟道长度的进一步减小，DIBL的影响越来越严重，使晶体管阈值电压降低，器件电压增益下降，同时也限制了超大规模集成电路集成度的提高。
因此，如何提供一种可有效减小MOS器件DIBL电流的MOS管制作方法，已成为业界亟待解决的技术问题。
发明内容
本发明提供了一种有效减小DIBL电流的MOSFET制作方法，有效抑制了器件的短沟道效应，提高了器件性能。具体地，本发明提供的制造方法包括以下步骤：
a.提供衬底、伪栅叠层、外延保护层以及牺牲侧墙；
b.用掩膜板覆盖伪栅叠层及其一侧的衬底，在衬底上形成空位；
c.在所述半导体结构上逐层生长半导体层，以填充空位；
d.去除所述外延保护层以及牺牲侧墙，在所述半导体结构上依次形成源漏扩展区、侧墙、源漏区以及层间介质层；
e.去除伪栅叠层以形成伪栅空位，在所述伪栅空位中依次沉积栅极介质层、功函数调节层和栅极金属层。
其中，优选的，所述空位位于源端一侧的衬底上，形成所述空位的方法是各向异性刻蚀与各向同性刻蚀的组合。
其中，所述空位与伪栅叠层重叠的长度L小于或等于伪栅叠层宽度。
其中，所述半导体层的禁带宽度从靠近源端一侧到至靠近漏端一侧逐渐增大；
其中，所述半导体层的材料为硅锗；
其中，所述半导体层从靠近源端一侧到至靠近漏端一侧硅锗中硅的比例逐渐增大。
相应地，本发明还提供一种MOSFET结构，包括：
衬底；
位于所述衬底上方的栅极叠层；
位于所述栅极叠层两侧衬底中的源漏区；
覆盖所述源漏区的层间介质层；
以及位于所述栅极叠层下方及其一侧的衬底中的半导体层，其中，构成所述半导体层的材料禁带宽度沿着沟道方向从靠近源端一侧到至靠近漏端一侧逐渐增大。
其中，所述半导体层位于栅极叠层下方的长度L小于等于栅极叠层的宽度。
根据本发明所述的半导体结构，采用禁带宽度较小的硅锗代替原沟道材料硅，且通过调节硅锗材料中硅锗的比例，使沟道材料的禁带宽度从源端到漏端逐渐增加，有效地增大了漏端势垒和源端势垒之间的高度差，减小了DIBL所引起的漏电流。同时，由于漏端一侧的半导体材料禁带宽度大于源端一侧的半导体禁带宽度，本发明还能有效的抑制GIDL效应所引起的漏电流。因此，通过本发明中的半导体结构，可以有效的减小器件漏电流，优化器件性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1～图6为根据本发明的一个具体实施方式中MOSFET各个制造阶段的剖面图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
参见图6，本发明提供了一种MOSFET结构，包括：衬底100；位于所述衬底100上方的栅极叠层600；位于所述栅极叠层600两侧衬底中的源漏区400；覆盖所述源漏区的层间介质层500；以及位于所述栅极叠层600下方及其一侧的衬底100中的半导体层300，其中，构成所述半导体层300的材料禁带宽度沿着沟道方向从靠近源端一侧到至靠近漏端一侧逐渐增大。
半导体沟道区位于衬底的表面，其优选材料为单晶硅或单晶锗合金薄膜，其厚度为5～20nm。该区域是极轻掺杂甚至未掺杂的。在掺杂的情况下，其掺杂类型与源漏区掺杂相反。
源区和漏区分别位于栅极叠层600两侧，衬底上方的半导体层内。源区的厚度大于漏区的厚度。靠近源区一侧的沟道部分厚度大于靠近漏端一侧的沟道厚度，为10nm～60nm。
所述半导体层300位于栅极叠层600下方，其长度L小于等于栅极叠层600的宽度。采用禁带宽度渐变的材料替换原衬底材料，具体的，采用禁带宽度较小的硅锗代替原沟道材料硅，且通过调节硅锗材料中硅锗的比例，使沟道材料的禁带宽度从源端到漏端逐渐增加，有效地增大了漏端势垒和源端势垒之间的高度差，减小了DIBL所引起的漏电流。同时，由于漏端一侧的半导体材料禁带宽度大于源端一侧的半导体禁带宽度，本发明还能有效的抑制GIDL效应所引起的漏电流。
下面结合附图对本发明的制作方法进行详细说明，包括以下步骤。需要说明的是，本发明各个实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参见图1，首先提供半导体衬底100，并在所述衬底100上形成伪栅结构200。所述伪栅结构200可以是单层的，也可以是多层的。伪栅结构200可以包括聚合物材料、非晶硅、多晶硅或TiN，厚度可以为10nm～200nm。本实施例中，伪栅结构包括多晶硅和二氧化，具体的，采用化学汽相淀积的方法在栅极空位中填充多晶硅，其高度略低于侧墙10～20nm，接着在多晶硅上方形成一层二氧化硅介质层，形成方法可以是外延生长、氧化、CVD等。接着采用常规CMOS工艺光刻和刻蚀所淀积的伪栅叠层形成栅电极图形。硅锗沟道层101中被栅极介质层所覆盖的部分形成晶体管的沟道区。需说明地是，以下若无特别说明，本发明实施例中各种介质材料的淀积均可采用上述所列举的形成栅介质层相同或类似的方法，故不再赘述。
接下来，在所述半导体结构上形成外延保护层101，覆盖所述衬底100和伪栅叠层200。外延保护层101的作用是在后续步骤中进行外延生长时，保护漏端一侧的半导体结构上不形成生成物。具体的，在本发明中，所述外延保护层101的材料是二氧化硅，其厚度为5～20nm。
接下来，在栅极堆叠的侧壁上形成牺牲侧墙102，用于将栅极隔开。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术再栅电极两侧形成宽度为35nm～75nm的氮化硅牺牲侧墙102。牺牲侧墙102还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。牺牲侧墙102可以具有多层结构。牺牲侧墙102还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
上述步骤完成之后的半导体结构剖面图如图1所示。
接下来，用掩膜板或光刻胶206覆盖伪栅叠层200及其一侧的衬底100，在衬底上形成空位102，如图2所示。具体的，在所述半导体结构上覆盖光刻胶206，并通过显影、曝光等步骤，去除位于源端一侧半导体结构上的光刻胶206，暴露出衬底100。接下来，对所述半导体结构进刻蚀行以形成空位102。所述空位102位于源端一侧的衬底上，其与伪栅叠层200重叠的长度L小于或等于伪栅叠层宽度。所述刻蚀方法是各向异性刻蚀和各向同性刻蚀的组合。在本实施例中，由于所述空位位于源端一侧的半导体结构中，因此靠近漏端的沟道中材料的禁带宽度大于靠近源端的沟道中材料的禁带宽度，可以有效地减小GIDL所引起的漏电流。
接下来，在所述半导体结构上逐层生长半导体层300，以填充空位102，如图3所示。其中，所述半导体层300的材料为硅锗，其禁带宽度从靠近源端一侧到至靠近漏端一侧逐渐增大，即硅锗中硅的比例逐渐增大。具体的，采用选择性外延的方法，在所述空位102中逐层生长硅锗材料，由于外延保护层101的存在，生长的硅锗只存在于空位102中而不会在半导体漏区和伪栅表面进行生长。可通过调节硅锗材料的层数和比例来控制沟道区材料的禁带宽度变化，得到所需要的能带结构。由于漏端的半导体材料中硅的比例逐渐增大，因此所述半导体层300的禁带宽度从靠近源端一侧到至靠近漏端一侧逐渐增大，有效地增大了漏端势垒和源端势垒之间的高度差，减小了DIBL所引起的漏电流。
接下来，去除位于所述半导体结构上的外延保护层101和牺牲侧墙205，露出伪栅结构200，如图4所示。接下来，对伪栅结构200两侧的衬底进行掺杂，以形成源漏扩展区，还可以进行Halo注入，以形成Halo注入区。其中源漏扩展区的杂质类型与器件类型一致，Halo注入的杂质类型与器件类型相反。
可选地，在栅极堆叠的侧壁上形成侧墙201，用于将栅极隔开。具体的，用LPCVD淀积40nm～80nm厚的牺牲侧墙介质层氮化硅，接着用会客技术再栅电极两侧形成宽度为35nm～75nm的氮化硅侧墙201。侧墙201还可以由氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙201可以具有多层结构。侧墙201还可以通过包括沉积刻蚀工艺形成，其厚度范围可以是10nm-100nm，如30nm、50nm或80nm。
接下来，在所述半导体结构上淀积一层厚度为10nm～35nm厚的二氧化硅介质层，并以该介质层为缓冲层，离子注入源漏区。对P型晶体而言，掺杂剂为硼或弗化硼或铟或镓等。对N型晶体而言，掺杂剂为磷或砷或锑等。掺杂浓度为5e1019cm-3～1e1020cm-3。源漏区掺杂完成后，在所述半导体结构上形成层间介质层500。在本实施例中，层间介质层500的材料为二氧化硅。淀积完层间介质层500的半导体结构如图5所示。
接下来，去除所述伪栅结构200，形成伪栅空位。去除伪栅结构200可以采用湿刻和/或干刻除去。在一个实施例中，采用等离子体刻蚀。
接下来，如图6所示，在栅极空位中形成栅极叠层600。栅极叠层600可以只为金属栅极，也可以为金属/多晶硅复合栅极，其中多晶硅上表面上具有硅化物。
具体的，优选的，在伪栅空位中栅极介质层601，接下来沉积功函数调节层602，之后再在功函数金属层之上形成栅极金属层603。所述栅极介质层601可以是热氧化层，包括氧化硅、氮氧化硅；也可为高K介质，例如HfAlON、HfSiAlON、HfTaAlON、HfTiAlON、HfON、HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合，栅极介质层601的厚度可以为1nm-10nm，例如3nm、5nm或8nm。可以采用热氧化、化学气相沉积（CVD）或原子层沉积（ALD）等工艺来形成栅极介质层601。
功函数金属层可以采用TiN、TaN等材料制成，其厚度范围为3nm～15nm。金属导体层可以为一层或者多层结构。其材料可以为TaN、TaC、TiN、TaAlN、TiAlN、MoAlN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax中的一种或其组合。其厚度范围例如可以为10nm-40nm，如20nm或30nm。
最后进入常规CMOS厚道工艺，包括点击钝化层、开接触孔以及金属化等，即可制的所述超薄SOI MOS晶体管。
在本发明中，采用禁带宽度更大的硅锗代替原沟道材料硅，且通过调节硅锗材料中硅锗的比例，使沟道材料的禁带宽度从源端到漏端逐渐下降，有效地增大了漏端势垒和源端势垒之间的高度差，减小了DIBL所引起的漏电流。同时，由于所述空位位于源端一侧的半导体结构中，因此靠近漏端的沟道中材料的禁带宽度大于靠近源端的沟道中材料的禁带宽度，可以有效地减小GIDL所引起的漏电流。因此，通过本发明中的半导体结构，可以有效的减小器件漏电流，优化器件性能。
因此，通过本发明中的半导体结构，可以有效的减小器件漏电流，优化器件性能。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (11)

1.一种MOSFET制造方法，包括：
a.提供衬底（100）、伪栅叠层（200）、外延保护层（101）以及牺牲侧墙（205）；
b.用掩膜板覆盖伪栅叠层（200）及其一侧的衬底（100），在衬底上形成空位（102）；
c.在所述半导体结构上逐层生长半导体层（300），以填充空位(102)；
d.去除所述外延保护层（101）以及牺牲侧墙（205），在所述半导体结构上依次形成源漏扩展区、侧墙（201）、源漏区以及层间介质层（500）；
e.去除伪栅叠层（200）以形成伪栅空位，在所述伪栅空位中形成栅极叠层。
2.根据权利要求1所述的制造方法，其特征在于，优选地，所述空位（102）位于源端一侧的衬底上。
3.根据权利要求1或2所述的制造方法，其特征在于，所述形成空位（102）的方法是各向异性刻蚀与各向同性刻蚀的组合。
4.根据权利要求1、2或3所述的制造方法，其特征在于，所述空位（102）与伪栅叠层（200）重叠的长度L小于或等于伪栅叠层宽度。
5.根据权利要求1所述的制造方法，其特征在于，所述半导体层（300）的禁带宽度从靠近源端一侧到至靠近漏端一侧逐渐增大。
6.根据权利要求1或5所述的制造方法，其特征在于，所述半导体层（300）的材料为硅锗。
7.根据权利要求6所述的制造方法，其特征在于，所述半导体层（300）从靠近源端一侧到至靠近漏端一侧硅锗中硅的比例逐渐增大。
8.一种MOSFET结构，包括：
衬底（100）；
位于所述衬底（100）上方的栅极叠层（600）；
位于所述栅极叠层（600）两侧衬底中的源漏区（400）；
覆盖所述源漏区的层间介质层（500）；
以及位于所述栅极叠层（600）下方及其一侧的衬底（100）中的半导体层（300），其中，构成所述半导体层（300）的材料禁带宽度沿着沟道方向从靠近源端一侧到至靠近漏端一侧逐渐增大。
9.根据权利要求8所述的MOSFET结构，其特征在于，所述半导体层（300）位于栅极叠层（600）下方的长度L小于等于栅极叠层（600）的宽度。
10.根据权利要求8所述的MOSFET结构，其特征在于，所述半导体层（300）的材料为硅锗。
11.根据权利要求8所述的MOSFET结构，其特征在于，所述半导体层（300）从靠近源端一侧到至靠近漏端一侧硅锗中硅的比例逐渐增大。
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