WO2013155760A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2013155760A1
WO2013155760A1 PCT/CN2012/076260 CN2012076260W WO2013155760A1 WO 2013155760 A1 WO2013155760 A1 WO 2013155760A1 CN 2012076260 W CN2012076260 W CN 2012076260W WO 2013155760 A1 WO2013155760 A1 WO 2013155760A1
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layer
soi
gate structure
semiconductor structure
source
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PCT/CN2012/076260
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English (en)
French (fr)
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朱慧珑
尹海洲
骆志炯
梁擎擎
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中国科学院微电子研究所
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Priority to US14/394,802 priority Critical patent/US9263581B2/en
Publication of WO2013155760A1 publication Critical patent/WO2013155760A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • a common method of increasing stress is to operate in the source and drain regions to form tensile or compressive stresses on the channel.
  • the transistor channel is oriented along the ⁇ 110 ⁇ of silicon.
  • the mobility of the holes is increased; and when the channel is subjected to the channel along the channel.
  • the tensile stress in the direction and/or the compressive stress in the direction perpendicular to the channel increases, the mobility of electrons increases. Therefore, stress is introduced in the channel region of the semiconductor device, and the performance of the device can be improved.
  • SOI substrates instead of silicon substrates can also achieve short channel effects and improved device performance. Effect.
  • the Silicon On Insulator (SOI) technology introduces a buried oxide layer between the top bulk silicon layer and the subterranean silicon layer.
  • SOI materials have advantages that are incomparable to bulk silicon: dielectric isolation of components in integrated circuits can be achieved, and parasitic latch-up effects in bulk silicon CMOS circuits are completely eliminated;
  • the integrated circuit also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, short channel effect and special application to low voltage and low power circuits. Therefore, it can be said that SOI will become a deep submicron low voltage. Mainstream technology for low-power integrated circuits.
  • Ultra-thin SOI provides an alternative means of controlling short channel effects through a natural electrostatic barrier established by a silicon dielectric interface.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising:
  • the present invention also provides a semiconductor structure, the semiconductor structure comprising: a SOI substrate, comprising an SOI layer, a BOX layer, and a bulk silicon layer;
  • the semiconductor structure and the method of fabricating the same provided on the ultra-thin SOI substrate form a ground layer, and then performing ion implantation and annealing operations in the ground layer to form a stress inducing region, which is a semiconductor device.
  • the channel provides favorable stresses that help to improve the performance of the semiconductor device.
  • FIG. 1 is a flow chart showing a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to 9 are cross-sectional structural views showing respective stages of fabrication of the semiconductor structure in the process of fabricating a semiconductor structure in accordance with the flow shown in Fig. 1 in accordance with an embodiment of the present invention.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • the components illustrated in the drawings are not necessarily drawn to scale. The description of the known components and processing techniques and processes is omitted to avoid unnecessarily limiting the present invention. [0019] Since the semiconductor structure provided by the present invention has several preferred structures, a preferred structure is provided below and outlined.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 9 illustrates a semiconductor structure including an SOI substrate, a ground layer 140, a gate structure 200, source/drain regions 160, source/drain extension regions 170, and stress inducing regions 150,
  • the SOI substrate includes an SOI layer 100, a BOX layer 110, and a bulk silicon layer 130;
  • the gate structure 200 is formed on the SOI layer 100;
  • the source/drain region 160 and the source/drain extension region 170 are formed in the SOI layer 100;
  • the ground layer 140 is located in the bulk silicon layer 130, below the BOX layer 110;
  • the stress inducing region 150 is formed under the BOX layer 110 in the SOI substrate on both sides of the gate structure 200.
  • sidewall spacers 210 are also formed on both sides of the gate structure 200.
  • the SOI substrate has at least three layers of structures: a bulk silicon layer 130, a BOX layer 110 over the bulk silicon layer 130, and an SOI layer 100 overlying the BOX layer 110.
  • the material of the BOX layer 110 may be a crystalline or amorphous oxide, a nitride or any combination thereof.
  • Si0 2 is usually selected.
  • the material of the SOI layer 100 is a single crystal silicon, a Ge or a III-V compound such as SiC, gallium arsenide, indium arsenide or indium phosphide.
  • the SOI substrate selected in the present invention is an SOI substrate having an ultrathin SOI layer 100 and an ultrathin BOX layer 110, wherein the ultrathin SOI layer 100 has a thickness ranging from 5 to 20 nm, such as 5 nm, 15 nm or 20 nm;
  • the thickness of layer 110 ranges from 5 to 30 nm, such as 5 nm, 20 nm or 30 nm.
  • an isolation region 120 may also be formed in the SOI substrate for dividing the SOI layer 100 into separate regions for subsequent processing to form a transistor structure.
  • the material of the isolation region 120 is an insulating material, and for example, SiO 2 , Si 3 N 4 or a combination thereof may be selected.
  • the width of the isolation region 120 can be determined by the design requirements of the semiconductor structure.
  • the gate structure 200 includes a gate dielectric layer and a gate stack; in the gate-last process, the gate structure 200 may include a dummy gate and a gate dielectric layer carrying a dummy gate or a dummy gate removal A replacement gate stack structure is then formed.
  • the spacer 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the spacer 210 may be formed by a deposition-etching process having a thickness ranging from about 10 nm to 100 nm.
  • the source/drain regions 160 and the source/drain extension regions 170 are formed by ion implantation in the SOI layer 100.
  • source/drain regions 160 and source/drain extension regions 170 may be P-type doped
  • source/drain regions 160 and source/drain extension regions 170 may be N-type doped.
  • the ground layer 140 is formed in the bulk silicon layer 130.
  • n-type and p-type doping may be employed for the PFET and the NFET, respectively, or p-type and n-type doping may be employed, respectively.
  • the stress inducing region 150 is formed in the ground layer 140 by carbon doping. The position of the stress inducing region 150 is below the source/drain region 160 (via the BOX layer), and tensile stress can be introduced into the channel region to increase electron mobility. Wenshan NFET performance.
  • FIG. 1 is a flow chart of a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention, the method comprising:
  • Step S101 providing an SOI substrate, and forming a gate structure 200 on the SOI substrate;
  • Step S102 performing stress-initiated ion implantation on the semiconductor structure by using the gate structure 200 as a mask, and forming a stress inducing region 150 under the BOX layer 110 of the SOI substrate on both sides of the gate structure.
  • FIG. 2 to FIG. 9 are diagrams showing the manufacture of the semiconductor structure in the process of fabricating a semiconductor structure according to the flow shown in FIG. 1 according to an embodiment of the present invention. Schematic diagram of the cross-sectional structure of the stage.
  • the drawings of the various embodiments of the present invention are intended to be illustrative only and not necessarily to scale.
  • step S101 is performed to provide an SOI substrate, and a gate structure 200 is formed on the SOI substrate.
  • the SOI substrate has at least three layers of structures: a bulk silicon layer 130, a BOX layer 110 over the bulk silicon layer 130, and an SOI overlying the BOX layer 110.
  • Layer 100 The material of the BOX layer 110 is generally selected from Si0 2 .
  • the material of the SOI layer 100 is a single crystal silicon, a Ge or a III-V compound such as SiC, gallium arsenide, indium arsenide or indium phosphide.
  • the SOI substrate selected in the present invention is an SOI substrate having an ultra-thin SOI layer 100 and an ultra-thin BOX layer 110, wherein the SOI layer 100 has a thickness ranging from 5 to 20 nm, for example, 5 ⁇ , 15 ⁇ , and 20 ⁇ ;
  • the thickness of 110 ranges from 5 to 30 nm, such as 5 nm, 20 nm, and 30 nm.
  • An isolation region 120 is further formed in the bottom of the SOI for dividing the SOI layer 100 into separate regions for subsequent processing to form a transistor structure, as shown in FIG.
  • Material of isolation zone 120 The material is an insulating material, for example, Si0 2 , Si 3 N 4 or a combination thereof may be selected, and the width of the isolation region 120 may be determined according to the design requirements of the semiconductor structure.
  • the ground layer 140 is formed by ion implantation, with reference to FIG.
  • the implantation energy is controlled such that the ground layer is formed under the BOX layer 110.
  • n-type and p-type doping may be employed for the PFET and the NFET, respectively, or in other embodiments, p-type and n-type doping may be employed, respectively.
  • a gate structure 200 is formed on the SOI substrate (specifically, on the SOI layer 100).
  • the formation process of the gate structure 200 is, for example: formation a gate dielectric layer covering the SOI layer 100, a gate metal layer covering the gate dielectric layer, a gate electrode layer covering the gate metal layer, an oxide layer covering the gate electrode layer, a nitride layer covering the oxide layer, and a nitrogen covering layer
  • the layer is patterned and used to etch the photoresist layer of the gate stack.
  • the material of the gate dielectric layer may be a thermal oxide layer, including silicon oxide or silicon oxynitride, or may be high K, such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La.
  • the material of the gate metal layer may be selected from TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x
  • the material of the gate electrode layer may be Poly-Si, and the thickness thereof is between 20 nm and 80 nm
  • the material of the oxide layer is Si0 2 , and the thickness thereof
  • the material of the nitride layer is Si 3 N 4 , and the thickness thereof is between 10 nm and 50 nm
  • the material of the photoresist layer may be an ethylenic monomer material, a material containing an azide quinone compound or a poly Ethylene laurate material, etc.
  • the above multilayer structure may be subjected to chemical vapor deposition (CVD), high-density plasma CVD, ALD (atomic layer deposition), plasma enhanced atomic layer deposition (PEALD). ), pulsed laser deposition (PLD) or other suitable method is sequentially formed on the SOI layer 100.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PLD pulsed laser deposition
  • the above multilayer structure can be etched to form a gate structure 200 as shown in FIG. 3 (gate lines are formed on the SOI substrate).
  • the gate structure 200 includes a dummy gate and a gate dielectric layer carrying a dummy gate, and a replacement gate process can be performed in a subsequent step to remove the dummy gate to form a desired gate stack structure.
  • annealing is performed to control the doping profile of the ground layer 140 to adjust the turn-on voltage of the device.
  • source/leakage is formed in the SOI layer 100 by low energy implantation.
  • Stretching zone 170 see Figure 6.
  • P-type or N-type dopants or impurities may be implanted into the SOI layer 100. That is, if the semiconductor device to be fabricated is an NMOS, the SOI layer 100 is doped with an N-type impurity such as boron and indium. If the semiconductor device is a PMOS, the SOI layer 100 is doped with a P-type impurity such as arsenic and phosphorus.
  • the semiconductor structure is then annealed to activate doping in the source/drain extension 170. In one embodiment, source/drain extension regions 170 may also not be formed.
  • sidewall spacers 210 are formed on sidewalls of the gate structure 200 for separating the gate structures 200, with reference to FIG.
  • the spacer 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the spacer 210 may be formed by a deposition-etching process having a thickness ranging from about 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • the source/drain regions 160 are formed after the sidewall spacers 210 are formed. As shown in FIG. 8, the source/drain regions 160 may be formed by implanting P-type or N-type dopants or impurities into the SOI layer 100. For example, for PMOS, the source/drain regions 160 may be P-type doped. For the NMOS, the source/drain regions 160 may be N-type doped. Source/drain regions 160 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes. In the present embodiment, the source/drain regions 160 are formed inside the SOI layer 100. In other embodiments, the source/drain regions 160 may be elevated source and drain structures formed by selective epitaxial growth, and the epitaxial portion thereof. The top of the gate stack is higher than the bottom of the gate stack (the bottom of the gate stack referred to in this specification means the boundary between the gate stack and the SOI layer 100).
  • Step S102 is performed to implant stress-induced ions into the semiconductor structure by using the gate structure 200 as a mask, and stress formation under the BOX layer 110 of the SOI substrate is formed on both sides of the gate structure. District 150.
  • a stress inducing region 150 is formed.
  • the ground layer 140 is carbon-injected by using the gate structure 200 as a mask, carbon implantation is performed by a conventional ion implantation process, and the depth is controlled to be below the BOX layer, thereby forming a stress inducing region 150.
  • high temperature annealing is performed to repair damage due to implantation, and for example, laser annealing, flash annealing, or the like can be employed.
  • the semiconductor structure can be annealed using a transient annealing process, such as laser annealing at a high temperature above about 1200 °C.
  • stress inducing regions 150 are formed in bulk silicon 130 below the BOX layer on either side of the gate structure.
  • the formation of the stress inducing region 150 may introduce tensile stress into the channel region to improve the performance of the n-type semiconductor device.
  • the dummy gate In the gate-last process, the dummy gate can be removed at this time and an alternate gate stack structure can be formed.
  • the semiconductor structure and the method of fabricating the same provided in the present invention form a stress inducing region in a ground layer on an ultrathin SOI substrate, which provides favorable stress for the channel of the semiconductor device, while reducing the short channel effect.
  • the carrier mobility of the n-type MOSFET is improved.

Abstract

一种半导体结构的制造方法，该方法包括：提供SOI衬底，并在SOI衬底上形成栅极结构（200）；以栅极结构（200）为掩模对半导体结构进行应力引发离子的注入，在栅极结构（200）的两侧形成位于SOI衬底的BOX层（110）之下的应力引发区。提供一种半导体结构。半导体结构及其制造方法在接地层形成应力引发区，应力引发区为半导体器件的沟道提供了有利应力，有助于提升半导体器件的性能。

Description

半导体结构及其制造方法
[0001]本申请要求了 2012月 4月 19日提交的、 申请号为 201210117019.5、 发明 名称为 "半导体结构及其制造方法" 的中国专利申请的优先权， 其全部内容 通过引用结合在本申请中。 技术械
[0002]本发明涉及半导体领域， 具体地说涉及一种半导体结构及其制造方法。 背景技术
[0003]随着半导体器件制造技术的发展， 具有更高性能和更强功能的集成电 路要求更大的元件密度， 而且各个部件、 元件之间或各个元件自身的尺寸、 大小和空间也需要进一步缩小， 因此半导体器件制造过程中对工艺控制的要 求较高。
[0004]半导体器件通过按比例缩小来实现工作速度的提升。 MOS晶体管的沟 道长度也在不断地按比例缩短， 但当 MOS晶体管的沟道长度变得非常短时， 所谓的短沟道效应（ SCE ) ,以及漏极感应势垒降低效应 ( Drain-Induced Barrier Lowering, DIBL ) 给半导体器件微型化设置了严重的障碍。
[0005] 由于短沟道效应会使器件性能劣化， 甚至无法正常工作， 因此减小短 沟道效应是半导体器件研究制造中的重要课题。 半导体器件内部的机械应力 被广泛地用于调节器件的性能， 通过在沟道施加应力的方法， 可以有效减小 短沟道效应。
[0006]常用的增加应力的方法是在源漏区进行操作， 以便在沟道上形成拉伸 或压缩应力。 例如， 在通用硅技术中， 晶体管沟道沿着硅的 { 110}取向。 在这 种布置中， 当沟道受到沿着沟道方向的压缩应力和 /或沿着与沟道垂直方向的 拉伸应力时， 空穴的迁移率提高； 而当沟道受到沿着沟道方向的拉伸应力和 / 或沿着与沟道垂直方向的压缩应力时， 电子的迁移率增高。 因此在半导体器 件的沟道区引入应力， 可以提高器件的性能。
[0007]使用 SOI衬底代替硅衬底也可以达到减小短沟道效应和提高器件性能 的效杲。 绝缘体上硅（Silicon On Insulator, SOI )技术是在顶部体硅层和村底 体硅层之间引入了一层埋氧层。 通过在绝缘体上形成半导体薄膜， SOI材料具 有了体硅所无法比拟的优点： 可以实现集成电路中元器件的介质隔离， 彻底 消除了体硅 CMOS电路中的寄生闩锁效应；采用这种材料制成的集成电路还具 有寄生电容小、 集成密度高、 速度快、 工艺简单、 短沟道效应小及特别适用 于低压低功耗电路等优势， 因此可以说 SOI将有可能成为深亚微米的低压、 低 功耗集成电路的主流技术。
[0008] 同时， SOI的异质结构为建造具有超薄硅体器件创造了机会。 通过由硅 电介质界面建立的天然静电屏障，超薄 SOI提供一种控制短沟道效应的可选手 段。
[0009] 目前， 有技术采用在超薄 SOI MOS晶体管（ Ultrathin-SOI MOSFET )的 超薄 BOX层之下形成一个接地层来减小短沟道效应， 并控制功耗。 但是要在 此种结构的半导体器件中引入较强的应力是比较困难的， 因此这种器件的性 能的提升受到限制。 发明内容
[0010]本发明的目的在于提供一种半导体结构及其制造方法， 通过在接地层 形成应力引发区， 对使用超薄 SOI衬底制造形成的半导体器件的沟道区引入有 利应力， 提高所述半导体器件的性能。
[0011]—方面， 本发明提供了一种半导体结构的制造方法， 该方法包括：
( a )提供 SOI村底， 并在所述 SOI衬底上形成栅极结构；
( b ) 以所述栅极结构为掩模对半导体结构进行应力引发离子的注入， 在 栅极结构的两侧形成位于所述 SOI村底的 BOX层之下的应力引发区。
[0012]相应地， 本发明还提供了一种半导体结构， 该半导体结构包括： SOI村底， 包括 SOI层、 BOX层和体硅层；
形成于 SOI层中的源 /漏区和在源 /漏区下方的体硅层中的应力引发区。
[0013]本发明提供的半导体结构及其制造方法在超薄 SOI村底上形成接地层， 之后在接地层中进行离子注入和退火操作， 形成应力引发区， 所述应力引发 区为半导体器件的沟道提供了有利应力， 有助于提升半导体器件的性能。 附图说明
[0014]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
图 1为根据本发明的半导体结构的制造方法的一个具体实施方式的流程 图；
图 2~图 9是根据本发明的一个具体实施方式按照图 1示出的流程制造半导 体结构过程中该半导体结构各个制造阶段的剖视结构示意图。
[0015]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0016]为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0017]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能 的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。
[0018]下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结 构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当 然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不 同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本 身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各 种特定的工艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺 的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征 之 "上" 的结构可以包括第一和第二特征形成为直接接触的实施例， 也可以 包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征 可能不是直接接触。 应当注意， 在附图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发 明。 [0019] 由于本发明提供的半导体结构具有几种优选结构， 下面提供一种优选 结构并进行概述。
[0020] 实施例一：
参考图 9, 图 9示出了一种半导体结构， 该半导体结构包括 SOI衬底、 接地 层 140、 栅极结构 200、 源 /漏区 160、 源 /漏延伸区 170和应力引发区 150, 其中： 所述 SOI村底包括 SOI层 100、 BOX层 110和体硅层 130;
所述栅极结构 200形成在所述 SOI层 100之上；
所述源 /漏区 160和源 /漏延伸区 170形成于所述 SOI层 100之中；
所述接地层 140位于所述体硅层 130中， 所述 BOX层 110的下方；
所述应力引发区 150形成在所述栅极结构 200两侧的所述 SOI衬底内 BOX 层 110的下方。
[0021]此外， 在栅极结构 200的两侧还形成侧墙 210。
[0022]所述 SOI衬底至少具有三层结构， 分别是： 体硅层 130、 体硅层 130之上 的 BOX层 110, 以及覆盖在 BOX层 110之上的 SOI层 100。 其中， 所述 BOX层 110 的材料可以选用晶体或者非晶体氧化物、 氮化物或其任意组合。 优选地， 通 常选用 Si02。 SOI层 100的材料是单晶硅、 Ge或 III- V族化合物 （如 SiC、 砷化 镓、 砷化铟或磷化铟等）。 本发明中选用的 SOI衬底是具有超薄 SOI层 100和超 薄 BOX层 110的 SOI衬底，其中超薄 SOI层 100的厚度范围为 5~20nm,例如 5nm、 15nm或 20nm;超薄 BOX层 110的厚度范围为 5~30nm,例如 5nm、 20nm或 30nm。
[0023]可选的， 还可以在 SOI衬底中还形成隔离区 120, 用于将所述 SOI层 100 分割为独立的区域， 用于后续加工形成晶体管结构所用。 隔离区 120的材料是 绝缘材料， 例如可以选用 Si02、 Si3N4或其组合。 隔离区 120的宽度可以视半导 体结构的设计需求决定。
[0024]在前栅工艺中， 栅极结构 200包括栅极介质层和栅极堆叠； 在后栅工艺 中， 栅极结构 200可以包括伪栅和承载伪栅的栅介质层或者是伪栅去除之后形 成的替代栅叠层结构。 侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适的材料形成。 侧墙 210可以具有多层结构。 侧墙 210可以通过沉积- 刻蚀工艺形成， 其厚度范围大约是 10nm-100nm。
[0025]在 SOI层 100内通过离子注入的方式形成源 /漏区 160和源 /漏延伸区 170。 例如， 对于 PMOS来说， 源 /漏区 160和源 /漏延伸区 170可以是 P型掺杂， 对于 NMOS来说， 源 /漏区 160和源 /漏延伸区 170可以是 N型掺杂。
[0026]接地层 140形成于体硅层 130内， 例如， 对于 PFET和 NFET可以分别采用 n型和 p型掺杂， 或者也可以分别采用 p型和 n型掺杂。 应力引发区 150采用碳掺 杂形成于接地层 140内。应力引发区 150的位置在源 /漏区 160的下方（隔着 BOX 层） ， 可以为沟道区引入拉应力， 提高电子的迁移率， ？文善 NFET的性能。
[0027]下文中将结合本发明提供的半导体结构的制造方法对上述实施例进行 进一步的阐述。
[0028]请参考图 1 , 图 1是根据本发明的半导体结构的制造方法的一个具体实 施方式的流程图， 该方法包括：
步骤 S101 , 提供 SOI衬底， 并在所述 SOI衬底上形成栅极结构 200;
步骤 S102, 以所述栅极结构 200为掩模对半导体结构进行应力引发离子的 注入， 在栅极结构的两侧形成位于所述 SOI衬底的 BOX层 110之下的应力引发 区 150。
[0029]下面结合图 2至图 9对步骤 S101至步骤 S102进行说明， 图 2至图 9是根据 本发明的一个具体实施方式按照图 1示出的流程制造半导体结构过程中该半 导体结构各个制造阶段的剖视结构示意图。 需要说明的是， 本发明各个实施 例的附图仅是为了示意的目的， 因此没有必要按比例绘制。
[0030]参考图 2~图8, 执行步骤 S101 , 提供 SOI衬底， 并在所述 SOI衬底上形成 栅极结构 200。
[0031]首先参考图 2, 其中， 所述 SOI村底至少具有三层结构， 分别是： 体硅 层 130、体硅层 130之上的 BOX层 110, 以及覆盖在 BOX层 110之上的 SOI层 100。 其中， 所述 BOX层 110的材料通常选用 Si02。 SOI层 100的材料是单晶硅、 Ge 或 III- V族化合物（如 SiC、砷化镓、砷化铟或磷化铟等）。本发明中选用的 SOI 衬底是具有超薄 SOI层 100和超薄 BOX层 110的 SOI衬底， 其中 SOI层 100的厚度 范围为 5~20nm, 例如 5匪、 15匪、 20匪； BOX层 110的厚度范围为 5~30nm, 例如 5nm、 20nm、 30nm。
[0032]之后在该 SOI村底中还形成隔离区 120, 用于将所述 SOI层 100分割为独 立的区域， 用于后续加工形成晶体管结构所用， 如图 3所示。 隔离区 120的材 料是绝缘材料， 例如可以选用 Si02、 Si3N4或其组合， 隔离区 120的宽度可以视 半导体结构的设计需求决定。
[0033]形成隔离区 120之后， 通过离子注入的方式形成接地层 140， 参考图 4。 控制注入能量使得所述接地层形成于 BOX层 110之下。 例如， 对于 PFET和 NFET可以分别采用 n型和 p型掺杂， 或者在其他的实施例中， 也可以分别采用 p型和 n型掺杂。
[0034]接下来参考图 5, 在所述 SOI衬底上 （具体而言是在 SOI层 100上） 形成 栅极结构 200, 在前栅工艺中， 该栅极结构 200的形成过程例如： 形成覆盖 SOI 层 100的栅极介质层、覆盖栅极介质层的栅金属层、覆盖栅金属层的栅电极层、 覆盖栅电极层的氧化物层、 覆盖氧化物层的氮化物层、 以及覆盖氮化物层并 用于绘图以刻蚀出栅极堆叠的光刻胶层。 其中， 栅极介质层的材料可以是热 氧化层，包括氧化硅或氮氧化硅，也可为高 K介廣，例如 Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 其 厚度在 lnm ~ 4nm之间； 栅金属层的材料可以选用 TaC、 TiN、 TaTbN、 TaErN, TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTa中的一种或其组合， 其厚度在 5nm ~ 20nm之间； 栅电极层的材料可以选用 Poly-Si， 其厚度在 20nm ~80nm之 间； 氧化物层的材料是 Si02, 其厚度在 5nm ~10nm之间； 氮化物层的材料是 Si3N4, 其厚度在 10nm ~50nm之间； 光刻胶层的材料可是烯类单体材料、 含有 叠氮醌类化合物的材料或聚乙烯月桂酸酯材料等。 上述多层结构中除所述光 刻胶层以外， 可以通过化学气相沉积（Chemical vapor deposition, CVD )、 高 密度等离子体 CVD、 ALD(原子层淀积）、等离子体增强原子层淀积（ PEALD )、 脉冲激光沉积 （PLD ) 或其他合适的方法依次形成在 SOI层 100上。 光刻胶层 构图后可以刻蚀上述多层结构形成如图 3所示的栅极结构 200 (在所述 SOI衬底 上形成栅极线） 。
[0035]在后栅工艺中， 栅极结构 200包括伪栅和承载伪栅的栅介质层， 可以在 随后的步骤中进行替代栅工艺， 移除伪栅以形成所需的栅极堆叠结构。
[0036]在栅极结构 200形成之后， 进行退火以控制接地层 140的摻杂分布， 以 便调节器件的开启电压。
[0037]在进行退火之后， 通过低能注入的方式在所述 SOI层 100中形成源 /漏延 伸区 170,参考图 6。可以向所述 SOI层 100中注入 P型或 N型掺杂物或杂质。即， 如杲要制作的半导体器件为 NMOS, 则向所述 SOI层 100中掺杂 N型杂质， 例如 硼和铟。 如果所述半导体器件为 PMOS, 则向所述 SOI层 100中掺杂 P型杂质， 例如砷和磷。 然后对所述半导体结构进行退火， 以激活源 /漏延伸区 170中的掺 杂。 在一个实施例中， 也可以不形成源 /漏延伸区 170。
[0038]随后，在栅极结构 200的侧壁上形成侧墙 210,用于将栅极结构 200隔开， 参考图 7。 侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适 的材料形成。 侧墙 210可以具有多层结构。 侧墙 210可以通过沉积 -刻蚀工艺形 成， 其厚度范围大约是 10nm~100nm, 如 30nm、 50nm或 80nm。
[0039]形成侧墙 210之后形成源 /漏区 160。 如图 8所示， 源 /漏区 160可以通过向 SOI层 100中注入 P型或 N型掺杂物或杂质而形成， 例如， 对于 PMOS来说， 源 / 漏区 160可以是 P型掺杂， 对于 NMOS来说， 源 /漏区 160可以是 N型掺杂。 源 / 漏区 160可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的方法形成。 在 本实施例中， 源 /漏区 160形成于 SOI层 100内部， 在其他一些实施例中， 源 /漏 区 160可以是通过选择性外延生长所形成的提升的源漏极结构， 其外延部分的 顶部高于栅极堆叠底部（本说明书中所指的栅极堆叠底部意指栅极堆叠与 SOI 层 100的交界线） 。
[0040]执行步骤 S102, 以所述栅极结构 200为掩模对半导体结构进行应力引发 离子的注入， 在栅极结构的两侧形成位于所述 SOI衬底的 BOX层 110之下的应 力引发区 150。
[0041]参考图 9, 形成应力引发区 150。 首先以所述栅极结构 200为掩模对所述 接地层 140进行碳注入， 通过传统的离子注入工艺进行碳注入， 控制其深度达 到 BOX层下方， 从而形成应力引发区 150。 之后进行高温退火， 以修复由于注 入引起的损伤， 例如可以采用激光退火、 闪光退火等。 在一个实施例中， 可 以采用瞬间退火工艺对半导体结构进行退火， 例如在大约 1200°C以上的高温 下进行激光退火。
[0042]如图所示，应力引发区 150形成在所述栅极结构两侧的 BOX层下方的体 硅 130中。 应力引发区 150的形成可以为沟道区引入拉应力， 改善 n型半导体器 件的性能。 [0043]在后栅工艺中， 这时可以将伪栅去除， 并形成替代栅叠层结构。
[0044]本发明提供的半导体结构及其制造方法在超薄 SOI村底上的接地层中 形成应力引发区， 为半导体器件的沟道提供了有利应力， 在减小短沟道效应 的同时， 提高了 n型 MOSFET的载流子迁移率。
[0045] 虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0046]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本 领域的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的 工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明 描述的对应实施例大体相同的功能或者获得大体相同的结果， 依照本发明可 以对它们进行应用。 因此， 本发明所附权利要求旨在将这些工艺、 机构、 制 造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 包括：
(a)提供 SOI衬底， 并在所述 SOI村底上形成栅极结构 （200) ；
(b) 以所述栅极结构 （200) 为掩模对半导体结构进行应力引发离子的 注入， 在栅极结构的两侧形成位于所述 SOI村底的 BOX ( 110) 层之下的应力 引发区 (150) 。
2. 根据权利要求 1所述方法， 还包括：
在步骤（a) 中形成所述栅极结构 （200)后， 在所述栅极结构 （200) 的 侧壁上形成侧墙 （210) 。
3. 根据权利要求 1所述方法， 还包括：
在步驟 )之前通过离子注入和退火工艺形成接地层（140) 。
4. 根据权利要求 3所述方法， 其中， 在所述接地层（ 140 )位于所述 SOI 衬底的 BOX ( 110)层之下的体硅层 （130) 中。
5. 根据权利要求 1所述方法， 所述 SOI衬底的 SOI层（ 100)的厚度范围为
5~20nm。
6. 根据权利要求 1所述方法， 所述 BOX层（ 110) 的厚度范围为 5~30nm。
7. 根据权利要求 1所述方法， 还包括在形成栅极结构（200)之后在栅极 结构的两侧形成源 /漏延伸区 （ 170 ) 。
8. 根据权利要求 2所述方法， 还包括在所述栅极结构（200)的侧壁形成 侧墙（210)之后在所述栅极结构 （200) 的两侧形成源漏区 （160) , 所述应 力引发区 （150)位于所述源漏区 （160) 的下方。
9. 根据权利要求 8所述方法 , 其中在形成源漏区 （ 160 )之后 , 所述方法 还包括： 去除所述栅极结构 （200) , 并形成替代栅结构。
10.根据权利要求 1所述方法， 还包括在进行应力引发离子的注入之后进 行退火。
11.根据权利要求 1所述方法， 其中应力引发离子为碳离子。
12.一种半导体结构， 包括：
SOI衬底， 包括 SOI层 （100) 、 BOX层（110)和体硅层 （130) ； 形成于 SOI层（100) 中的源 /漏区 （160)和在源 /漏区 （160) 下方的体硅 层中的应力引发区 （150) 。
13.根据权利要求 12所述的半导体结构， 所述 SOI衬底的 SOI层 （100) 的 厚度范围为 5~20nm。
14.根据权利要求 12所述的半导体结构， 所述 BOX层 （110) 的厚度范围 为 5~30nm。
15.根据权利要求 12所述的半导体结构， 还包括栅极结构 （200) ， 位于 所述 SOI层 （100) 上方， 且夹于所述源 /漏区 （160)之间。
16.根据权利要求 15所述的半导体结构， 还包括源漏延伸区 （170) ， 位 于所述栅极结构 （ 200 ) 两侧的 SOI层 ( 100) 中。
17.根据权利要求 12所述的半导体结构， 还包括接地层 （ 170) , 位于所 述 BOX层（110) 下的体硅层（130) 中。
18.根据权利要求 12所述的半导体结构， 所述应力引发区 （150) 中包含 碳离子。
19.根据权利要求 12所述的半导体结构， 所述半导体结构为 NMOSFET, 所述接地层为 n型或 p型掺杂。
PCT/CN2012/076260 2012-04-19 2012-05-30 半导体结构及其制造方法 WO2013155760A1 (zh)

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