JP2010118500A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】半導体基板2上にゲート絶縁膜21を介して形成されたゲート電極22と、ゲート電極22の側面に形成されたオフセットスペーサ13、23と、一方のオフセットスペーサ23の側面に形成されたゲート側壁27と、半導体基板2中のゲート絶縁膜21下に形成されたチャネル領域25と、半導体基板2内のチャネル領域25を挟む領域に形成され、チャネル領域25側に導電型不純物が偏析して形成されたエクステンション領域24aを有するソース・ドレイン領域24と、ソース・ドレイン領域24上にオフセットスペーサ13に接して形成されたシリサイド層16、及び、ゲート側壁27に接して形成されたシリサイド層26と、を有した半導体装置1とする。
【選択図】図1
Description
A Kinoshita et al., Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials Tokyo, 2004, pp.172-173.
(半導体装置1の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の断面図である。半導体装置1は
、半導体基板2上に素子分離領域3により電気的に分離されたMOSFET10を有する。
本発明の第1の実施の形態に係る半導体装置1は、非対称なソース/ドレイン電極を持つDSS構造のMOSFETである。この非対称DSS MOSFETによる効果を以下に示す従来のMOSFET、及び、DSS MOSFETと比較する。
(半導体装置の製造方法)
図2A(a)〜(d)、図2B(e)〜(h)は、本発明の実施の形態に係る半導体装置1の製造工程を示す断面図である。
に層間絶縁膜32を形成する。
本発明の第2の実施の形態に係る半導体装置1の製造方法によれば、異方性のDensify処理を行なうので、別途のフォトレジスト工程等が不要である。従って、フォトレジストの形成、除去等のプロセスの追加工程なしで第1の実施の形態に示したような非対称DSS MOSFETを製造することが可能となる。これにより、コスト増加を伴わずに、HP(High Performance)で、LSTP(Low Stand-by Power)のMOSFET、CMOSが製造可能となる。
本発明の第3の実施の形態に係る半導体装置の製造方法は、第2の実施の形態に係る半導体装置の製造方法とゲート側壁の改質処理工程が異なるのみであるので、この異なる改質処理工程について、以下に説明する。
本発明の第3の実施の形態に係る半導体装置1の製造方法によれば、異方性のAmorphous化処理を行なうので、別途のフォトレジスト工程等が不要である。従って、フォトレジストの形成、除去等のプロセスの追加工程なしで第1の実施の形態に示したような非対称DSS MOSFETを製造することが可能となる。これにより、コスト増加を伴わずに、HP(High Performance)で、LSTP(Low Stand-by Power)のMOSFET、CMOSが製造可能となる。
Claims (5)
- 半導体基板上にゲート絶縁膜を介して形成されたゲート電極、前記ゲート電極の両側面に形成されたスペーサ、一方の前記スペーサの側面に形成されたゲート側壁、前記半導体基板中の前記ゲート絶縁膜下に形成されたチャネル領域、前記チャネル領域の両側に形成され前記チャネル領域側に導電型不純物が偏析して形成されたエクステンション領域を有するソース・ドレイン領域、および前記ソース・ドレイン領域上に形成されたシリサイド領域を有し、
前記ソース・ドレイン領域のソース側の前記シリサイド領域とドレイン側の前記シリサイド領域が、ゲート電極に対して非対称に形成されていることを特徴とする半導体装置。 - 前記ゲート側壁は、前記ソース・ドレイン領域のドレイン側にのみ形成され、前記ソース・ドレイン領域のソース側の前記シリサイド領域が前記スペーサに接して形成されると共に、ドレイン側の前記シリサイド領域が前記スペーサから離間して形成されていることを特徴とする請求項1に記載の半導体装置。
- 半導体基板上のトランジスタ領域に、ゲート電極をゲート絶縁膜を介して形成する工程と、
前記ゲート電極の両側面に、スペーサをそれぞれ形成する工程と、
前記スペーサ、及び、前記ゲート電極をマスクとして用いて、前記半導体基板上の前記トランジスタ領域に不純物を注入して、ソース・ドレイン領域のエクステンション領域を形成する工程と、
前記スペーサの側面に、ゲート側壁を形成する工程と、
前記スペーサ、及び、前記ゲート電極をマスクとして用いて、前記ソース・ドレイン領域のソース側又はドレイン側のいずれか一方の前記ゲート側壁に異方性の改質処理を施す工程と、
前記ソース側の前記ゲート側壁を選択的に剥離する工程と、
前記改質処理を施した前記ゲート側壁を剥離した後、前記半導体基板の前記トランジスタ領域の前記スペーサの両側の露出した領域に、シリサイド層を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記異方性の改質処理は、イオン注入、プラズマドーピング、またはレーザ照射の少なくともいずれか1つを用いたDensify処理であり、前記ドレイン側の前記ゲート側壁に施されることを特徴とする請求項3に記載の半導体装置。
- 前記異方性の改質処理は、イオン注入、プラズマドーピング、またはレーザ照射の少なくともいずれか1つを用いたAmorphous化処理であり、前記ソース側の前記ゲート側壁に施されることを特徴とする請求項3に記載の半導体装置。
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KR101346005B1 (ko) | 2006-07-28 | 2013-12-31 | 프리스케일 세미컨덕터, 인크. | 데이터 저장 회로용 비대칭을 가진 트랜지스터 |
JP2014514757A (ja) * | 2011-03-28 | 2014-06-19 | 日本テキサス・インスツルメンツ株式会社 | 化学的に改変されたスペーサ表面を有する集積回路 |
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US8946724B1 (en) | 2010-06-02 | 2015-02-03 | Hrl Laboratories, Llc | Monolithically integrated self-aligned GaN-HEMTs and Schottky diodes and method of fabricating the same |
US9449833B1 (en) * | 2010-06-02 | 2016-09-20 | Hrl Laboratories, Llc | Methods of fabricating self-aligned FETS using multiple sidewall spacers |
US9177780B2 (en) * | 2012-10-02 | 2015-11-03 | Applied Materials, Inc. | Directional SiO2 etch using plasma pre-treatment and high-temperature etchant deposition |
US10217819B2 (en) * | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US10170611B1 (en) | 2016-06-24 | 2019-01-01 | Hrl Laboratories, Llc | T-gate field effect transistor with non-linear channel layer and/or gate foot face |
US10868162B1 (en) | 2018-08-31 | 2020-12-15 | Hrl Laboratories, Llc | Self-aligned gallium nitride FinFET and method of fabricating the same |
US10937786B2 (en) * | 2018-09-18 | 2021-03-02 | Globalfoundries U.S. Inc. | Gate cut structures |
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KR101346005B1 (ko) | 2006-07-28 | 2013-12-31 | 프리스케일 세미컨덕터, 인크. | 데이터 저장 회로용 비대칭을 가진 트랜지스터 |
JP2014514757A (ja) * | 2011-03-28 | 2014-06-19 | 日本テキサス・インスツルメンツ株式会社 | 化学的に改変されたスペーサ表面を有する集積回路 |
JP2017143302A (ja) * | 2011-03-28 | 2017-08-17 | 日本テキサス・インスツルメンツ株式会社 | 化学的に改変されたスペーサ表面を有する集積回路 |
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