JP5203905B2 - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 122
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000012212 insulator Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 9
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 39
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 21
- 239000013078 crystal Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
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- 229910004129 HfSiO Inorganic materials 0.000 description 2
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- 230000009471 action Effects 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910004143 HfON Inorganic materials 0.000 description 1
- -1 HfSiON Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910006252 ZrON Inorganic materials 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
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Description
V. Narayanan et al., 2006 Symposium On VLSI Technology Digest of Technical Papers, pp.224 関根克行他、2006年秋季応用物理学学術講演会講演予稿集 Y. Yamamoto et al., Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, pp.212
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置1の断面図である。半導体装置1は、半導体基板2上に、素子分離領域3により電気的に分離された高い動作電圧を有するN型トランジスタ10(以下、HVNトランジスタ10)、高い動作電圧を有するP型トランジスタ20(以下、HVPトランジスタ20)、低い動作電圧を有するN型トランジスタ30(以下、LVNトランジスタ30)、および低い動作電圧を有するP型トランジスタ40(以下、LVPトランジスタ40)、ならびに素子分離領域3上に形成された抵抗素子50を有する。
図2A(a)〜(d)、図2B(e)〜(h)、図2C(i)〜(k)は、本発明の第1の実施の形態に係る半導体装置1の製造工程を示す断面図である。
本発明の第1の実施の形態によれば、メタルゲートとして働く金属層12a、22aを用いることにより、ゲート電極12、22の空乏化を防ぐことができる。一方、抵抗素子50は金属からなる層を含まないため、フューズとして働くために必要な程度の大きさの電気抵抗を有する。
本発明の第2の実施の形態は、半導体装置1のAl2O3膜63をパターニングする際のマスクとして、レジスト膜70aの他にハードマスクを用いる点において、第1の実施の形態と異なる。
図3(a)〜(d)は、本発明の第2の実施の形態に係る半導体装置1の製造工程を示す断面図である。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。また、発明の主旨を逸脱しない範囲内において上記各実施の形態の構成要素を任意に組み合わせることができる。
Claims (5)
- 半導体基板内に素子分離領域を形成し、前記半導体基板上の前記素子分離領域に分離された第1、第2、第3、および第4の領域を形成する工程と、
前記第1、第2の領域上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜上に第1の半導体膜を形成する工程と、
前記第1の半導体膜形成後、前記第4の領域上に第2の絶縁膜を形成し、前記第2の絶縁膜上に酸化アルミニウム膜を形成する工程と、
前記第1の半導体膜形成後、前記第3の領域上に第3の絶縁膜を形成し、前記第3の絶縁膜上に酸化ランタン膜を形成する工程と、
前記酸化アルミニウム膜および前記酸化ランタン膜上に高誘電率絶縁膜を形成する工程と、
前記高誘電率絶縁膜上に金属膜を形成する工程と、
前記第1の半導体膜および前記金属膜上に第2の半導体膜を形成する工程と、
前記第1の絶縁膜、前記第1の半導体膜、前記第2の絶縁膜、前記酸化アルミニウム膜、前記第3の絶縁膜、前記酸化ランタン膜、前記高誘電率絶縁膜、前記金属膜、および前記第2の半導体膜をパターニングする工程と、
を含む半導体装置の製造方法。 - 半導体基板内に素子分離領域を形成し、前記半導体基板上の前記素子分離領域に分離された第1、第2、第3、および第4の領域、ならびに前記素子分離領域上の第5の領域を形成する工程と、
前記第1、第2、および第5の領域上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜上に第1の半導体膜を形成する工程と、
前記第1の半導体膜形成後、前記第4の領域上に第2の絶縁膜を形成し、前記第2の絶縁膜上に酸化アルミニウム膜を形成する工程と、
前記第1の半導体膜形成後、前記第3の領域上に第3の絶縁膜を形成し、前記第3の絶縁膜上に酸化ランタン膜を形成する工程と、
前記酸化アルミニウム膜および前記酸化ランタン膜上に高誘電率絶縁膜を形成する工程と、
前記高誘電率絶縁膜上に金属膜を形成する工程と、
前記第1の半導体膜および前記金属膜上に第2の半導体膜を形成する工程と、
前記第1の絶縁膜、前記第1の半導体膜、前記第2の絶縁膜、前記酸化アルミニウム膜、前記第3の絶縁膜、前記酸化ランタン膜、前記高誘電率絶縁膜、前記金属膜、および前記第2の半導体膜をパターニングする工程と、
を含む半導体装置の製造方法。 - 前記第2の絶縁膜および前記第3の絶縁膜の膜厚は、前記第1の絶縁膜の膜厚よりも薄く形成される、
請求項1または2に記載の半導体装置の製造方法。 - 半導体基板上に形成され、第1の絶縁体層からなるゲート絶縁膜および第1の半導体層からなるゲート電極を有する第1のN型トランジスタと、
前記半導体基板上に形成され、前記第1の絶縁体層からなるゲート絶縁膜および前記第1の半導体層からなるゲート電極を有する第1のP型トランジスタと、
前記半導体基板上に形成され、第2の絶縁体層、前記第2の絶縁体層上の酸化ランタン層、および前記酸化ランタン層上の高誘電率絶縁体層からなるゲート絶縁膜ならびに金属層および前記金属層上の第2の半導体層からなるゲート電極を有し、前記第1のN型トランジスタよりも低い動作電圧を有する第2のN型トランジスタと、
前記半導体基板上に形成され、第3の絶縁体層、前記第3の絶縁体層上の酸化アルミニウム層、および前記酸化アルミニウム層上の前記高誘電率絶縁体層からなるゲート絶縁膜ならびに前記金属層および前記金属層上の前記第2の半導体層からなるゲート電極を有し、前記第1のP型トランジスタよりも低い動作電圧を有する第2のP型トランジスタと、
を有する半導体装置。 - 前記第1の絶縁体層からなる第1の層、前記第1の層上の前記第1の半導体層からなる第2の層を有する抵抗素子と、
をさらに有する請求項4に記載の半導体装置。
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JP5292878B2 (ja) * | 2008-03-26 | 2013-09-18 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8017469B2 (en) * | 2009-01-21 | 2011-09-13 | Freescale Semiconductor, Inc. | Dual high-k oxides with sige channel |
JP5521726B2 (ja) * | 2010-04-16 | 2014-06-18 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
KR20110123544A (ko) * | 2010-05-07 | 2011-11-15 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR101282343B1 (ko) | 2010-07-30 | 2013-07-04 | 에스케이하이닉스 주식회사 | 금속게이트를 갖는 반도체장치 및 그 제조 방법 |
KR101212567B1 (ko) * | 2010-12-22 | 2012-12-13 | 에스케이하이닉스 주식회사 | 반도체 장치 및 반도체 장치의 제조방법 |
US8389352B2 (en) * | 2011-02-11 | 2013-03-05 | International Business Machines Corporation | Silicon germanium film formation method and structure |
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JP2003060072A (ja) * | 2001-08-10 | 2003-02-28 | Seiko Epson Corp | 半導体装置の製造方法及びこれにより製造された半導体装置 |
JP2004221483A (ja) * | 2003-01-17 | 2004-08-05 | Seiko Epson Corp | 半導体装置の製造方法 |
JP4524995B2 (ja) * | 2003-03-25 | 2010-08-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4575653B2 (ja) * | 2003-07-31 | 2010-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
US6897095B1 (en) * | 2004-05-12 | 2005-05-24 | Freescale Semiconductor, Inc. | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode |
JP4588483B2 (ja) * | 2005-02-21 | 2010-12-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2007234740A (ja) * | 2006-02-28 | 2007-09-13 | Toshiba Corp | 半導体装置の製造方法 |
JP2008021935A (ja) * | 2006-07-14 | 2008-01-31 | Fujitsu Ltd | 電子デバイス及びその製造方法 |
JP2008066715A (ja) * | 2006-08-10 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2008306051A (ja) * | 2007-06-08 | 2008-12-18 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JP5196954B2 (ja) * | 2007-10-31 | 2013-05-15 | 株式会社東芝 | 半導体装置の製造方法 |
JP2009164424A (ja) * | 2008-01-08 | 2009-07-23 | Toshiba Corp | 半導体装置およびその製造方法 |
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