JP2008193060A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2008193060A JP2008193060A JP2007329564A JP2007329564A JP2008193060A JP 2008193060 A JP2008193060 A JP 2008193060A JP 2007329564 A JP2007329564 A JP 2007329564A JP 2007329564 A JP2007329564 A JP 2007329564A JP 2008193060 A JP2008193060 A JP 2008193060A
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Abstract
【解決手段】半導体基板3上にゲート絶縁膜5を介して設けられたゲート電極7と、ゲート電極7の両脇において半導体基板3の表面を掘り下げた部分にエピタキシャル成長によって形成された半導体層(応力印加層)9とを備えた半導体装置1において、半導体層9は、半導体基板3とは格子定数の異なる層であり、ゲート絶縁膜5およびゲート電極7は、半導体層9間において半導体基板3の表面を掘り下げた部分を埋め込む状態で設けられている。半導体基板3の表面に対するゲート絶縁膜5の深さ位置d2は、半導体層9の深さ位置d1よりも浅いこととする。
【選択図】図1
Description
図1は、本発明を適用した半導体装置1の要部断面図である。この図に示す半導体装置は、電界効果型トランジスタ構成の半導体装置であり、次のように構成されている。
図2〜図6は、本発明を適用した半導体装置の製造方法の第1例を示す断面工程図であり、図1を用いて説明した構成の半導体装置の製造方法の一例である。以下これらの図に基づいて製造方法の実施の形態を説明する。尚、図1を用いて説明したと同様の構成要素には同一の符号を付して説明を行うこととする。
図10〜図13は、本発明を適用した半導体装置の製造方法の第2例を示す断面工程図であり、図1を用いて説明した構成の半導体装置の製造方法の他の例である。以下これらの図に基づいて製造方法の実施の形態を説明する。尚、先の図面を用いて説明したと同様の構成要素には同一の符号を付して説明を行うこととする。
図14から図15は、本発明を適用した半導体装置の製造方法の第3例の要部を示す断面工程図である。以下これらの図に基づいて製造方法の実施の形態を説明する。尚、これらの図に示す第3例の製造方法は、上述した第2例の変形例であり、先の図面を用いて説明したと同様の構成要素には同一の符号を付し、重複する説明は省略する。
図16〜図17は、本発明を適用した半導体装置の製造方法の第4例を示す断面工程図である。以下これらの図に基づいて製造方法の実施の形態を説明する。尚、これらの図に示す第4例の製造方法は、上述した第2例および第3例の変形例であり、先の図面を用いて説明したと同様の構成要素には同一の符号を付し、重複する説明は省略する。
図18は、以上のような第4例を適用し、p型電界効果トランジスタとn型電界効果トランジスタとでゲート電極を作り分けたCMOS構成の半導体装置を作製する手順を示す図である。以下、この図に基づいて、本発明を適用した半導体装置の製造方法の第5例を説明する。尚、図面上右側をp型電界効果トランジスタが設けられるpMOS領域とし、左側をn型電界効果トランジスタが設けられるnMOS領域とする。
図19は、以上のような第4例を適用し、p型電界効果トランジスタとn型電界効果トランジスタとでゲート電極を作り分けたCMOS構成の半導体装置を作製する他の手順を示す図である。以下、この図に基づいて、本発明を適用した半導体装置の製造方法の第6例を説明する。尚、図面上右側をp型電界効果トランジスタが設けられるpMOS領域とし、左側をn型電界効果トランジスタが設けられるnMOS領域とする。
Claims (24)
- 半導体基板上にゲート絶縁膜を介して設けられたゲート電極と、前記ゲート電極下のチャネル部に応力を加えるための応力印加層とを備えると共に、
前記応力印加層が、前記ゲート電極の両脇における前記半導体基板の表面より深い位置に設けられ、
前記ゲート絶縁膜およびゲート電極は、前記応力印加層間において前記半導体基板の表面を掘り下げた部分を埋め込む状態で設けられている
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記応力印加層は、当該半導体基板とは格子定数の異なる半導体材料で構成され、前記ゲート電極の両脇において前記半導体基板の表面を掘り下げた部分にエピタキシャル成長によって形成された半導体層である
ことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記半導体基板は単結晶シリコンからなり、
前記半導体層は、シリコンにシリコンとは格子定数の異なる元素材料を含有させてなる
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板の表面に対する前記チャネル部の深さ位置は、前記応力印加層の深さ位置よりも浅い
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板および前記応力印加層上を覆う層間絶縁膜における当該応力印加層間に、当該半導体基板を底面としてこれを掘り下げた溝パターンが設けられ、
少なくとも前記半導体基板の露出面を覆う前記ゲート絶縁膜を介して前記溝パターンを埋め込む状態で前記ゲート電極が形成されている
ことを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記ゲート絶縁膜は、前記溝パターンの底面を含む内壁を覆う状態で設けられている
ことを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記ゲート絶縁膜は、前記溝パターンの内壁上部を露出する状態で設けられている
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート絶縁膜は、アルミニウム(Al)、イットリウム(Y)、ジルコニウム(Zr)、ランタン(La)、ハフニウム(Hf)、タンタル(Ta)のうちから選択される少なくとも1種を含んだ酸化物、酸化珪化物、窒化酸化物、または酸化窒化珪化物を有する
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極は、当該ゲート電極の仕事関数を調整するための仕事関数制御層を含む積層構造を有する
ことを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記仕事関数制御層は、前記ゲート絶縁膜に接して設けられている
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板上に、前記ゲート絶縁膜とゲート電極と応力印加層とを備えたp型電界効果トランジスタとn型電界効果トランジスタとが設けられており、
前記p型電界効果トランジスタおよびn型電界効果トランジスタの少なくとも一方のゲート電極は、当該ゲート電極の仕事関数を調整するための仕事関数制御層を含む積層構造を有する
ことを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記p型電界効果トランジスタおよびn型電界効果トランジスタのゲート電極が、それぞれ異なる仕事関数を有する
ことを特徴とする半導体装置。 - 半導体基板上にダミーのゲート電極を形成し、当該ダミーのゲート電極をマスクにしたエッチングにより当該半導体基板の表面を掘り下げる第1工程と、
前記掘り下げられた半導体基板の表面に、当該半導体基板とは格子定数の異なる半導体材料からなる応力印加層をエピタキシャル成長によって形成する第2工程と、
前記ダミーのゲート電極および応力印加層を覆う状態で層間絶縁膜を成膜し、当該層間絶縁膜から当該ダミーのゲート電極を露出させた後、当該ダミーのゲート電極を除去することにより当該層間絶縁膜に溝パターンを形成すると共に前記半導体基板を露出させる第3工程と、
前記溝パターンの底部に露出させた前記半導体基板の露出面を掘り下げる第4工程と、
前記半導体基板の露出面が掘り下げられた前記溝パターン内にゲート絶縁膜を介して新たなゲート電極を埋め込み形成する第5工程とを行う
ことを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第4工程で前記半導体基板を掘り下げる深さは、前記応力印加層の深さ位置よりも浅い
ことを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第1工程では、前記ダミーのゲート電極の側壁にサイドウォールを形成し、当該ダミーのゲート電極およびサイドウォールをマスクにしたエッチングにより当該半導体基板の表面を張り下げ、
前記第2工程では、前記サイドウォールの外側に前記応力印加層を形成する
ことを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記第5工程では、仕事関数を調整するための仕事関数制御層を含む積層構造からなる前記ゲート電極を形成する
ことを特徴とする半導体装置の製造方法。 - 半導体基板の表面側を掘り下げた凹部を形成する第1工程と、
前記凹部にダミーのゲート電極を形成し、当該ゲート電極をマスクにしたエッチングにより当該半導体基板の表面を掘り下げる第2工程と、
前記掘り下げられた半導体基板の表面に、当該半導体基板とは格子定数の異なる半導体材料からなる応力印加層をエピタキシャル成長によって形成する第3工程と、
前記ダミーのゲート電極および応力印加層を覆う状態で層間絶縁膜を成膜し、当該層間絶縁膜から当該ダミーのゲート電極を露出させた後、当該ダミーのゲート電極を除去して前記半導体基板の凹部に重なる溝パターンを形成する第4工程と、
前記半導体基板の凹部を含む前記溝パターン内にゲート絶縁膜を介して新たなゲート電極を埋め込み形成する第5工程とを行う
ことを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記第2工程で前記半導体基板を掘り下げる深さは、前記凹部の深さ位置よりも深い
ことを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記第2工程では、前記ダミーのゲート電極の側壁にサイドウォールを形成し、当該ダミーのゲート電極およびサイドウォールをマスクにしたエッチングにより当該半導体基板の表面を掘り下げ、
前記第3工程では、前記サイドウォールの外側に前記応力印加層を形成する
ことを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記第5工程では、仕事関数を調整するための仕事関数制御層を含む積層構造からなる前記ゲート電極を形成する
ことを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記第2工程では、前記ゲート絶縁膜を介して前記ダミーのゲート電極を形成し、
前記第5工程では、前記第2工程で形成した前記ゲート絶縁膜上に新たなゲート電極を埋め込み形成する
ことを特徴とする半導体装置の製造方法。 - 請求項21記載の半導体装置の製造方法において、
前記第2工程では、前記ゲート絶縁膜と前記ダミーのゲート電極との間に、キャップ膜を形成し、
前記第4工程で前記ダミーのゲート電極を除去する際には、前記キャップ膜をストッパとしたエッチングを行う
ことを特徴とする半導体装置の製造方法。 - 請求項22記載の半導体装置の製造方法において、
前記第4工程では、前記ゲート絶縁膜上に、前記ゲート電極の仕事関数を調整するための仕事関数制御層として前記キャップ膜を残す
ことを特徴とする半導体装置の製造方法。 - 請求項22記載の半導体装置の製造方法において、
前記第4工程では、前記ゲート絶縁膜上に前記キャップ膜を残して前記ダミーのゲート電極を除去し、
前記第5工程では、前記キャップ膜と反応させる金属膜を当該キャップ膜上に成膜し、当該キャップ膜と金属膜とを反応させて仕事関数制御層を形成した後、前記半導体基板の凹部を含む前記溝パターン内に当該仕事関数制御層を介してゲート電極材料を埋め込み形成し、当該仕事関数制御層によって仕事関数が制御された新たなゲート電極を形成する
ことを特徴とする半導体装置の製造方法。
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JP2010010508A (ja) * | 2008-06-30 | 2010-01-14 | Sony Corp | 半導体装置および半導体装置の製造方法 |
US7927943B2 (en) | 2008-09-12 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for tuning a work function of high-k metal gate devices |
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Also Published As
Publication number | Publication date |
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CN101542699B (zh) | 2011-05-18 |
TWI389215B (zh) | 2013-03-11 |
TW200842988A (en) | 2008-11-01 |
US8518813B2 (en) | 2013-08-27 |
US20090065809A1 (en) | 2009-03-12 |
US20110189845A1 (en) | 2011-08-04 |
CN101542699A (zh) | 2009-09-23 |
US8441033B2 (en) | 2013-05-14 |
JP5326274B2 (ja) | 2013-10-30 |
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