WO2008084765A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2008084765A1
WO2008084765A1 PCT/JP2008/050007 JP2008050007W WO2008084765A1 WO 2008084765 A1 WO2008084765 A1 WO 2008084765A1 JP 2008050007 W JP2008050007 W JP 2008050007W WO 2008084765 A1 WO2008084765 A1 WO 2008084765A1
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WIPO (PCT)
Prior art keywords
semiconductor
semiconductor substrate
semiconductor device
insulating film
gate electrode
Prior art date
Application number
PCT/JP2008/050007
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English (en)
French (fr)
Inventor
Shinya Yamakawa
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007329564A external-priority patent/JP5326274B2/ja
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to US12/282,112 priority Critical patent/US8441033B2/en
Priority to CN2008800001064A priority patent/CN101542699B/zh
Publication of WO2008084765A1 publication Critical patent/WO2008084765A1/ja
Priority to US13/084,194 priority patent/US8518813B2/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

　半導体基板とは格子定数の異なる半導体層からチャネル部に対して効果的に応力を印加することが可能でこれによりキャリア移動度の向上を図り高機能化の達成が可能な半導体装置を提供する。半導体基板３上にゲート絶縁膜５を介して設けられたゲート電極７と、ゲート電極７の両脇において半導体基板３の表面を掘り下げた部分にエピタキシャル成長によって形成された半導体層（応力印加層）９とを備えた半導体装置１において、半導体層９は、半導体基板３とは格子定数の異なる層であり、ゲート絶縁膜５およびゲート電極７は、半導体層９間において半導体基板３の表面を掘り下げた部分を埋め込む状態で設けられている。半導体基板３の表面に対するゲート絶縁膜５の深さ位置ｄ２は、半導体層９の深さ位置ｄ１よりも浅いこととする。
PCT/JP2008/050007 2007-01-09 2008-01-04 半導体装置および半導体装置の製造方法 WO2008084765A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/282,112 US8441033B2 (en) 2007-01-09 2008-01-04 Semiconductor device and method of manufacturing semiconductor device
CN2008800001064A CN101542699B (zh) 2007-01-09 2008-01-04 半导体器件和制造半导体器件的方法
US13/084,194 US8518813B2 (en) 2007-01-09 2011-04-11 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-000978 2007-01-09
JP2007000978 2007-01-09
JP2007-329564 2007-12-21
JP2007329564A JP5326274B2 (ja) 2007-01-09 2007-12-21 半導体装置および半導体装置の製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/282,112 A-371-Of-International US8441033B2 (en) 2007-01-09 2008-01-04 Semiconductor device and method of manufacturing semiconductor device
US13/084,194 Division US8518813B2 (en) 2007-01-09 2011-04-11 Semiconductor device and method of manufacturing semiconductor device

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Publication Number Publication Date
WO2008084765A1 true WO2008084765A1 (ja) 2008-07-17

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031753A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
JP2004266278A (ja) * 2003-02-28 2004-09-24 Samsung Electronics Co Ltd 上昇されたソース／ドレーン構造を有するｍｏｓトランジスタ及びこの製造方法
WO2004097943A1 (ja) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法
JP2006270051A (ja) * 2005-02-28 2006-10-05 Fujitsu Ltd 半導体装置およびその製造方法
JP2007103654A (ja) * 2005-10-04 2007-04-19 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031753A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
JP2004266278A (ja) * 2003-02-28 2004-09-24 Samsung Electronics Co Ltd 上昇されたソース／ドレーン構造を有するｍｏｓトランジスタ及びこの製造方法
WO2004097943A1 (ja) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
JP2006270051A (ja) * 2005-02-28 2006-10-05 Fujitsu Ltd 半導体装置およびその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法
JP2007103654A (ja) * 2005-10-04 2007-04-19 Toshiba Corp 半導体装置およびその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
TATESHITA Y. ET AL.: "High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates", INTERNATIONAL ELECTRON DEVICES MEETING, 2006, IEDM'06, 11 December 2006 (2006-12-11) *
WANG J. ET AL.: "Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascence Gata Process", 2007 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 12 June 2007 (2007-06-12), pages 46 - 47 *

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