TWI495106B - 鰭式場效電晶體及其製造方法 - Google Patents

鰭式場效電晶體及其製造方法 Download PDF

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TWI495106B
TWI495106B TW101111996A TW101111996A TWI495106B TW I495106 B TWI495106 B TW I495106B TW 101111996 A TW101111996 A TW 101111996A TW 101111996 A TW101111996 A TW 101111996A TW I495106 B TWI495106 B TW I495106B
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fin
top surface
gate dielectric
field effect
substrate
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TW101111996A
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TW201320340A (zh
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Clement Hsingjen Wann
Ling Yen Yeh
Chi Yuan Shih
Yi Tang Lin
Chih Sheng Chang
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Taiwan Semiconductor Mfg Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Description

鰭式場效電晶體及其製造方法
本發明係有關於一種積體電路的製造方法，特別係有關於一種鰭式場效電晶體的製造方法。
半導體製程係致力於提高元件密度、提高元件性能、及降低成本以進展至奈米技術製程節點，然而在發展例如鰭式場效電晶體(以下簡稱FinFET)之三維設計時會導致製造和設計問題的挑戰。係利用從一基板延伸之薄的、垂直的鰭(或鰭狀結構)來製造一習知FinFET，舉例來說，藉由蝕刻至基板的一矽層內之方式來形成上述習知FinFET。而FinFET的通道係定義於上述垂直的鰭內。一閘極係位於(包圍)鰭的三個側邊上。通道區的兩側上具有一閘極造係允許閘極於通道的兩側控制通道。另外，利用選擇性成長矽鍺之位於之凹陷的源/汲極部分中的應力材料可用於增加載子動能。因此，FinFET係具有高電流和降低短通道效應之優點。
然而，於互補式金氧半導體(CMOS)製程中應用這些元件和製程會遭受到挑戰。舉例來說，因為在可實行的FinFET製程中，FinFET由複數個完全相同的鰭構成，所以使用FinFET的電路會難以達到具有彈性的電路設計。
因此，在此技術領域中，有需要一種改良的鰭式場效電晶體及其製造方法，以克服習知技術的缺點。
有鑑於此，本發明一實施例係提供一種鰭式場效電晶體。上述鰭式場效電晶體包括一基板，包括一頂面；一第一鰭和一第二鰭，延伸於上述基板的上述頂面的上方，其中上述第一鰭具有一頂面和側邊，且上述第二鰭具有一頂面和側邊；一絕緣層，介於上述第一鰭和上述第二鰭之間，且從上述基板的上述頂面延伸至部分的上述第一鰭和上述第二鰭；一第一閘極介電質，覆蓋上述第一鰭的上述頂面和上述些側邊且具有一第一厚度，以及一第二閘極介電質，覆蓋上述第二鰭的上述頂面和上述些側邊且具有一第二厚度；以及一導電閘極條狀物，穿過上述第一閘極介電質和上述第二閘極介電質兩者。
本發明另一實施例係提供一種鰭式場效電晶體。上述鰭式場效電晶體包括於一基板，包括一頂面；一第一鰭和一第二鰭，延伸於上述基板的上述頂面的上方，其中上述第一鰭具有一頂面和側邊，且上述第二鰭具有一頂面和側邊；一絕緣層，介於上述第一鰭和上述第二鰭之間，且從上述基板的上述頂面延伸至部分的上述第一鰭和上述第二鰭，其中上述絕緣層的一頂面大體上與上述第一鰭的上述頂面共平面；一第一閘極介電質，覆蓋上述第一鰭的上述頂面和上述些側邊且具有一第一厚度，以及一第二閘極介電質，覆蓋上述第二鰭的上述頂面和上述些側邊且具有小於上述第一厚度的一第二厚度；以及一導電閘極條狀物，穿過上述第一閘極介電質和上述第二閘極介電質兩者。
本發明又一實施例係提供一種鰭式場效電晶體的製造方法。上述鰭式場效電晶體的製造方法包括提供一基板，其具有一第一鰭和一第二鰭，延伸於一基板頂面的上方，其中上述第一鰭具有一頂面和側邊，且上述第二鰭具有一頂面和側邊；形成一絕緣層，介於上述第一鰭和上述第二鰭之間，且從上述基板的上述頂面延伸至部分的上述第一鰭和上述第二鰭；於上述第一鰭和上述第二鰭上方形成一感光層；圖案化上述感光層，以暴露出位於上述絕緣層上方的部分上述第一鰭且覆蓋上述第二鰭；使用一電漿摻雜製程，形成一第一閘極介電質，覆蓋上述第一鰭的上述頂面和上述些側邊且具有一第一厚度；移除上述感光層；形成一第二閘極介電質，覆蓋上述第二鰭的上述頂面和上述些側邊且具有小於上述第一厚度的一第二厚度；以及形成一導電閘極條狀物，穿過上述第一閘極介電質和上述第二閘極介電質兩者。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在不脫離本發明之精神和範圍內，任何熟悉此項技藝者，可依據此項技藝，以清楚地形成本發明其他的實施例。而本發明之保護範圍僅為申請專利範圍之附屬項所限制。
請參考第1圖，其顯示本發明不同實施例之鰭式場效電晶體(FinFET)的製造方法100的製程流程圖。方法100始於步驟102，提供一基板，其具有一第一鰭和一第二鰭，延伸於一基板頂面的上方，其中第一鰭和第二鰭各自具有一頂面和側邊。接著，在步驟104中，形成一絕緣層，介於上述第一鰭和上述第二鰭之間，且從上述基板的上述頂面延伸至部分的上述第一鰭和上述第二鰭。接著，在步驟106中，於上述第一鰭和上述第二鰭的三個表面上方形成一感光層(意即包圍第一鰭和上述第二鰭)。接著，在步驟108中，圖案化上述感光層，以暴露出位於上述絕緣層上方的部分上述第一鰭且同時持續覆蓋上述第二鰭。接著，在步驟110中，使用一電漿摻雜製程，形成一第一閘極介電質，覆蓋上述第一鰭的上述頂面和上述些側邊(意即包圍第一鰭)且具有一第一厚度。接著，在步驟112中，移除上述感光層。接著，在步驟114中，形成一第二閘極介電質，覆蓋上述第二鰭的上述頂面和上述些側邊(意即包圍第二鰭)且具有小於上述第一厚度的一第二厚度。接著，在步驟116中，形成一導電閘極條狀物，穿過上述第一閘極介電質和上述第二閘極介電質兩者。後續會說明如第1圖所示的方法。
第2至10B圖為本發明不同實施例之FinFET 200的不同製程步驟剖面圖。在本發明實施例中，FinFET 200係有關於任何鰭式電晶體或多重閘極電晶體。上述FinFET 200可包括一微處理器(microprocessor)、記憶體及/其他積體電路(IC)。注意第1圖所示的方法不會製造出一完整的FinFET 200。可使用互補式金氧半導體(CMOS)技術製程製造完整的FinFET 200。另外，可以了解的是可於第1圖所示的方法的之前、之中或之後提供額外的步驟，並且可僅於說明書中簡單描述一些其他的製程。並且，第1至10B圖係經過簡化，以更為了解本發明的發明概念。舉例來說，雖然圖式係顯示FinFET 200，可以了解的是積體電路可包括數個包括電阻、電容、電感、保險絲及/或其他常用的元件。
請參考第2圖，提供一基板202。在本發明一實施例中，基板202可包括一結晶矽基板(例如晶圓)。基板202可包括依據設計要求的不同摻雜區(例如p型基板或n型基板)。在本發明一些實施例中，上述摻雜區可摻雜p型或n型摻質。舉例來說，上述摻雜區可摻雜例如硼或二氟化硼(BF2 )的p型摻質、例如磷或砷的n型摻質及/或上述組合。上述摻雜區可用來構成一n型鰭式場效電晶體，或用來構成一p型鰭式場效電晶體。
在本發明其他實施例中，上述基板202可包括例如鑽石或鍺的其他適當元素半導體，或包括例如砷化鎵(gallium arsenic)、碳化矽(silicon carbide)、砷化銦(indium arsenide)或磷化銦(indium phosphide)的一適當化合物半導體，或包括例如碳鍺化矽(silicon germanium carbide)、磷砷化鎵(gallium arsenic phosphide)、磷銦化鎵(gallium indium phosphide)的一適當合金半導體。此外，上述基板202可包括一磊晶層，可對上述基板202施加應力以增加其性能表現，及/或可包括一絕緣層上覆矽(SOI)基板。
可於蝕刻至上述基板202之後，於一基板頂面的上方形成上述鰭，其中上述鰭各別具有一頂面和側邊。在本發明一些實施例中，於上述半導體基板202上形成一墊層204a和一遮罩層204b。上述墊層204a可為包括氧化矽的一薄膜，且例如可使用一熱氧化製程形成上述墊層204a。上述墊層204a可做為半導體基板202和遮罩層204b之間的一黏著層。上述墊層204a也可做為蝕刻遮罩層204b的蝕刻停止層。在本發明一些實施例中，遮罩層204b可為氮化矽，且例如可使用低壓化學氣相沉積(LPCVD)法、電漿增強型化學氣相沉積(PECVD)法的製程形成形成上述遮罩層204b。上述遮罩層204b可做為後續微影製程的一硬遮罩層。於上述遮罩層204b上形成一感光層206，接著圖案化感光層206，以於感光層206中形成開口208。
請參考第3圖，藉由開口208蝕刻遮罩層204b和墊層204a，暴露其下的半導體基板202。然後，蝕刻暴露出的半導體基板202，以形成具有一基板頂面202s的溝槽210。位於溝槽210之間的部分半導體基板202係形成複數個各自獨立的半導體鰭。在本發明一些實施例中，上述各自獨立的半導體鰭包括第一鰭212_1和第二鰭212_2。在本發明其他實施例中，上述各自獨立的半導體鰭包括第一鰭212_1、第二鰭212_2和第三鰭212_3。溝槽210可為彼此平行的條狀物(在上視圖中)，且彼此接近。舉例來說，溝槽210之間的間隙S可小於30 nm。在本發明一些實施例中，溝槽210之間的間隙S可介於15 nm和30 nm之間。在本發明其他實施例中，溝槽210之間的間隙S可介於2 nm和15 nm之間。之後，移除上述感光層206。接著，可進行一清潔製程以移除半導體基板202的原生氧化物。可使用稀釋氫氟酸(DHF)進行上述清潔製程。
當溝槽210的寬度W約介於300和1500之間時，溝槽210的深度D可約介於2100和2500之間。在本發明一些實施例中，溝槽210的深寬比(D/W)約大於7.0。在本發明其他實施例中，雖然溝槽210的深寬比(D/W)也可約小於7.0，然而溝槽210的深寬比(D/W)可約大於8.0，或約介於7.0和8.0之間。然而熟習此技藝者當可了解說明書中的尺寸和數值僅做為實施例，且可改變上述尺寸和數值以適用於不同尺度的積體電路。
可於上述鰭之間形成一絕緣層，上述絕緣層從上述基板頂面202s延伸至上述鰭上，將上述鰭彼此隔開。在本發明一些實施例中，可選擇性於溝槽210中形成墊氧化層(圖未顯示)。在本發明一些實施例中，上述墊氧化層可為厚度約介於20和500之間的熱氧化層。在本發明其他實施例中，可使用臨場蒸氣產生製程(in situ steam generation，ISSG)或類似的製程形成上述熱氧化層。上述墊氧化層的形成可圓滑溝槽210的轉角，其可降低電場且因此改善積體電路的性能。
接著，在本發明一些實施例中，可以一介電材料216填充溝槽210。第4圖係顯示沉積介電材料216之後的最終結構。介電材料216可包括氧化矽，然而也可使用例如氮化矽、氮氧化矽、摻氟矽玻璃(FSG)或一低介電常數介電材料等其他的介電材料。在本發明一些實施例中，可利用高密度電漿(HDP)CVD法，使用甲烷(SiH4 )和氧氣(O2 )做為前驅反應物形成介電材料216。在本發明其他實施例中，可利用次大氣壓CVD(SACVD)法或高深寬比(HARP)法形成介電材料216，其中製程氣體可包括四乙氧基矽烷(TEOS)和臭氧(O3 )。在本發明其他實施例中，可利用旋塗介電質(Spin on dielectric,SOD)製程形成例如含氫矽酸鹽類低介電常數材質(Hydrogen Silsesquioxane，HSQ)或含甲基矽酸鹽類低介電常數材質(Methylsilsesquioxane，MSQ)之介電材料216。
在本發明一些實施例中，之後進行化學機械研磨(CMP)製程，接著移除遮罩層204b和墊層204a，以形成第5圖所示的結構。介電材料216在溝槽210中的剩餘部分之後係視為一絕緣層217。如果遮罩層204b由氮化矽構成，可利用使用熱磷酸(hot H3 PO4 )的一濕式製程移除遮罩層204b，且如果墊層204a由氧化矽構成，可使用氫氟酸(HF)移除墊層204a。在本發明其他實施例中，可於凹陷絕緣層217之後進行遮罩層204b和墊層204a的移除製程，且上述凹陷製程以第6圖顯示。
如第6圖所示，利用一蝕刻步驟凹陷絕緣層217產生凹陷214，以形成複數個半導體鰭(標示為212_1、212_2和212_3)的複數個上部(標示為222_1、222_2和222_3)。在本發明一些實施例中，剩餘絕緣層217可包括一第一絕緣層217_1，用以隔開第一鰭212_1和第二鰭212_2，且第二絕緣層217_2係用以隔開第二鰭212_2和第三鰭212_3。在本發明一些實施例中，可利用濕蝕刻製程進行蝕刻步驟，舉例來說，將FinFET 200浸泡於氫氟酸(HF)中。在本發明其他實施例中，可利用乾蝕刻製程進行蝕刻步驟，舉例來說，可使用三氟甲烷(CHF3 )或三氟化硼(BF3 )做為蝕刻氣體來進行乾蝕刻製程。
在本發明一些實施例中，剩餘絕緣層217包括平坦的頂面217t。在本發明其他實施例中，剩餘的絕緣層217包括彎曲的頂面(圖未顯示)。並且，突出於剩餘絕緣層217之平坦的頂面217t上方之複數個半導體鰭的複數個上部係用以形成將FinFET 200的通道區。換句話說，第一鰭222_1和第二鰭222_2之間的(剩餘)第一絕緣層217_1從基板頂面202s延伸至部分第一鰭212_1和第二鰭212_2上。第二鰭212_2和第三鰭212_3之間的(剩餘)第二絕緣層217_2從基板頂面202s延伸至部分第二鰭212_2和第三鰭212_3上。在本發明一些實施例中，複數個半導體鰭的複數個上部係各自包括一頂面(標示為222t_1、222t_2和222t_3)和側壁(標示為222s_1、222s_2和222s_3)。半導體鰭的上部的高度H可介於15nm和50nm之間，然而上述高度可大於或小於上述範圍。
在本發明一些實施例中，此時的製程步驟係提供基板202，其具有延伸於基板頂面202s上方的第一鰭212_1和第二鰭212_2，其中第一鰭212_1和第二鰭212_2各自包括頂面222t_1、222t_2和側壁222s_1、222s_2，其中第一鰭212_1和第二鰭212_2之間的第一絕緣層217_1從基板頂面202s延伸至部分第一鰭212_1和第二鰭212_2上。之後，形成一導電閘極條狀物，覆蓋第一鰭212_1和第二鰭212_2的頂面222t_1、222t_2和側壁222s_1、222s_2，建立第一鰭212_1和第二鰭212_2之間的電性連接，以形成一鰭式場效電晶體。應注意由複數個完全相同的鰭構成的鰭式場效電晶體對於量產鰭式場效電晶體是可實行的，但是如果鰭式場效電晶體包括多於需求的鰭，會產生過量的開啟電流(on-current)，因而當電路使用鰭式場效電晶體時會減少電路設計的彈性。
因此，如下述第7至10B圖所討論的製程可於一選定的鰭上形成一較薄的閘極介電質，使一鰭式場效電晶體的上述選定鰭能夠形成通道區，但是於未選定的鰭形成一較厚的閘極介電質，使一鰭式場效電晶體的上述未選定鰭不能形成通道區。上述製程有助於防止鰭式場效電晶體過的量開啟電流的問題，因而增加鰭式場效電晶體電路設計的彈性。
請參考第7圖，利用例如旋轉塗佈(spin-on coating)製程之一適當製程，於第一鰭212_1和第二鰭212_2上方形成一感光層218。在本發明一些實施例中，可圖案化感光層218，以暴露第一絕緣層217_1上方的第一鰭212_1，且覆蓋第二鰭212_2。
第8A圖係顯示第7圖的FinFET 200形成覆蓋第一鰭212_1的頂面222t_1x和側壁222s_1x的第一閘極介電質224a之後的結構。係使用一電漿摻雜製程220來進行形成第一閘極介電質224a的製程步驟，以避免損傷感光層218。第8B圖係顯示第7圖的FinFET 200形成形成覆蓋第一鰭212_1的頂面222t_1y的第一閘極介電質224b之後的結構。係使用一電漿摻雜製程220來進行形成第一閘極介電質224b的製程步驟，以避免損傷感光層218。在本發明一些實施例中，電漿摻雜製程220可包括一含氧電漿摻雜製程。舉例來說，可於製程功率約為260至2500W、偏壓約為-200V至-20kV、製程壓力約為1至50mTorr、使用氧(O2 )、臭氧(O3 )或水氣(H2 O)做為摻雜氣體之條件下來進行電漿摻雜製程220。接著，移除感光層218。
應注意可調整電漿摻雜製程220所使用的偏壓，使得第一閘極介電質224a或224b的厚度得到更好的控制，以使第一鰭212_1的氧化達到想要的輪廓。舉例來說，電漿摻雜製程係直接使用電漿離子流入反應腔室以發生反應，藉以於鰭的暴露表面上形成一反應邊界層，且上述邊界層會依照摻質濃度的變化而改變。
正好相反，脈衝電漿摻雜製程的概念係使用氣體流入反應腔室，並使用週期性電壓法，使用增加/不增加電壓控制，從氣體分離出正離子。然後上述正離子朝鰭的表面移動，使上述邊界層均勻且不變。因此，可控制驅動力維持一定值。
在本發明一些實施例中，在進行電漿摻雜製程220之後，對第一閘極介電質224a或224b退火。在本發明其他實施例中，於形成一第二閘極介電質234(如第9A、9B圖所示)之後，對第一閘極介電質224a或224b退火。換句話說，可於形成一第二閘極介電質234之後同時對第一閘極介電質224a或224b和第二閘極介電質234退火。
如果電漿摻雜製程驅動的氧分子太靠近第一鰭212_1的表面，第一鰭212_1的上部的外部會因為與電漿離子反應形成第一閘極介電質224a而部分消耗，第二鰭212_2的上部被感光層218保護(如第8A圖所示)。因此，第一閘極介電質224a覆蓋第一鰭212_1的剩餘上部222_1x的頂面222t_1x和側壁222s_1x。在本發明一些實施例中，第一鰭212_1的頂面222t_1x低於第二鰭212_2的頂面222t_2。在本發明其他實施例中，絕緣層217的頂面217t低於第一鰭212_1的頂面222t_1x。在本發明又其他實施例中，延伸於絕緣層217上的第一鰭212_1的上部222_1x薄於延伸於絕緣層217上的第二鰭212_2的上部。
如果電漿摻雜製程驅動的氧分子太靠近第一鰭212_1的中心，位於絕緣層217的頂面217t上的第一鰭212_1的材料會因為與電漿離子反應形成第一閘極介電質224a而完全消耗(如第8B圖所示)。換句話說，絕緣層217的頂面217t大體上與第一鰭212_1的頂面222t_1y共平面。在本發明一些實施例中，第一鰭212_1的頂面222t_1y低於第二鰭212_2的頂面222t_2。由於操作鰭式場效電晶體時不需開啟第一鰭212_1(未選定的鰭)，所以可允許位於絕緣層217下方的第一鰭212_1的額外材料消耗。
在本發明一些實施例中，延伸於絕緣層217上的第一鰭212_1的寬度W1 對延伸於絕緣層217上的第二鰭212_2的的寬度W2 比值可從0至0.95。在本發明一些實施例中，延伸於絕緣層217上的第一鰭212_1的高度h1 對延伸於絕緣層217上的第二鰭212_2的的高度h2 比值可從0至0.95。
請參考第9A、9B圖，形成第一閘極介電質224a或224b且移除感光層218之後，形成一第二閘極介電質234，覆蓋第二鰭212_2的頂面222t_2和側壁222s_2以及第一閘極介電質224a或224b。在本發明一些實施例中，第二閘極介電質234可包括氧化矽、氮化矽、氮氧化矽或高介電常數(high-k)介電材料。上述高介電常數(high-k)介電材料包括金屬氧化物。用於高介電常數(high-k)介電材料的金屬氧化物可包括鋰(Li)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鈧(Sc)、釔(Y)、鋯(Zr)、鉿(Hf)、鋁(Al)、鑭(La)、鈰(Ce)、鏷(Pr)、釹(Nd)、釤(Sm)、銪(Eu)、釓(Gd)、鋱(Tb)、鏑(Dy)、鈥(Ho)、鉺(Er)、銩(Tm)、鐿(Yb)、鎦(Lu)的氧化物及上述混合物。可使用例如原子層沉積(ALD)法、化學氣相沉積(CVD)法、物理氣相沉積(PVD)法、熱氧化法、紫外線-臭氧氧化法或上述組合等適當製程形成第二閘極介電質234。第二閘極介電質234可更包括一中介層(圖未顯示)以降低第二閘極介電質234和第二鰭212_2之間的損傷。上述中介層可包括氧化矽。
在本發明一些實施例中，第二閘極介電質234為一高介電常數(high-k)層，其具有範圍約為10至30的一第二厚度t2 。結構上來說，係結合第一閘極介電質224a或224b和覆蓋第一閘極介電質224a或224b的部分第二閘極介電質234且此後視為一閘極介電質225。因此，結合後的閘極介電質225的一第一厚度t1 為第一閘極介電質224a或224b的厚度tx 和第二閘極介電質234的第二厚度t2 的總合。換句話說，覆蓋第一鰭212_1的頂面222t_1x或222t_1y的閘極介電質225具有第一厚度t1 ，且覆蓋第二鰭212_2的頂面222t_2和側壁222s_2具有小於第一厚度t1 的第二厚度t2 。在本發明一些實施例中，第一厚度t1 對第二厚度t2 的比值可從1.05至2。
請參考第10A和10B圖，於第二閘極介電質234的形成製程之後，形成一導電閘極條狀物226穿過第一閘極介電質224a或224b和第二閘極介電質234兩者上方。在本發明一些實施例中，導電閘極條狀物226係覆蓋多於一個半導體鰭212_1、212_2，使最終的FinFET 200包括多於一個鰭。在本發明一些實施例中，導電閘極條狀物226可包括多晶矽。並且，導電閘極條狀物226可為均勻摻雜或非均勻摻雜的摻雜多晶矽。在本發明其他實施例中，導電閘極條狀物226可包括N型功函數金屬，其中上述鰭式場效電晶體為一n型鰭式場效電晶體，且其中N型功函數金屬包括一金屬，其擇自鈦(Ti)、銀(Ag)、鋁(Al)、鈦化鋁(TiAl)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、氮化碳鉭(TaCN)、氮化矽鉭(TaSiN)、錳(Mn)和鋯(Zr)所組成之族群。在本發明其他實施例中，可包括P型功函數金屬，其中上述鰭式場效電晶體為一p型鰭式場效電晶體，且其中P型功函數金屬包括一金屬，其擇自氮化鈦(TiN)、氮化鎢(WN)、氮化鉭(TaN)和釕(Ru)所組成之族群。在本發明一些實施例中，導電閘極條狀物226的厚度範圍約為30nm至60nm。可使用例如原子層沉積(ALD)法、化學氣相沉積(CVD)法、物理氣相沉積(PVD)法、電鍍法或上述組合之一適當製程形成導電閘極條狀物226。
在本發明一些實施例中，一FinFET 200包括一基板202，包括一頂面202s；一第一鰭212_1和一第二鰭212_2，延伸於基板202的頂面202s的上方，其中第一鰭212_1和第二鰭212_2各自具有一頂面和側邊；一絕緣層217，介於第一鰭212_1和一第二鰭212_2之間，且從基板202的頂面202s延伸至部分的第一鰭212_1和第二鰭212_2上；一第一閘極介電質224a或224b，覆蓋第一鰭212_1的頂面222t_1x和側邊222s_1x且具有一第一厚度t1 ，以及一第二閘極介電質234，覆蓋第二鰭212_2的該頂面222t_2和側邊222s_2且具有一第二厚度t2 ；以及一導電閘極條狀物226，穿過第一閘極介電質224a或224b和第二閘極介電質234兩者。因此，本發明實施例之FinFET 200的製造方法可製造一鰭式場效電晶體，當操作鰭式場效電晶體時會開啟具有較薄閘極介電質之選定的鰭(第二鰭)時，不會開啟具有較厚閘極介電質之未選定的鰭(第一鰭)，因而增加鰭式場效電晶體電路設計的彈性。
了解可對FinFET 200進行更進一步的CMOS製程，以形成例如源/汲極、接觸插塞/介層孔插塞、內連線金屬層、介電層、保護層及其他常用元件等不同元件。
依據本發明一些實施例的一鰭式場效電晶體包括一基板，包括一頂面；一第一鰭和一第二鰭，延伸於該基板的該頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭；一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊且具有一第一厚度，以及一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊且具有一第二厚度；以及一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
依據本發明其他實施例的一鰭式場效電晶體包括一基板，包括一頂面；一第一鰭和一第二鰭，延伸於該基板的該頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭，其中該絕緣層的一頂面大體上與該第一鰭的該頂面共平面；一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊且具有一第一厚度，以及一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊且具有小於該第一厚度的一第二厚度；以及一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
依據本發明又其他實施例的一鰭式場效電晶體的製造方法，包括提供一基板，其具有一第一鰭和一第二鰭，延伸於一基板頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；形成一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭；於該第一鰭和該第二鰭上方形成一感光層；圖案化該感光層，以暴露出位於該絕緣層上方的部分該第一鰭且覆蓋該第二鰭；使用一電漿摻雜製程，形成一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊且具有一第一厚度；移除該感光層；形成一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊且具有小於該第一厚度的一第二厚度；以及形成一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
100．．．方法
102、104、106、108、110、112、114、116．．．步驟
200．．．鰭式場效電晶體
202．．．基板
202s．．．基板頂面
202s．．．基板頂面
204a．．．墊層
204b．．．遮罩層
206．．．感光層
208．．．開口
210．．．溝槽
212_1．．．第一鰭
212_2．．．第二鰭
212_3．．．第三鰭
214．．．凹陷
216．．．介電材料
217．．．絕緣層
217_1．．．第一絕緣層
217_2．．．第二絕緣層
217t、222t_1、222t_2、222t_3、222t_1x、222t_1y．．．頂面
218．．．感光層
222s_1、222s_2、222s_3、222s_1x．．．側壁
222_1、222_2、222_3、222_1x．．．上部
224a、224b．．．第一閘極介電質
225．．．閘極介電質
226．．．導電閘極條狀物
234．．．第二閘極介電質
D．．．深度
W．．．寬度
S．．．間隙
H、h1 、h2 ．．．高度
W1 、W2 ．．．寬度
t1 、t2 、tx ．．．厚度
第1圖為本發明不同實施例之鰭式場效電晶體的製造方法的製程流程圖。
第2-7、8A-8B、9A-9B、10A-10B圖為本發明不同實施例之鰭式場效電晶體的不同製程步驟剖面圖。
200．．．鰭式場效電晶體
202．．．基板
212_1．．．第一鰭
212_2．．．第二鰭
217_1．．．第一絕緣層
217_2．．．第二絕緣層
225．．．閘極介電質
226．．．導電閘極條狀物
234．．．第二閘極介電質

Claims (10)

  1. 一種鰭式場效電晶體，包括：一基板，包括一頂面；一第一鰭和一第二鰭，延伸於該基板的該頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭；一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊且具有一第一厚度t1 ，其中該第一閘極介電質直接接觸該第一鰭；一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊且具有一第二厚度t2 ，其中該第二閘極介電質直接接觸該第二鰭；以及一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體，其中延伸該絕緣層上方的部分該第一鰭的厚度小於延伸該絕緣層上方的部分該第二鰭的厚度。
  3. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該第一鰭的該頂面低於該第二鰭的該頂面。
  4. 如申請專利範圍第1項所述之鰭式場效電晶體，其中該絕緣層的一頂面低於該第一鰭的該頂面。
  5. 如申請專利範圍第1項所述之鰭式場效電晶體，其中於開啟該第二鰭且不開啟該第一鰭的條件下操作該鰭 式場效電晶體。
  6. 一種鰭式場效電晶體，包括：一基板，包括一頂面；一第一鰭和一第二鰭，延伸於該基板的該頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭，其中該絕緣層的一頂面大體上與該第一鰭的該頂面共平面；一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊且具有一第一厚度；一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊且具有小於該第一厚度的一第二厚度；以及一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
  7. 如申請專利範圍第6項所述之鰭式場效電晶體，其中該第一鰭的該頂面低於該第二鰭的該頂面。
  8. 一種鰭式場效電晶體的製造方法，包括下列步驟：提供一基板，其具有一第一鰭和一第二鰭，延伸於一基板頂面的上方，其中該第一鰭具有一頂面和側邊，且該第二鰭具有一頂面和側邊；形成一絕緣層，介於該第一鰭和該第二鰭之間，且從該基板的該頂面延伸至部分的該第一鰭和該第二鰭上；於該第一鰭和該第二鰭上方形成一感光層； 圖案化該感光層，以暴露出位於該絕緣層上方的部分該第一鰭且覆蓋該第二鰭；使用一電漿摻雜製程，形成具有一第一厚度的一第一閘極介電質，覆蓋該第一鰭的該頂面和該些側邊；移除該感光層；形成具有小於該第一厚度的一第二厚度的一第二閘極介電質，覆蓋該第二鰭的該頂面和該些側邊；以及形成一導電閘極條狀物，穿過該第一閘極介電質和該第二閘極介電質兩者。
  9. 如申請專利範圍第8項所述之鰭式場效電晶體的製造方法，其中該電漿摻雜製程包括一含氧電漿摻雜製程。
  10. 如申請專利範圍第8項所述之鰭式場效電晶體的製造方法，更包括：於該電漿摻雜製程之後對該第一閘極介電質退火；以及形成該第二閘極介電質程後同時對該第一閘極介電質和該第二閘極介電質退火。
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