CN103107196A - 鳍式场效应晶体管及其制造方法 - Google Patents

鳍式场效应晶体管及其制造方法 Download PDF

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CN103107196A
CN103107196A CN2012100412498A CN201210041249A CN103107196A CN 103107196 A CN103107196 A CN 103107196A CN 2012100412498 A CN2012100412498 A CN 2012100412498A CN 201210041249 A CN201210041249 A CN 201210041249A CN 103107196 A CN103107196 A CN 103107196A
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fin
face
grid dielectric
insulating barrier
finfet
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CN103107196B (zh
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万幸仁
叶凌彦
施启元
林以唐
张智胜
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及鳍式场效应晶体管(FinFET)。FinFET的一个示例性结构包括：具有顶面的衬底；在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，每个鳍片均具有顶面和侧壁；位于第一鳍片和第二鳍片之间的绝缘层，该绝缘层从衬底顶面沿着鳍片的一部分向上延伸；覆盖第一鳍片的顶面和侧壁且具有第一厚度的第一栅极电介质和覆盖第二鳍片的顶面和侧壁且具有小于第一厚度的第二厚度的第二栅极电介质；以及跨过第一栅极电介质和第二栅极电介质两者的导电栅极带。本发明提供了鳍式场效应晶体管及其制造方法。

Description

鳍式场效应晶体管及其制造方法
技术领域
本发明涉及集成电路制造，更具体而言，涉及鳍式场效应晶体管。
背景技术
随着半导体产业在追求更大的器件密度、更卓越的性能以及更低的成本方面已发展到了纳米技术工艺节点，制造和设计问题中的挑战已引起了三维设计诸如鳍式场效应晶体管(FinFET)的发展。典型的FinFET是用例如蚀刻至衬底的硅层内的从衬底延伸的垂直薄“鳍片”(或鳍片结构)制造的。在这种垂直鳍片中形成FinFET的沟道。在鳍片的三个面的上方(例如包围)提供栅极。在沟道的两侧上具有栅极容许沟槽从两侧进行栅极控制。此外，可以使用应用了选择性生长的硅锗(SiGe)的FinFET的凹进的源极/漏极(S/D)部分中的应变材料来增强载流子迁移率。
然而，在互补金属氧化物半导体(CMOS)制造中应用这种部件和工艺仍存在挑战。例如，由于对FinFET制造而言由多个完全相同的鳍片形成FinFET是可行的，所以使用FinFET难以实现灵活的电路设计。
因此，需要一种改进的FinFET结构以及制造该FinFET的方法。
发明内容
本发明提供了一种鳍式场效应晶体管(FinFET)，所述FinFET包括：衬底，所述衬底具有顶面；第一鳍片和第二鳍片，所述第一鳍片和第二鳍片在所述衬底顶面上方延伸，其中，所述第一鳍片具有顶面和侧壁，以及所述第二鳍片具有顶面和侧壁；绝缘层，所述绝缘层位于所述第一鳍片和所述第二鳍片之间，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸；第一栅极电介质和第二栅极电介质，所述第一栅极电介质覆盖所述第一鳍片的所述顶面和侧壁，所述第一栅极电介质具有第一厚度t1，所述第二栅极电介质覆盖所述第二鳍片的所述顶面和侧壁，所述第二栅极电介质具有小于所述第一厚度的第二厚度t2；以及导电栅极带，所述导电栅极带跨过所述第一栅极电介质和所述第二栅极电介质两者。
在所述的FinFET中，所述第一鳍片延伸在所述绝缘层上方的部分薄于所述第二鳍延伸在所述绝缘层上方的部分。
在所述的FinFET中，所述第一鳍片延伸在所述绝缘层上方的部分的宽度与所述第二鳍片延伸在所述绝缘层上方的部分的宽度的比值为0至0.95。
在所述的FinFET中，所述第一鳍片的所述顶面低于所述第二鳍片的所述顶面。
在所述的FinFET中，所述第一鳍片在所述绝缘层上方的高度与所述第二鳍片在所述绝缘层上方的高度的比值为0至0.95。
在所述的FinFET中，所述绝缘层的顶面低于所述第一鳍片的所述顶面。
在所述的FinFET中，所述第一厚度与所述第二厚度的比值为1.05至2。
在所述的FinFET中，所述导电栅极带包含N-功函金属，其中，所述晶体管是n型FinFET。
在所述的FinFET中，所述N-功函金属包括选自由Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn以及Zr组成的组中的金属。
在所述的FinFET中，在导通所述第二鳍片但不导通所述第一鳍片时操作所述FinFET。
在所述的FinFET中，所述导电栅极带包含P-功函金属，其中，所述晶体管是p型FinFET。
在所述的FinFET中，所述P-功函金属包括选自由TiN、WN、TaN以及Ru组成的组中的金属。
另一方面，本发明还提供了一种鳍式场效应晶体管(FinFET)，所述FinFET包括：衬底，所述衬底具有顶面；第一鳍片和第二鳍片，所述第一鳍片和所述第二鳍片在所述衬底顶面上方延伸，其中，所述第一鳍片具有顶面，以及所述第二鳍片具有顶面和侧壁；绝缘层，所述绝缘层位于所述第一鳍片和所述第二鳍片之间，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸，其中，所述绝缘层的顶面与所述第一鳍片的所述顶面基本上共平面；第一栅极电介质和第二栅极电介质，所述第一栅极电介质覆盖所述第一鳍片的所述顶面，所述第一栅极电介质具有第一厚度，所述第二栅极电介质覆盖所述第二鳍片的所述顶面和侧壁，所述第二栅极电介质具有小于所述第一厚度的第二厚度；以及导电栅极带，所述导电栅极带跨过所述第一栅极电介质和所述第二栅极电介质两者。
在所述的FinFET中，所述第一鳍片的所述顶面低于所述第二鳍片的所述顶面。
又一方面，本发明还提供了一种制造鳍式场效应晶体管(FinFET)的方法，所述方法包括：提供衬底，所述衬底具有在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，所述第一鳍片具有顶面和侧壁，以及所述第二鳍片具有顶面和侧壁；在所述第一鳍片和所述第二鳍片之间形成绝缘层，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸；在所述第一鳍片和所述第二鳍片上方形成感光层；图案化所述感光层以暴露出位于所述绝缘层上方的部分所述第一鳍片，但仍覆盖所述第二鳍片；采用等离子体掺杂工艺形成具有第一厚度且覆盖所述第一鳍片的所述顶面和侧壁的第一栅极电介质；去除所述感光层；形成覆盖所述第二鳍片的所述顶面和侧壁且具有小于所述第一厚度的第二厚度的第二栅极电介质；以及形成跨过所述第一栅极电介质和所述第二栅极电介质两者的导电栅极带。
在所述的方法中，所述等离子体掺杂工艺包括含氧等离子体掺杂工艺。
在所述的方法中，在约260至2500W的源功率下实施等离子体掺杂工艺。
在所述的方法中，在约1mTorr至50mTorr的压力下实施等离子体掺杂工艺。
所述的方法进一步包括：在所述等离子体掺杂工艺之后对所述第一栅极电介质进行退火。
所述的方法进一步包括：在形成所述第二栅极电介质之后，同时对所述第一栅极电介质和所述第二栅极电介质进行退火。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据本发明的各个实施例制造FinFET的方法的流程图；以及
图2至图10B是根据本发明的各个实施例在各个制造阶段的FinFET的示意性剖面图。
具体实施方式
可以理解，为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然，这些仅仅是实例并不打算用于限制。例如，在以下描述中，第一部件在第二部件上方或在第二部件上的形成可以包括其中第一部件和第二部件以直接接触形成的实施例，也可以包括其中可以在第一部件和第二部件之间形成其他部件，使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考符号和/或字符。
参考图1，示出了根据本发明的各个实施例制造鳍式场效应晶体管(FinFET)的方法100的流程图。方法100开始于步骤102，在步骤102中提供了衬底，该衬底具有在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，每个鳍片均具有顶面和侧壁。方法100继续到步骤104，在步骤104中在第一鳍片和第二鳍片之间形成绝缘层，该绝缘层从衬底顶面沿着鳍片的一部分向上延伸。方法100继续到步骤106，在步骤106中，在第一鳍片和第二鳍片的三个表面上方(即，包围)形成感光层。方法100继续到步骤108，在步骤108中对感光层进行图案化，从而暴露出位于绝缘层上方的部分第一鳍片，同时保持覆盖第二鳍片。方法100继续到步骤110，在步骤110中采用等离子体掺杂工艺形成覆盖第一鳍片的顶面和侧壁(即，包围)的具有第一厚度的第一栅极电介质。方法100继续到步骤112，在步骤112中去除感光层。方法100继续到步骤114，在步骤114中形成覆盖第二鳍片的顶面和侧壁(即，包围)的第二栅极电介质，该第二栅极电介质具有小于第一厚度的第二厚度。方法100继续到步骤116，在步骤116中形成跨过第一栅极电介质和第二栅极电介质两者的导电栅极带。下面的论述示出了根据图1的方法的实施例。
图2至图10B是根据本发明的各个实施例在各个制造阶段的FinFET200的示意性剖面图。如本发明中所应用的，FinFET 200是指任何基于鳍片的多栅极晶体管。FinFET 200可以包括在微处理器、存储单元和/或其他集成电路(IC)中。可以注意到，图1的方法不能制造出完整的FinFET 200。可以采用互补金属氧化物半导体(CMOS)技术加工制造出完整的FinFET200。因此，可以理解，可以在图1的方法100之前、期间以及之后提供额外的工艺，并且在此对一些其他工艺仅进行简要描述。而且，为了更好地理解本发明，对图1至图10B进行了简化。例如，尽管附图示出的是FinFET200，但是可以理解，IC可以包括许多其他器件，包括电阻器、电容器、电感器、熔丝和/或本领域中已知的其他器件。
参考图2，提供了衬底202。在一个实施例中，衬底202包括晶体硅衬底(例如，晶圆)。根据设计需要(例如，p型衬底或n型衬底)，衬底202可以包括各种掺杂区域。在一些实施例中，掺杂区域可以掺杂有p型或n型掺杂剂。例如，掺杂区域可以掺杂有p型掺杂剂(诸如，硼或BF2)；n型掺杂剂(诸如，磷或砷)；和/或其组合。掺杂区域可以被配置用于n型FinFET或可选地被配置用于p型FinFET。
衬底202可以可选地包括一些其他适当的元素半导体(诸如，金刚石或锗)；适当的化合物半导体(诸如，砷化镓、碳化硅、砷化铟、或磷化铟)；或适当的合金半导体(诸如，碳化硅锗、磷化镓砷或磷化镓铟)。另外，衬底202可以包括外延层(epi-layer)，可以是应变的用于增强性能，和/或可以包括绝缘体上硅(SOI)结构。
在蚀刻至衬底202内之后，形成了在衬底顶面上方延伸的鳍片，其中，每个鳍片均具有顶面和侧壁。在一些实施例中，在半导体衬底202上形成焊盘层204a和掩模层204b。焊盘层204a可以是例如采用热氧化工艺形成的包含氧化硅的薄膜。焊盘层204a可以充当半导体衬底202和掩模层204b之间的粘合层。焊盘层204a还可以充当用于蚀刻掩模层204b的蚀刻停止层。在一些实施例中，掩模层204b由氮化硅例如采用低压化学汽相沉积(LPCVD)或等离子体增强化学汽相沉积(PECVD)形成。掩模层204b可以用作后续光刻工艺期间的硬掩模。在掩模层204b上形成感光层206，然后对其进行图案化，从而在感光层206中形成开口208。
参考图3，通过开口208蚀刻掩模层204b和焊盘层204a，从而暴露出下面的半导体衬底202。然后，对暴露出的半导体衬底202进行蚀刻以形成具有衬底顶面202s的沟槽210。半导体衬底202位于沟槽210之间的部分形成了多个完全相同的半导体鳍片。在一些实施例中，多个完全相同的半导体鳍片包括第一鳍片212_1以及第二鳍片212_2。在可选的实施例中，多个完全相同的半导体鳍片包括第一鳍片212_1、第二鳍片212_2以及第三鳍片212_3。沟槽210可以是彼此平行的并且在位置上彼此紧挨着的带(在俯视图中)。例如，沟槽210之间的间隔S可以小于约30nm。在一些实施例中，沟槽210之间的间隔S可以在约30nm和约15nm之间。在其他实施例中，沟槽210之间的间隔S可以在约15nm和约2nm之间。然后，去除感光层206。接着，可以实施清洗来去除半导体衬底202的自然氧化物。可以使用稀氢氟(DHF)酸来实施清洗。
沟槽210的深度D可以在约
Figure BDA0000137217140000061
和约
Figure BDA0000137217140000062
之间，而沟槽210的宽度W在约
Figure BDA0000137217140000063
和约之间。在一些实施例中，沟槽210的纵横比(D/W)大于约7.0。在其他实施例中，纵横比可以大于约8.0，然而纵横比也可以低于约7.0或在7.0和8.0之间。然而，本领域的技术人员将意识到，整个说明书中所叙述的尺寸和值仅仅是实例，并且可以对其进行改变以适应不同级别的集成电路。
在鳍片之间可以形成绝缘层，该绝缘层从衬底顶面202s沿着鳍片的一部分向上延伸，从而使鳍片彼此隔离。在一些实施例中，任选地在沟槽210中形成衬垫氧化物(未示出)。在一些实施例中，衬垫氧化物可以是厚度在约
Figure BDA0000137217140000065
至约
Figure BDA0000137217140000066
之间的热氧化物。在其他实施例中，可以采用原位水汽生成(ISSG)等形成衬垫氧化物。围绕着沟槽210的角落形成衬垫氧化物，这减小了电场并且由此改善了所得到的集成电路(IC)的性能。
在一些实施例中，然后，用介电材料216填充沟槽210。图4示出了在沉积介电材料216之后所得到的结构。介电材料216可以包括氧化硅，然而也可以使用其他介电材料，诸如，氮化硅、氮氧化硅、氟化物掺杂的硅酸盐玻璃(FSG)或低k介电材料。在一些实施例中，可以采用高密度等离子体(HDP)CVD工艺，使用硅烷(SiH4)和氧气(O2)作为反应前体来形成介电材料216。在其他实施例中，可以采用次常压CVD(SACVD)工艺或高纵横比工艺(HARP)来形成介电材料216，其中，工艺气体可以包括正硅酸四乙酯(TEOS)和臭氧(O3)。在又一些实施例中，可以采用旋涂电介质(SOD)工艺形成介电材料216，诸如，氢倍半硅氧烷(HSQ)或甲基倍半硅氧烷(MSQ)。
在一些实施例中，然后实施化学机械抛光(CMP)，接着去除掩模层204b和焊盘层204a，产生图5中所示的结构。沟槽210中剩余部分的介电材料216在下文中被称为绝缘层217。掩模层204b如果是由氮化硅形成的，则可以采用湿式工艺使用热H3PO4来去除，同时，焊盘层204a如果由氧化硅形成，则可以使用稀HF酸来去除。在可选的实施例中，可以在凹进绝缘层217之后去除掩模层204b和焊盘层204a，该凹进步骤在图6中示出。
如图6中所示，通过蚀刻步骤凹进绝缘层217，得到凹槽214，从而形成多个半导体鳍片(表示为212_1、212_2和212_3)的多个上部(表示为222_1、222_2和222_3)。在一些实施例中，剩下的绝缘层217可以包括用于隔离第一鳍片212_1和第二鳍片212_2的第一绝缘层217_1以及用于隔离第一鳍片212_1和第三鳍片212_3的第二绝缘层217_2。在一些实施例中，可以采用湿式蚀刻工艺(例如，通过将FinFET 200浸渍在氢氟酸(HF)中)来实施蚀刻步骤。在其他实施例中，可以采用干式蚀刻工艺来实施蚀刻步骤，例如，可以使用CHF3或BF3作为蚀刻气体来实施干式蚀刻工艺。
在一些实施例中，剩下的绝缘层217包括平坦顶面217t。在其他实施例中，剩下的绝缘层217包括弯曲顶面(未示出)。另外，在剩下的绝缘层217的平坦顶面217t上方伸出的多个半导体鳍片的多个上部被用于形成FinFET 200的沟道区域。换言之，第一鳍片212_1和第二鳍片212_2之间的剩下的绝缘层217_1从衬底顶面202s沿着鳍片212_1、212_2的一部分向上延伸。第一鳍片212_1和第三鳍片212_3之间的剩下的绝缘层217_2从衬底顶面202s沿着鳍片212_1、212_3的一部分向上延伸。在一些实施例中，多个半导体鳍片的多个上部中的每个均包括顶面(表示为222t_1、222t_2和222t_3)以及侧壁(表示为222s_1、222s_2和222s_3)。半导体鳍片的上部的高度H可以在15nm和约50nm之间，然而该高度也可以更大或更小。
在一些实施例中，到目前为止的工艺步骤已经提供了具有在衬底顶面202s上方延伸的第一鳍片212_1和第二鳍片212_2的衬底202，其中，鳍片212_1、212_2中的每个均具有顶面222t_1、222t_2以及侧壁222s_1、222s_2，其中，第一鳍片212_1和第二鳍片212_2之间的绝缘层217从衬底顶面202s沿着鳍片212_1、212_2的一部分向上延伸。然后，形成导电栅极带用于覆盖多个鳍片212_1、212_2的顶面222t_1、222t_2和侧壁222s_1、222s_2，从而在鳍片212_1、212_2之间建立起电连接以形成FinFET。应该注意到，对FinFET制造而言，由多个完全相同的鳍片形成FinFET是可行的，但如果FinFET所包括的鳍片多于其所需量，那么这可能会提供过量的导通电流(on-current)，从而在使用FinFET时降低了电路设计的灵活性。
因此，下面参考图7至图10B论述的加工可以在选定的鳍片上形成较薄的栅极电介质，从而启动FinFET的所选鳍片的沟道区域，但也可以在未选定的鳍片上形成较厚的栅极电介质，从而禁用FinFET的未选鳍片的沟槽区域。该加工有助于避免与FinFET的过量导通电流相关的问题，从而提高了FinFET电路设计的灵活性。
参考图7，通过适当的工艺(诸如，旋涂)在第一鳍片212_1和第二鳍片212_2上方形成感光层218。在一些实施例中，对感光层218进行图案化，从而暴露出位于绝缘层217上方的部分第一鳍片212_1，但仍覆盖第二鳍片212_2。
图8A示出了在形成覆盖第一鳍片212_1的顶面222t_1x和侧壁222s_1x的第一栅极电介质224a之后的图7的FinFET 200。采用等离子体掺杂工艺220实施形成第一栅极电介质224a的步骤，由此避免对感光层218造成损伤。图8B示出了在形成覆盖第一鳍片212_1的顶面222t_1y的第一栅极电介质224b之后的图7的FinFET 200。采用等离子体掺杂工艺220实施形成第一栅极电介质224b的步骤，由此避免对感光层218造成损伤。在一些实施例中，等离子体掺杂工艺220包括含氧等离子体掺杂工艺。例如，在功率为约260至2500W，偏压为约-200V至-20kV以及压力为约1至50mTorr的条件下，使用O2、O3或H2O作为掺杂气体来实施等离子体掺杂工艺220的步骤。然后，去除感光层218。
应该注意到，可以对等离子体掺杂工艺220中所用的偏压进行调整，以容许更好地控制第一栅极电介质224a或224b的厚度，从而实现用于氧化第一鳍片212_1所期望的轮廓。例如，等离子体掺杂工艺直接使用流入反应室中进行反应的等离子体离子，由此在鳍片的暴露的表面上形成反应边界层，并且该边界层可以根据掺杂剂浓度的变化而发生改变。
相反地，脉冲等离子体掺杂的概念是采用通过加电压/不加电压控制的间歇电压法使用进入到反应室中的气流，从而从气体中分离出正离子。然后，正离子朝向鳍片表面运动，由此使得边界层是均匀的并且处在稳定状态下。因此，可以控制驱动力使其保持不变。
在一些实施例中，在等离子体掺杂工艺220之后对第一栅极电介质224a或224b进行退火。在可选的实施例中，在形成第二栅极电介质234(在图9A和图9B中示出)之后对第一栅极电介质224a或224b进行退火。换言之，在形成第二栅极电介质234之后可以同时对第一栅极电介质224a或224b和第二栅极电介质234进行退火。
如果等离子体掺杂使得氧气过于接近第一鳍片212_1的表面，那么第一鳍片212_1的上部的外部由于与等离子体离子反应而被部分地消耗掉，从而形成第一栅极电介质224a，而第二鳍片212_2的上部受到感光层218(在图8A中示出)的保护。因此，第一栅极电介质224a覆盖第一鳍片212_1的剩下的上部222_1x的顶面222t_1x和侧壁222s_1x。在一些实施例中，第一鳍片212_1的顶面222t_1x低于第二鳍片212_2的顶面222t_2。在其他实施例中，绝缘层217的顶面217t低于第一鳍片212_1的顶面222t_1x。在又一些实施例中，在绝缘层217上方延伸的第一鳍片212_1的上部222_1x薄于在绝缘层217上方延伸的第二鳍片212_2的上部。
如果等离子体掺杂使得氧气过于接近第一鳍片212_1的中心，那么位于绝缘层217的顶面217t上方的第一鳍片212_1的材料可能由于与等离子体离子反应而被完全消耗掉，从而形成第一栅极电介质224b(在图8B中示出)。换言之，绝缘层217的顶面217t与第一鳍片212_1的顶面222t_1y基本上共平面。在一些实施例中，第一鳍片212_1的顶面222t_1y低于第二鳍片212_2的顶面222t_2。由于操作FinFET不接通第一鳍片212_1(未选鳍片)，所以绝缘层217的顶面下方的第一鳍片212_1的其他材料消耗是允许的。
在一些实施例中，第一鳍片212_1延伸在绝缘层217上方的部分的宽度W1与第二鳍片212_2延伸在绝缘层217上方的部分的宽度W2的比值是0至0.95。在一些实施例中，第一鳍片212_1在绝缘层217上方的高度h1与第二鳍片212_2在绝缘层217上方的高度h2的比值是0至0.95。
参考图9A和图9B，在第一栅极电介质224a或224b的形成工艺以及去除感光层218之后，形成第二栅极电介质234，该第二栅极电介质234覆盖第二鳍片212_2的顶面222t_2和侧壁222s_2以及第一栅极电介质224a或224b。在一些实施例中，第二栅极电介质234包括氧化硅、氮化硅、氮氧化硅或高k电介质。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及其混合物的氧化物。可以采用适当的工艺(诸如，原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV-臭氧氧化或其组合来形成第二栅极电介质234。第二栅极电介质234可以进一步包括用于减少第二栅极电介质234和第二鳍片212_2之间的损伤的界面层(未示出)。界面层包含氧化硅。
在一些实施例中，第二栅极电介质234是具有处于约至约
Figure BDA0000137217140000102
范围内的第二厚度t2的高k介电层。在结构上，将第一栅极电介质224a或224b与第二栅极电介质234覆盖第一栅极电介质224a或224b的部分组合起来并且在下文中被称为组合栅极电介质225。因此，组合栅极电介质225的第一厚度t1是第一栅极电介质224a或224b的厚度tx与第二栅极电介质234的第二厚度t2的和。换言之，覆盖第一鳍片212_1的顶面222t_1x或222t_1y的组合栅极电介质225具有第一厚度t1，而覆盖第二鳍片212_2的顶面222t_2和侧壁222s_2的第二栅极电介质234具有小于第一厚度t1的第二厚度t2。在一些实施例中，第一厚度t1与第二厚度t2的比值是1.05至2。
参考图10A和图10B，在第二栅极电介质234形成工艺之后，随后形成导电栅极带226，该导电栅极带226跨过第一栅极电介质224a或224b以及第二栅极电介质234两者。在一些实施例中，导电栅极带226覆盖一个以上的半导体鳍片212_1、212_2，以使得到的FinFET 200包括一个以上的鳍片。在一些实施例中，导电栅极带226包括单层或多层结构。在一些实施例中，导电栅极带226包含多晶硅。另外，可以采用均匀掺杂或非均匀掺杂用多晶硅掺杂导电栅极带226。可选地，导电栅极带226包括N-功函金属，其中，晶体管是n型FinFET，其中，N-功函金属包括选自由Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn以及Zr组成的组中的金属。可选地，导电栅极带226包含P-功函金属，其中，晶体管是p型FinFET，其中，P-功函金属包括选自由TiN、WN、TaN以及Ru组成的组中的金属。在一些实施例中，导电栅极带226具有处于约30nm至约60nm范围内的厚度。可以采用适当的工艺(诸如，ALD、CVD、PVD、电镀或其组合)形成导电栅极带226。
在一些实施例中，鳍式场效应晶体管(FinFET)200包括：具有顶面202s的衬底202；在衬底顶面202s上方延伸的第一鳍片212_1和第二鳍片212_2，其中，鳍片212_1、212_2中的每个均具有顶面和侧面；位于第一鳍片212_1和第二鳍片212_2之间的绝缘层217，该绝缘层217从衬底顶面202s沿着鳍片212_1、212_2的一部分向上延伸；组合栅极电介质225和第二栅极电介质234，该组合栅极电介质225覆盖第一鳍片212_1的顶面222t_1x和侧壁222s_1x，具有第一厚度t1，该第二栅极电介质234覆盖第二鳍片212_2的顶面222t_2和侧壁222s_2，具有小于第一厚度t1的第二厚度t2；以及导电栅极带226，该导电栅极带226跨过第一栅极电介质224a或224b以及第二栅极电介质234两者。因此，申请人的制造FinFET 200的方法可以制造出在导通具有较薄栅极电介质的所选鳍片(第二鳍片)但不导通具有较厚栅极电介质的未选鳍片(第一鳍片)的时候进行工作的FinFET，从而提高了电路设计的灵活性。
可以理解，FinFET 200可以经过其他CMOS工艺来形成各种部件，诸如，源极/漏极、接触件/通孔、互连金属层、介电层、钝化层以及本领域中已知的其他部件。
根据一些实施例，鳍式场效应晶体管(FinFET)包括：具有顶面的衬底；在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，每个鳍片均具有顶面和侧壁；位于第一鳍片和第二鳍片之间的绝缘层，该绝缘层从衬底顶面沿着鳍片的一部分向上延伸；覆盖第一鳍片的顶面和侧壁且具有第一厚度的第一栅极电介质和覆盖第二鳍片的顶面和侧壁且具有小于第一厚度的第二厚度的第二栅极电介质；以及跨过第一栅极电介质和第二栅极电介质两者的导电栅极带。
根据其他实施例，鳍式场效应晶体管(FinFET)包括：具有顶面的衬底；在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，第一鳍片具有顶面，以及第二鳍片具有顶面和侧壁；位于第一鳍片和第二鳍片之间的绝缘层，该绝缘层从衬底顶面沿着鳍片的一部分向上延伸，其中，该绝缘层的顶面与第一鳍片的顶面基本上共平面；覆盖第一鳍片的顶面且具有第一厚度的第一栅极电介质和覆盖第二鳍片的顶面和侧壁且具有小于第一厚度的第二厚度的第二栅极电介质；以及跨过第一栅极电介质和第二栅极电介质两者的导电栅极带。
根据又一些实施例，一种制造鳍式场效应晶体管(FinFET)的方法包括：提供衬底，该衬底具有在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，每个鳍片均具有顶面和侧壁；在第一鳍片和第二鳍片之间形成绝缘层，该绝缘层从衬底顶面沿着鳍片的一部分向上延伸；在第一鳍片和第二鳍片上方形成感光层；图案化该感光层以暴露出位于绝缘层上方的部分第一鳍片，但仍覆盖第二鳍片；采用等离子体掺杂工艺形成具有第一厚度且覆盖第一鳍片的顶面和侧壁的第一栅极电介质；去除感光层；形成覆盖第二鳍片的顶面和侧壁且具有小于第一厚度的第二厚度的第二栅极电介质；以及形成跨过第一栅极电介质和第二栅极电介质两者的导电栅极带。
尽管已经通过实例并且根据实施例对本发明进行了描述，但可以理解，本发明并不局限于所公开的实施例。相反，本发明旨在涵盖各种改进和类似的布置(对本领域技术人员来说是显而易见的)。因此，所附权利要求的范围应该与最广泛的解释一致，以涵盖所有这些改进和类似的布置。

Claims (10)

1.一种鳍式场效应晶体管(FinFET)，包括：
衬底，具有顶面；
第一鳍片和第二鳍片，在所述衬底顶面上方延伸，其中，所述第一鳍片具有顶面和侧壁，以及所述第二鳍片具有顶面和侧壁；
绝缘层，位于所述第一鳍片和所述第二鳍片之间，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸；
第一栅极电介质和第二栅极电介质，所述第一栅极电介质覆盖所述第一鳍片的所述顶面和侧壁，所述第一栅极电介质具有第一厚度t1，所述第二栅极电介质覆盖所述第二鳍片的所述顶面和侧壁，所述第二栅极电介质具有小于所述第一厚度的第二厚度t2；以及
导电栅极带，跨过所述第一栅极电介质和所述第二栅极电介质两者。
2.根据权利要求1所述的FinFET，其中，所述第一鳍片延伸在所述绝缘层上方的部分的宽度与所述第二鳍片延伸在所述绝缘层上方的部分的宽度的比值为0至0.95。
3.根据权利要求1所述的FinFET，其中，所述第一鳍片在所述绝缘层上方的高度与所述第二鳍片在所述绝缘层上方的高度的比值为0至0.95。
4.根据权利要求1所述的FinFET，其中，所述第一厚度与所述第二厚度的比值为1.05至2。
5.根据权利要求1所述的FinFET，其中，所述导电栅极带包含N-功函金属，其中，所述晶体管是n型FinFET。
6.根据权利要求1所述的FinFET，其中，所述导电栅极带包含P-功函金属，其中，所述晶体管是p型FinFET。
7.一种鳍式场效应晶体管(FinFET)，包括：
衬底，具有顶面；
第一鳍片和第二鳍片，在所述衬底顶面上方延伸，其中，所述第一鳍片具有顶面，以及所述第二鳍片具有顶面和侧壁；
绝缘层，位于所述第一鳍片和所述第二鳍片之间，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸，其中，所述绝缘层的顶面与所述第一鳍片的所述顶面基本上共平面；
第一栅极电介质和第二栅极电介质，所述第一栅极电介质覆盖所述第一鳍片的所述顶面，所述第一栅极电介质具有第一厚度，所述第二栅极电介质覆盖所述第二鳍片的所述顶面和侧壁，所述第二栅极电介质具有小于所述第一厚度的第二厚度；以及
导电栅极带，跨过所述第一栅极电介质和所述第二栅极电介质两者。
8.一种制造鳍式场效应晶体管(FinFET)的方法，包括：
提供衬底，所述衬底具有在衬底顶面上方延伸的第一鳍片和第二鳍片，其中，所述第一鳍片具有顶面和侧壁，以及所述第二鳍片具有顶面和侧壁；
在所述第一鳍片和所述第二鳍片之间形成绝缘层，所述绝缘层从所述衬底顶面沿着所述鳍片的一部分向上延伸；
在所述第一鳍片和所述第二鳍片上方形成感光层；
图案化所述感光层以暴露出位于所述绝缘层上方的部分所述第一鳍片，但仍覆盖所述第二鳍片；
采用等离子体掺杂工艺形成具有第一厚度且覆盖所述第一鳍片的所述顶面和侧壁的第一栅极电介质；
去除所述感光层；
形成覆盖所述第二鳍片的所述顶面和侧壁且具有小于所述第一厚度的第二厚度的第二栅极电介质；以及
形成跨过所述第一栅极电介质和所述第二栅极电介质两者的导电栅极带。
9.根据权利要求8所述的方法，进一步包括：
在所述等离子体掺杂工艺之后对所述第一栅极电介质进行退火。
10.根据权利要求8所述的方法，进一步包括：
在形成所述第二栅极电介质之后，同时对所述第一栅极电介质和所述第二栅极电介质进行退火。
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