JP5432798B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 48
- 238000000034 method Methods 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000000203 mixture Substances 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 239000012298 atmosphere Substances 0.000 claims description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- -1 tungsten nitride Chemical class 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 description 13
- 230000007423 decrease Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910005793 GeO 2 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Manufacturing & Machinery (AREA)
- Composite Materials (AREA)
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- Materials Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
前記第1のゲート絶縁膜上に、金属窒化膜により構成される下部ゲート電極膜を形成する工程と、
前記下部ゲート電極膜を熱処理する工程と、
前記下部ゲート電極膜上に上部ゲート電極膜を形成する工程と、
を備える半導体装置の製造方法が提供される。
以下、参考形態の例を付記する。
1.基板に設けられた第1の素子形成領域上に第1のゲート絶縁膜を形成する工程と、
前記第1のゲート絶縁膜上に、金属窒化膜により構成される下部ゲート電極膜を形成する工程と、
前記下部ゲート電極膜を熱処理する工程と、
前記下部ゲート電極膜上に上部ゲート電極膜を形成する工程と、
を備える半導体装置の製造方法。
2.1.に記載の半導体装置の製造方法において、
前記下部ゲート電極膜を形成する工程の前に、前記基板に設けられた第2の素子形成領域上に第2のゲート絶縁膜を形成する工程を備え、
前記下部ゲート電極膜を形成する工程において、前記第2のゲート絶縁膜上にも前記下部ゲート電極膜を形成し、
前記下部ゲート電極膜を形成する工程と前記下部ゲート電極膜を熱処理する工程との間に、前記第2のゲート絶縁膜上に位置する前記下部ゲート電極膜上にマスク膜を形成する工程を有し、
前記上部ゲート電極膜を形成する工程において、前記第2のゲート絶縁膜上に位置する前記下部ゲート電極膜上にも前記上部ゲート電極膜を形成する半導体装置の製造方法。
3.1.または2.に記載の半導体装置の製造方法において、
前記下部ゲート電極膜は窒化チタニウム、窒化タンタル、窒化タングステン、または窒化モリブデンのいずれかにより構成される半導体装置の製造方法。
4.1.ないし3.いずれか1項に記載の半導体装置の製造方法において、
前記上部ゲート電極膜はシリコン、ゲルマニウム、またはシリコンとゲルマニウムの混合物のいずれかにより構成される半導体装置の製造方法。
5.1.ないし4.いずれか1項に記載の半導体装置の製造方法において、
前記第1の素子形成領域に形成されるトランジスタがnチャネル型である半導体装置の製造方法。
6.2.ないし5.いずれか1項に記載の半導体装置の製造方法において、
前記下部ゲート電極膜を熱処理する工程と前記上部ゲート電極膜を形成する工程との間に、前記マスク膜を除去する工程をさらに備える半導体装置の製造方法。
7.2.ないし5.いずれか1項に記載の半導体装置の製造方法において、
前記マスク膜はシリコン、ゲルマニウム、またはシリコンとゲルマニウムの混合物である半導体装置の製造方法。
8.2.ないし6.いずれか1項に記載の半導体装置の製造方法において、
前記マスク膜はシリコン酸化膜である半導体装置の製造方法。
9.1.ないし8.いずれか1項に記載の半導体装置の製造方法において、
前記下部ゲート電極膜を熱処理する工程における雰囲気は真空又は窒素雰囲気である半導体装置の製造方法。
10.基板と、
前記基板に設けられた第1の素子形成領域上に形成された第1のゲート絶縁膜と、
前記基板に設けられた第2の素子形成領域上に形成された第2のゲート絶縁膜と、
前記第1のゲート絶縁膜上、及び前記第2のゲート絶縁膜上に形成され、金属窒化膜により構成される下部ゲート電極膜と、
前記第2のゲート絶縁膜上に位置する前記下部ゲート電極膜上に形成されたマスク膜と、
前記下部ゲート電極膜上及び前記マスク膜上に形成された上部ゲート電極膜と、
を備える半導体装置。
20 素子形成領域
30 素子形成領域
50 素子分離領域
60 エクステンション領域
70 ソース・ドレイン領域
100 ゲート絶縁膜
120 ゲート絶縁膜
200 下部ゲート電極膜
220 上部ゲート電極膜
240 ゲート電極
250 マスク膜
280 オフセットスペーサ
Claims (6)
- 基板に設けられた第1の素子形成領域上に第1のゲート絶縁膜を形成する工程と、
前記第1のゲート絶縁膜上に、金属窒化膜により構成される下部ゲート電極膜を形成する工程と、
前記下部ゲート電極膜を熱処理する工程と、
前記下部ゲート電極膜上に上部ゲート電極膜を形成する工程と、
を備え、
前記下部ゲート電極膜を形成する工程の前に、前記基板に設けられた第2の素子形成領域上に第2のゲート絶縁膜を形成する工程を備え、
前記下部ゲート電極膜を形成する工程において、前記第2のゲート絶縁膜上にも前記下部ゲート電極膜を形成し、
前記下部ゲート電極膜を形成する工程と前記下部ゲート電極膜を熱処理する工程との間に、前記第2のゲート絶縁膜上に位置する前記下部ゲート電極膜上にマスク膜を形成する工程を有し、
前記上部ゲート電極膜を形成する工程において、前記第2のゲート絶縁膜上に位置する前記下部ゲート電極膜上にも前記上部ゲート電極膜を形成し、
前記下部ゲート電極膜を熱処理する工程と前記上部ゲート電極膜を形成する工程との間に、前記マスク膜を除去する工程をさらに備える半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記下部ゲート電極膜は窒化チタニウム、窒化タンタル、窒化タングステン、または窒化モリブデンのいずれかにより構成される半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記上部ゲート電極膜はシリコン、ゲルマニウム、またはシリコンとゲルマニウムの混合物のいずれかにより構成される半導体装置の製造方法。 - 請求項1ないし3いずれか1項に記載の半導体装置の製造方法において、
前記第1の素子形成領域に形成されるトランジスタがnチャネル型である半導体装置の製造方法。 - 請求項1ないし4いずれか1項に記載の半導体装置の製造方法において、
前記マスク膜はシリコン酸化膜である半導体装置の製造方法。 - 請求項1ないし5いずれか1項に記載の半導体装置の製造方法において、
前記下部ゲート電極膜を熱処理する工程における雰囲気は真空又は窒素雰囲気である半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010077975A JP5432798B2 (ja) | 2010-03-30 | 2010-03-30 | 半導体装置の製造方法 |
US12/929,938 US8329540B2 (en) | 2010-03-30 | 2011-02-25 | Semiconductor device and manufacturing method thereof |
CN201110076960.2A CN102208347B (zh) | 2010-03-30 | 2011-03-23 | 半导体器件及其制造方法 |
US13/620,767 US20130009234A1 (en) | 2010-03-30 | 2012-09-15 | Semiconductor device and manufacturing method thereof |
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JP2010077975A JP5432798B2 (ja) | 2010-03-30 | 2010-03-30 | 半導体装置の製造方法 |
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JP2011210997A JP2011210997A (ja) | 2011-10-20 |
JP5432798B2 true JP5432798B2 (ja) | 2014-03-05 |
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JP2010077975A Active JP5432798B2 (ja) | 2010-03-30 | 2010-03-30 | 半導体装置の製造方法 |
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US (2) | US8329540B2 (ja) |
JP (1) | JP5432798B2 (ja) |
CN (1) | CN102208347B (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0855857A (ja) * | 1994-08-15 | 1996-02-27 | Yamaha Corp | 絶縁膜加工法 |
JP2004172311A (ja) * | 2002-11-19 | 2004-06-17 | Renesas Technology Corp | 半導体装置の製造方法 |
JP3790237B2 (ja) * | 2003-08-26 | 2006-06-28 | 株式会社東芝 | 半導体装置の製造方法 |
JP4143505B2 (ja) * | 2003-09-03 | 2008-09-03 | 株式会社半導体理工学研究センター | Mos型半導体装置及びその製造方法 |
KR100868768B1 (ko) * | 2007-02-28 | 2008-11-13 | 삼성전자주식회사 | Cmos 반도체 소자 및 그 제조방법 |
JP5349903B2 (ja) * | 2008-02-28 | 2013-11-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
-
2010
- 2010-03-30 JP JP2010077975A patent/JP5432798B2/ja active Active
-
2011
- 2011-02-25 US US12/929,938 patent/US8329540B2/en not_active Expired - Fee Related
- 2011-03-23 CN CN201110076960.2A patent/CN102208347B/zh active Active
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2012
- 2012-09-15 US US13/620,767 patent/US20130009234A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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US8329540B2 (en) | 2012-12-11 |
CN102208347B (zh) | 2015-04-15 |
CN102208347A (zh) | 2011-10-05 |
US20110241097A1 (en) | 2011-10-06 |
JP2011210997A (ja) | 2011-10-20 |
US20130009234A1 (en) | 2013-01-10 |
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