US20130009234A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- US20130009234A1 US20130009234A1 US13/620,767 US201213620767A US2013009234A1 US 20130009234 A1 US20130009234 A1 US 20130009234A1 US 201213620767 A US201213620767 A US 201213620767A US 2013009234 A1 US2013009234 A1 US 2013009234A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title description 20
- 238000009413 insulation Methods 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention concerns a method of manufacturing a semiconductor device having a field effect transistor, and the semiconductor device.
- MOSFETs metal-oxide-semiconductor field effect transistors
- an insulation layer having a higher dielectric constant (High-k material) than SiO 2 or SiON as a gate insulation film and using a metal or a metal nitride as a gate electrode. This technique can improve the current driving performance.
- Non-patent document 1 describes use of an Si/metal nitride film where Si is stacked on a metal nitride film as a gate electrode.
- Non-document 2 2008 Symposium on VLST Technology Digest of Technical Papers, pp 48 to 49, written by M. Kadoshima, et al.(Non-document 2) describes that an apparent work function of a gate electrode can be controlled by adjusting the thickness of a metal nitride film used for a gate electrode. Specifically, the non-patent document 2 describes that an apparent work function of the gate electrode increases as the thickness of a metal nitride film used for the gate electrode increases more.
- a threshold voltage Vt of pMOSFET is lowered (absolute value for negative Vt value is decreased) as the apparent work function of the gate electrode increases and the threshold voltage Vt of nMOSFET increases (absolute value for positive Vt value is further increased).
- the non-patent document 2 describes that a CMOSFET in which both of a pMOSFET and an nMOSFET have lower threshold value voltages (small absolute value for Vt value) by controlling the threshold voltage Vt depending on the thickness of the metal nitride film.
- the present inventor has recognized as follows.
- a gate electrode is formed by using the structure described in the non-patent document 1 for a gate electrode, and then impurities introduced into source-drain regions are activated electrically by a heat treatment at high temperature, there was a problem that the apparent work function of the gate electrode is changed.
- the thickness of the metal nitride film that forms the gate electrode varies in a wafer plane and, accordingly, the threshold voltage Vt of the gate electrode varies in the wafer plane.
- the threshold voltage Vt varies in the wafer plane, it becomes difficult to mass-produce semiconductor integrated circuit devices by using a semiconductor wafer of a large diameter. Accordingly, it is necessary that fluctuation of the threshold voltage Vt can be suppressed by other methods.
- a method of manufacturing a semiconductor device includes:
- the threshold voltage of a gate electrode is lowered by performing a heat treatment to a gate electrode film comprising a metal nitride film in an open state.
- the heat treatment is performed to the lower gate electrode film comprising the metal nitride film before formation of the upper gate electrode film. Accordingly, variation of the work function of the gate electrode can be suppressed in an MOSFET in which the gate electrode comprises the metal nitride film.
- a semiconductor device includes a substrate, a first gate insulation film formed over a first device forming region disposed in the substrate, a second gate insulation film formed over a second device forming region disposed in the substrate, a lower gate electrode film formed over the first insulation film and the second gate insulation film and having a metal nitride film, a mask film formed over the lower gate electrode film situated over the second gate insulation film, and an upper gate electrode film formed over the lower gate electrode film and the mask film.
- a current driving performance can be improved in the MOSFET in which the gate electrode comprises the metal nitride film.
- FIG. 1A to FIG. 1D are cross sectional views showing a method of manufacturing a semiconductor device according to a first embodiment
- FIG. 2 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown in FIG. 1 ;
- FIG. 3 is a graph showing a correlation between a heat treatment temperature and a threshold voltage of a gate electrode in the method of manufacturing the semiconductor device shown in FIG. 2 ;
- FIG. 4A to FIG. 4E are cross sectional views showing a method of manufacturing a semiconductor device according to a second embodiment
- FIG. 5 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown in FIG. 4 ;
- FIG. 6 is a cross sectional view showing a semiconductor device according to a third embodiment.
- FIG. 1A to FIG. 1D are cross sectional views showing the method of manufacturing the semiconductor device according to the first embodiment.
- FIG. 2 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown in FIG. 1A to FIG. 1D .
- a gate insulation film 100 is formed over a device forming region 20 disposed in a substrate 10 .
- a lower gate electrode film 200 is formed over the gate insulation film 100 .
- a heat treatment is performed to the lower gate electrode film 200 .
- an upper gate electrode film 220 is formed over the lower gate electrode film 200 .
- a semiconductor device shown in FIG. 2 is formed by way of an etching step and an ion implantation step.
- FIG. 1A device isolation regions 50 are formed in the substrate 10 .
- the device forming region 20 having the transistor formed therein is isolated.
- the device forming region 20 is a region for nMOSFET.
- the substrate 10 comprises, for example, Si, Ge, or a mixture of Si and Ge.
- the gate insulation film 100 is deposited over the device forming region 20 .
- the gate insulation film 100 is formed, for example, by growing HfO 2 or HfZrO x to several nm on SiO 2 or SiON, for example, of about 1 nm thickness, and performing a heat treatment at about 850° C.
- the gate insulation film 100 may be formed, for example, of an SiO 2 film, a GeO 2 film, a laminate film of a CVD-SiO 2 film and a High-k film (HfO 2 or HfZrO x ), or a single layer of High-k film (HfO 2 or HfZrO x ), etc., formed by a CVD method.
- a lower gate electrode film 200 is deposited over the gate insulation film 100 .
- the lower gate electrode film 200 comprises, for example, TiN, TaN, WN, or MoN. Further, the lower gate electrode film 200 has a thickness, for example, of 3 to 10 nm.
- a heat treatment is performed in a state where the lower electrode film 200 is exposed as shown in FIG. 1C .
- the heat treatment to the lower gate electrode film 200 is performed at a temperature, for example, of 600° C. or higher. Further, the heat treatment for the lower gate electrode film 200 is performed, for example, in a vacuum or a nitrogen atmosphere.
- an upper gate electrode film 220 is deposited over the lower gate electrode film 200 .
- the gate electrode film 220 comprises, for example, Si, Ge, or a mixture of Si and Ge. Then, the lower gate electrode film 200 and the upper gate electrode film 220 are removed selectively to form a gate electrode 240 as shown in FIG. 2 .
- impurity ions are injected into the substrate 10 by using the device isolation regions 50 and the gate electrode 240 as a mask.
- source/drain extension regions 60 are formed in the device forming region 20 .
- an insulation film is foiled over the gate electrode 240 , over the device forming region 20 , and over the device isolation region 50 , and the insulation film is etched back.
- an offset spacer 280 is formed on the side wall of the gate electrode 240 as shown in FIG. 2 .
- impurity ions are injected into the substrate 10 by using the gate electrode 240 , the offset spacer 280 , and the device isolation regions 50 as a mask.
- source/drain regions 70 are formed in the device isolation 20 as shown in FIG. 2 .
- FIG. 3 is a graph showing a correlation between a heat treatment temperature and a threshold voltage of the gate electrode in the heat treatment step for the lower gate electrode film 200 before forming the upper electrode 220 .
- the threshold voltage Vt of the gate electrode of the nMOSFET is lowered (absolute value for positive value is lowered) by performing the heat treatment at 600° C. or higher in the open state of the gate electrode film comprising the metal nitride film in an nMOSFET.
- the threshold voltage Vt is lowered and a higher on current can be obtained at an identical drain voltage.
- a heat treatment is performed to the lower gate electrode film 200 comprised of the metal nitride film before formation of the upper gate electrode film 220 . That is, at the timing of performing the heat treatment, the lower gate electrode film 200 is not covered at all. In such a process, increase of the apparent work function of the gate electrode can be controlled and the current driving performance can be improved in the MOSFET in which the gate electrode comprises the metal nitride film as shown in FIG. 3 .
- FIG. 4A to FIG. 4E are cross sectional views showing a method of manufacturing a semiconductor device according to a second embodiment, which corresponds to FIGS. 1A to 1D .
- FIG. 5 is a cross sectional view showing the semiconductor device formed by the manufacturing method shown in FIGS. 4A to 4E which corresponds to the first embodiment.
- the method of manufacturing the semiconductor device shown in FIGS. 4A to 4E is identical with the method of manufacturing the semiconductor device shown in FIGS. 1A to 1D excepting that it includes the step of forming and removing a mask 250 .
- a semiconductor device shown in FIG. 5 has the similar configuration as the semiconductor device shown in FIG. 2 except that a plurality of transistors are provided.
- the method of manufacturing the semiconductor device according to the second embodiment is to be described specifically with reference to FIG. 4A to FIG. 4E and FIG. 5 .
- device isolation regions 50 are formed in the substrate 10 , and a device forming region 20 and a device forming region 30 are isolated from each other ( FIG. 4A ).
- the device forming region 20 is a region for nMOSFET and the device forming region 30 is a region for pMOSFET.
- a gate insulation film 100 is formed over the device forming region 20 and a gate insulation film 120 is formed over the device forming region 30 ( FIG. 4B ).
- the step of forming the gate insulation film 100 and the gate insulation film 120 are performed, for example, in one identical step.
- the lower gate electrode film 200 is formed ( FIG. 4C ).
- the forming procedures described above are similar with those of the first embodiment.
- a mask film 250 is formed as shown in FIG. 4D .
- the mask film 250 is formed over the lower gate electrode film 200 situated over the gate insulation film 120 .
- the mask film 250 is formed, for example, by depositing SiO 2 using plasma CVD and selectively removing the mask film over the lower gate electrode film 200 situated over the gate insulation film 100 .
- a heat treatment is performed to the lower gate electrode 200 .
- the mask film 250 over the gate electrode film 200 is removed.
- an upper gate electrode film 220 is deposited over the lower gate electrode film 200 ( FIG. 4E ). Then, a gate electrode 240 , an extension region 60 , an offset spacer 280 , and source/drain regions 70 are formed. The forming procedures are similar with those of the first embodiment. Thus, a semiconductor region shown in FIG. 5 is formed.
- the heat treatment is performed to the lower gate electrode film 200 comprising the metal nitride film before forming the upper gate electrode film 220 . Accordingly, the same effect as that of the first embodiment can be obtained.
- the threshold voltage Vt of the gate electrode of the pMOSFET is lowered (absolute value for the negative Vt value is decreased) by performing a heat treatment to a gate electrode film comprising a metal nitride film while covering the electrode film with the mask film.
- the threshold voltage Vt is lowered as the work function is increased and higher on current is obtained at an identical drain voltage.
- the heat treatment is performed to the lower gate electrode film 200 after forming the mask film 250 over the lower gate electrode film 200 situated over the gate insulation film 120 . That is, at the timing of performing the heat treatment, the lower gate electrode film 200 situated over the gate insulation film 200 is covered with the mask film. Accordingly, decrease in the apparent work function of the gate electrode can be controlled and the current driving performance can be improved in a selected pMOSFET among a plurality of MOSFETs formed in the substrate.
- the threshold voltage Vt can be lowered by the heat treatment only for one nMOSFET selected from the plurality of MOSFETs. This enables to arrange one nMOSFET and other nMOSFETs of different threshold voltages in one substrate without introducing impurities.
- FIG. 6 is a cross sectional view showing a semiconductor device according to a third embodiment, which corresponds to FIG. 5 for the second embodiment.
- the method of manufacturing the semiconductor device shown in FIG. 6 is similar with the method of manufacturing the semiconductor device according to the second embodiment shown in FIG. 4 except that the mask film is not removed after the step of performing heat treatment to the lower gate electrode gate 200 .
- the semiconductor device shown in FIG. 6 has a configuration identical with that of the semiconductor device shown in FIG. 5 excepting that a mask film 250 is situated between the lower gate electrode film 200 and the upper gate electrode film 220 situated over the gate insulation film 120 .
- the mask film 250 shown in FIG. 6 comprises, for example, Si, Ge, or a mixture of Si and Ge. Further, the mask film 250 is deposited, for example, to a thickness of about 10 nm by PVD.
- a heat treatment is performed to the lower gate electrode film 200 comprising the metal nitride film before forming the upper gate electrode film 220 . Further, a heat treatment is performed to the lower gate electrode film 200 after forming the mask film 250 over the lower gate electrode 200 situated over the gate insulation film 120 . Accordingly, the same effects as those of the second embodiment can be obtained.
- this embodiment does not have the step of removing the mask film 250 . Accordingly, the number of steps can be saved in the manufacture of the semiconductor device.
Abstract
A semiconductor device includes a substrate, a first gate insulation film formed over a first device forming region disposed in the substrate, a second gate insulation film formed over a second device forming region disposed in the substrate, a lower gate electrode film formed over the first gate insulation film and over the second gate insulation film and comprising a metal nitride film; a mask film formed over the lower gate electrode film situated over the second gate insulation film, and an upper gate electrode film formed over the lower gate electrode film and over the mask film.
Description
- The present application is a Divisional Application of U.S. patent application Ser. No. 12/929,938, filed on Feb. 25, 2011, which is based on and claims priority from Japanese patent application No. 2010-77975, filed on Mar. 30, 2010, the entire contents of which is incorporated herein by reference.
- The disclosure of Japanese Patent Application No. 2010-77975 filed on Mar. 30, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety
- 1. Field of the Invention
- The present invention concerns a method of manufacturing a semiconductor device having a field effect transistor, and the semiconductor device.
- 2. Description of Related Art
- In metal-oxide-semiconductor field effect transistors (MOSFETs), there is a technique of using an insulation layer having a higher dielectric constant (High-k material) than SiO2 or SiON as a gate insulation film and using a metal or a metal nitride as a gate electrode. This technique can improve the current driving performance.
- IEEE Electron Device Letters, vol. 25, No. 5, 2004, pp 337 to 339, written by H. Y. Yu (Non-patent document 1) describes use of an Si/metal nitride film where Si is stacked on a metal nitride film as a gate electrode.
- 2008 Symposium on VLST Technology Digest of Technical Papers, pp 48 to 49, written by M. Kadoshima, et al.(Non-document 2) describes that an apparent work function of a gate electrode can be controlled by adjusting the thickness of a metal nitride film used for a gate electrode. Specifically, the non-patent document 2 describes that an apparent work function of the gate electrode increases as the thickness of a metal nitride film used for the gate electrode increases more. When the apparent work function of the gate electrode increases, a threshold voltage Vt of pMOSFET is lowered (absolute value for negative Vt value is decreased) as the apparent work function of the gate electrode increases and the threshold voltage Vt of nMOSFET increases (absolute value for positive Vt value is further increased). The non-patent document 2 describes that a CMOSFET in which both of a pMOSFET and an nMOSFET have lower threshold value voltages (small absolute value for Vt value) by controlling the threshold voltage Vt depending on the thickness of the metal nitride film.
- The present inventor has recognized as follows. When a gate electrode is formed by using the structure described in the non-patent document 1 for a gate electrode, and then impurities introduced into source-drain regions are activated electrically by a heat treatment at high temperature, there was a problem that the apparent work function of the gate electrode is changed. It may be considered to solve the problem described above by controlling the film thickness while considering the fluctuation of the work function by applying the technique described in the non-patent document 2. In this case, however, the thickness of the metal nitride film that forms the gate electrode varies in a wafer plane and, accordingly, the threshold voltage Vt of the gate electrode varies in the wafer plane. When the threshold voltage Vt varies in the wafer plane, it becomes difficult to mass-produce semiconductor integrated circuit devices by using a semiconductor wafer of a large diameter. Accordingly, it is necessary that fluctuation of the threshold voltage Vt can be suppressed by other methods.
- According to an aspect of the present invention, a method of manufacturing a semiconductor device includes:
-
- forming a first gate insulation film over a first device forming region disposed in a substrate,
- forming a lower gate electrode film comprising a metal nitride film over the first gate insulation film,
- a heat treatment is performed to the lower gate electrode film, and
- forming an upper gate electrode film over the lower gate electrode film.
- In an nMOSFET, the threshold voltage of a gate electrode is lowered by performing a heat treatment to a gate electrode film comprising a metal nitride film in an open state. According to the invention, the heat treatment is performed to the lower gate electrode film comprising the metal nitride film before formation of the upper gate electrode film. Accordingly, variation of the work function of the gate electrode can be suppressed in an MOSFET in which the gate electrode comprises the metal nitride film.
- According to another aspect of the present invention, a semiconductor device includes a substrate, a first gate insulation film formed over a first device forming region disposed in the substrate, a second gate insulation film formed over a second device forming region disposed in the substrate, a lower gate electrode film formed over the first insulation film and the second gate insulation film and having a metal nitride film, a mask film formed over the lower gate electrode film situated over the second gate insulation film, and an upper gate electrode film formed over the lower gate electrode film and the mask film.
- According to the invention, a current driving performance can be improved in the MOSFET in which the gate electrode comprises the metal nitride film.
-
FIG. 1A toFIG. 1D are cross sectional views showing a method of manufacturing a semiconductor device according to a first embodiment; -
FIG. 2 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown inFIG. 1 ; -
FIG. 3 is a graph showing a correlation between a heat treatment temperature and a threshold voltage of a gate electrode in the method of manufacturing the semiconductor device shown inFIG. 2 ; -
FIG. 4A toFIG. 4E are cross sectional views showing a method of manufacturing a semiconductor device according to a second embodiment; -
FIG. 5 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown inFIG. 4 ; and -
FIG. 6 is a cross sectional view showing a semiconductor device according to a third embodiment. - Preferred embodiments of the invention are to be described with reference to the drawings. Throughout the drawings, identical constituent elements carry the same reference numerals for which description is optionally omitted.
-
FIG. 1A toFIG. 1D are cross sectional views showing the method of manufacturing the semiconductor device according to the first embodiment.FIG. 2 is a cross sectional view showing a semiconductor device formed by the manufacturing method shown inFIG. 1A toFIG. 1D . In the manufacturing method, agate insulation film 100 is formed over adevice forming region 20 disposed in asubstrate 10. Then, a lowergate electrode film 200 is formed over thegate insulation film 100. Further, a heat treatment is performed to the lowergate electrode film 200. Then, an uppergate electrode film 220 is formed over the lowergate electrode film 200. Subsequently, a semiconductor device shown inFIG. 2 is formed by way of an etching step and an ion implantation step. - A method of manufacturing the semiconductor device according to the first embodiment is to be described in details with reference to
FIG. 1A toFIG. 1D , andFIG. 2 . At first, as shown inFIG. 1A ,device isolation regions 50 are formed in thesubstrate 10. Thus, thedevice forming region 20 having the transistor formed therein is isolated. For example, thedevice forming region 20 is a region for nMOSFET. Thesubstrate 10 comprises, for example, Si, Ge, or a mixture of Si and Ge. Then, as shown inFIG. 1B , thegate insulation film 100 is deposited over thedevice forming region 20. Thegate insulation film 100 is formed, for example, by growing HfO2 or HfZrOx to several nm on SiO2 or SiON, for example, of about 1 nm thickness, and performing a heat treatment at about 850° C. When thesubstrate 10 comprises Ge, or a mixture of Si and Ge, thegate insulation film 100 may be formed, for example, of an SiO2 film, a GeO2 film, a laminate film of a CVD-SiO2 film and a High-k film (HfO2 or HfZrOx), or a single layer of High-k film (HfO2 or HfZrOx), etc., formed by a CVD method. - Then, as shown in
FIG. 1C , a lowergate electrode film 200 is deposited over thegate insulation film 100. The lowergate electrode film 200 comprises, for example, TiN, TaN, WN, or MoN. Further, the lowergate electrode film 200 has a thickness, for example, of 3 to 10 nm. - Then, a heat treatment is performed in a state where the
lower electrode film 200 is exposed as shown inFIG. 1C . The heat treatment to the lowergate electrode film 200 is performed at a temperature, for example, of 600° C. or higher. Further, the heat treatment for the lowergate electrode film 200 is performed, for example, in a vacuum or a nitrogen atmosphere. - As shown in
FIG. 1D , an uppergate electrode film 220 is deposited over the lowergate electrode film 200. Thegate electrode film 220 comprises, for example, Si, Ge, or a mixture of Si and Ge. Then, the lowergate electrode film 200 and the uppergate electrode film 220 are removed selectively to form agate electrode 240 as shown inFIG. 2 . - Then, as shown in
FIG. 2 , impurity ions are injected into thesubstrate 10 by using thedevice isolation regions 50 and thegate electrode 240 as a mask. Thus, source/drain extension regions 60 are formed in thedevice forming region 20. Then, an insulation film is foiled over thegate electrode 240, over thedevice forming region 20, and over thedevice isolation region 50, and the insulation film is etched back. Thus, an offsetspacer 280 is formed on the side wall of thegate electrode 240 as shown inFIG. 2 . - Then, impurity ions are injected into the
substrate 10 by using thegate electrode 240, the offsetspacer 280, and thedevice isolation regions 50 as a mask. Thus, source/drain regions 70 are formed in thedevice isolation 20 as shown inFIG. 2 . - An advantageous effect of this embodiment is to be described.
FIG. 3 is a graph showing a correlation between a heat treatment temperature and a threshold voltage of the gate electrode in the heat treatment step for the lowergate electrode film 200 before forming theupper electrode 220. The threshold voltage Vt of the gate electrode of the nMOSFET is lowered (absolute value for positive value is lowered) by performing the heat treatment at 600° C. or higher in the open state of the gate electrode film comprising the metal nitride film in an nMOSFET. In the nMOSFET, as the work function decreases, the threshold voltage Vt is lowered and a higher on current can be obtained at an identical drain voltage. - According to this embodiment, a heat treatment is performed to the lower
gate electrode film 200 comprised of the metal nitride film before formation of the uppergate electrode film 220. That is, at the timing of performing the heat treatment, the lowergate electrode film 200 is not covered at all. In such a process, increase of the apparent work function of the gate electrode can be controlled and the current driving performance can be improved in the MOSFET in which the gate electrode comprises the metal nitride film as shown inFIG. 3 . -
FIG. 4A toFIG. 4E are cross sectional views showing a method of manufacturing a semiconductor device according to a second embodiment, which corresponds toFIGS. 1A to 1D .FIG. 5 is a cross sectional view showing the semiconductor device formed by the manufacturing method shown inFIGS. 4A to 4E which corresponds to the first embodiment. The method of manufacturing the semiconductor device shown inFIGS. 4A to 4E is identical with the method of manufacturing the semiconductor device shown inFIGS. 1A to 1D excepting that it includes the step of forming and removing amask 250. A semiconductor device shown inFIG. 5 has the similar configuration as the semiconductor device shown inFIG. 2 except that a plurality of transistors are provided. - The method of manufacturing the semiconductor device according to the second embodiment is to be described specifically with reference to
FIG. 4A toFIG. 4E andFIG. 5 . At first,device isolation regions 50 are formed in thesubstrate 10, and adevice forming region 20 and adevice forming region 30 are isolated from each other (FIG. 4A ). For example, thedevice forming region 20 is a region for nMOSFET and thedevice forming region 30 is a region for pMOSFET. Then, agate insulation film 100 is formed over thedevice forming region 20 and agate insulation film 120 is formed over the device forming region 30 (FIG. 4B ). The step of forming thegate insulation film 100 and thegate insulation film 120 are performed, for example, in one identical step. Then, the lowergate electrode film 200 is formed (FIG. 4C ). The forming procedures described above are similar with those of the first embodiment. - Then, after forming the lower
gate electrode film 200, amask film 250 is formed as shown inFIG. 4D . Themask film 250 is formed over the lowergate electrode film 200 situated over thegate insulation film 120. Further, themask film 250 is formed, for example, by depositing SiO2 using plasma CVD and selectively removing the mask film over the lowergate electrode film 200 situated over thegate insulation film 100. Then, a heat treatment is performed to thelower gate electrode 200. Then, themask film 250 over thegate electrode film 200 is removed. - Then, an upper
gate electrode film 220 is deposited over the lower gate electrode film 200 (FIG. 4E ). Then, agate electrode 240, anextension region 60, an offsetspacer 280, and source/drain regions 70 are formed. The forming procedures are similar with those of the first embodiment. Thus, a semiconductor region shown inFIG. 5 is formed. - Also in this embodiment, the heat treatment is performed to the lower
gate electrode film 200 comprising the metal nitride film before forming the uppergate electrode film 220. Accordingly, the same effect as that of the first embodiment can be obtained. - Further, in a pMOSFET, the threshold voltage Vt of the gate electrode of the pMOSFET is lowered (absolute value for the negative Vt value is decreased) by performing a heat treatment to a gate electrode film comprising a metal nitride film while covering the electrode film with the mask film. In the pMOSFET, the threshold voltage Vt is lowered as the work function is increased and higher on current is obtained at an identical drain voltage.
- According to this embodiment, the heat treatment is performed to the lower
gate electrode film 200 after forming themask film 250 over the lowergate electrode film 200 situated over thegate insulation film 120. That is, at the timing of performing the heat treatment, the lowergate electrode film 200 situated over thegate insulation film 200 is covered with the mask film. Accordingly, decrease in the apparent work function of the gate electrode can be controlled and the current driving performance can be improved in a selected pMOSFET among a plurality of MOSFETs formed in the substrate. - Further, the threshold voltage Vt can be lowered by the heat treatment only for one nMOSFET selected from the plurality of MOSFETs. This enables to arrange one nMOSFET and other nMOSFETs of different threshold voltages in one substrate without introducing impurities.
-
FIG. 6 is a cross sectional view showing a semiconductor device according to a third embodiment, which corresponds toFIG. 5 for the second embodiment. The method of manufacturing the semiconductor device shown inFIG. 6 is similar with the method of manufacturing the semiconductor device according to the second embodiment shown inFIG. 4 except that the mask film is not removed after the step of performing heat treatment to the lowergate electrode gate 200. Further, the semiconductor device shown inFIG. 6 has a configuration identical with that of the semiconductor device shown inFIG. 5 excepting that amask film 250 is situated between the lowergate electrode film 200 and the uppergate electrode film 220 situated over thegate insulation film 120. - The
mask film 250 shown inFIG. 6 comprises, for example, Si, Ge, or a mixture of Si and Ge. Further, themask film 250 is deposited, for example, to a thickness of about 10 nm by PVD. - Also in this embodiment, a heat treatment is performed to the lower
gate electrode film 200 comprising the metal nitride film before forming the uppergate electrode film 220. Further, a heat treatment is performed to the lowergate electrode film 200 after forming themask film 250 over thelower gate electrode 200 situated over thegate insulation film 120. Accordingly, the same effects as those of the second embodiment can be obtained. - Further, this embodiment does not have the step of removing the
mask film 250. Accordingly, the number of steps can be saved in the manufacture of the semiconductor device. - While preferred embodiments of the invention have been descried with reference to the drawings, they are examples of the invention and various other constitutions than those described above can also be adopted.
Claims (1)
1. A semiconductor device comprising:
a substrate;
a first gate insulation film formed over a first device forming region disposed in the substrate;
a second gate insulation film formed over a second device forming region disposed in the substrate;
a lower gate electrode film formed over the first gate insulation film and over the second gate insulation film and comprising a metal nitride film;
a mask film formed over the lower gate electrode film situated over the second gate insulation film; and
an upper gate electrode film formed over the lower gate electrode film and over the mask film.
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US12/929,938 US8329540B2 (en) | 2010-03-30 | 2011-02-25 | Semiconductor device and manufacturing method thereof |
US13/620,767 US20130009234A1 (en) | 2010-03-30 | 2012-09-15 | Semiconductor device and manufacturing method thereof |
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JP4143505B2 (en) * | 2003-09-03 | 2008-09-03 | 株式会社半導体理工学研究センター | MOS type semiconductor device and manufacturing method thereof |
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US8329540B2 (en) | 2012-12-11 |
CN102208347B (en) | 2015-04-15 |
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