CN103811349A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
- Publication number
- CN103811349A CN103811349A CN201210591064.4A CN201210591064A CN103811349A CN 103811349 A CN103811349 A CN 103811349A CN 201210591064 A CN201210591064 A CN 201210591064A CN 103811349 A CN103811349 A CN 103811349A
- Authority
- CN
- China
- Prior art keywords
- layer
- grid
- pseudo
- soi
- stacking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 135
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 230000000977 initiatory effect Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 description 23
- 230000000694 effects Effects 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 230000006835 compression Effects 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000004549 pulsed laser deposition Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 241000849798 Nita Species 0.000 description 1
- 235000003976 Ruta Nutrition 0.000 description 1
- 240000005746 Ruta graveolens Species 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000005806 ruta Nutrition 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Abstract
本发明提供了一种半导体结构的制造方法,该方法包括:提供SOI衬底,该SOI衬底从上至下包括基底层(130),BOX层(110)和SOI层(100);在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层;去除伪栅堆叠形成栅极凹陷(220);d)通过所述栅极凹陷(220)对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷(220)正下方形成位于所述SOI衬底的BOX(110)层之下的应力引发区(150)。相应地,本发明还提供了一种根据上述方法形成的半导体结构。
Description
技术领域
本发明涉及半导体领域,具体地说涉及一种半导体结构及其制造方法。
背景技术
随着半导体器件制造技术的发展,具有更高性能和更强功能的集成电路要求更大的元件密度,而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小,因此半导体器件制造过程中对工艺控制的要求较高。
半导体器件通过按比例缩小来实现工作速度的提升。MOS晶体管的沟道长度也在不断地按比例缩短,但当MOS晶体管的沟道长度变得非常短时,所谓的短沟道效应(SCE),以及漏极感应势垒降低效应(Drain-Induced BarrierLowering,DIBL)给半导体器件微型化设置了严重的障碍。
由于短沟道效应会使器件性能劣化,甚至无法正常工作,因此减小短沟道效应是半导体器件研究制造中的重要课题。半导体器件内部的机械应力被广泛地用于调节器件的性能,通过在沟道施加应力的方法,可以有效减小短沟道效应。
常用的增加应力的方法是在源漏区进行操作,以便在沟道上形成拉伸或压缩应力。例如,在通用硅技术中,晶体管沟道沿着硅的{110}取向。在这种布置中,当沟道受到沿着沟道方向的压缩应力和/或沿着与沟道垂直方向的拉伸应力时,空穴的迁移率提高;而当沟道受到沿着沟道方向的拉伸应力和/或沿着与沟道垂直方向的压缩应力时,电子的迁移率增高。因此在半导体器件的沟道区引入应力,可以提高器件的性能。
使用SOI衬底代替硅衬底也可以达到减小短沟道效应和提高器件性能的效果。绝缘体上硅(Silicon On Insulator,SOI)技术是在顶部硅层和衬底体硅层之间引入了一层埋氧层。通过在绝缘体上形成半导体薄膜,SOI材料具有了体硅所无法比拟的优点:可以实现集成电路中元器件的介质隔离,彻底消除了体硅CMOS电路中的寄生闩锁效应;采用这种材料制成的集成电路还具有寄生电容小、集成密度高、速度快、工艺简单、短沟道效应小及特别适用于低压低功耗电路等优势,因此可以说SOI将有可能成为深亚微米的低压、低功耗集成电路的主流技术。
同时,SOI的异质结构为建造具有超薄硅体器件创造了机会。通过由硅电介质界面建立的天然静电屏障,超薄SOI提供一种控制短沟道效应的可选手段。
目前,有技术采用在超薄SOI MOS晶体管(Ultrathin-SOI MOSFET)的超薄BOX(Buried Oxide,埋氧)层之下形成接地层来减小短沟道效应,并控制功耗。但是如果能在此种结构的半导体器件中引入应力则可以进一步减小短沟道效应并提高半导体器件的性能。
发明内容
本发明的目的在于提供一种半导体结构及其制造方法,通过在SOI衬底的BOX层之下的体硅层中形成应力引发区,对在SOI衬底的SOI层中制造的半导体器件的沟道区引入有利应力,提高所述半导体器件的性能。
一方面,本发明提供了一种半导体结构的制造方法,该方法包括:
a)提供SOI衬底,该SOI衬底从上至下包括基底层(130),BOX层(110)和SOI层(100);
b)在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层;
c)去除伪栅堆叠形成栅极凹陷(220);
d)通过所述栅极凹陷(220)对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷(220)正下方形成位于所述SOI衬底的BOX(110)层之下的应力引发区(150)。
相应地,本发明还提供了一种半导体结构,该半导体结构包括
SOI衬底,从上至下包括SOI层、BOX层和体硅层;
形成于SOI层之上的栅极堆叠,包括栅极和栅极介质层;
应力引发区,形成在所述栅极正下方的体硅层内。
本发明提供的半导体结构及其制造方法通过离子注入和退火操作在栅极正下方的SOI衬底的BOX层之下的体硅层中形成应力引发区,所述应力引发区为在SOI衬底的SOI层中制造的半导体器件的沟道提供了有利应力,有助于提升半导体器件的性能。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1为根据本发明的半导体结构的制造方法的一个具体实施方式的流程图;
图2~图11是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明的实施例作详细描述。
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。应当注意,在附图中所图示的部件不一定按比例绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本发明。
由于本发明提供的半导体结构具有几种优选结构,下面提供一种优选结构并进行概述。
参考图10,图10示出了一种半导体结构,该半导体结构包括SOI衬底、接地层140、栅极堆叠、源/漏区160、源/漏延伸区170、应力引发区150和层间介质层250,其中:
所述SOI衬底从上至下包括SOI层100、BOX层110和体硅层130;
所述栅极堆叠包括栅极200和栅极介质层280,所述栅极介质层280、栅极200依次形成在所述SOI衬底之上;
所述源/漏区160和源/漏延伸区170形成于所述SOI层100之中,所述层间介质层250覆盖所述源/漏区160;
所述接地层140位于所述体硅层130中,所述BOX层110的下方;
所述应力引发区150形成在栅极200正下方的体硅层130内。
此外,在栅极堆叠的两侧还形成侧墙210。
所述SOI衬底至少具有三层结构,分别是:体硅层130、体硅层130之上的BOX层110,以及覆盖在BOX层110之上的SOI层100。其中,所述BOX层110的材料可以选用晶体或者非晶体氧化物、氮化物或其任意组合,优选地,通常选用SiO2。SOI层100的材料是单晶硅、Ge或Ⅲ-Ⅴ族化合物(如SiC、砷化镓、砷化铟或磷化铟等)。本发明中选用的SOI衬底是具有超薄SOI层100和超薄BOX层110的SOI衬底,其中超薄SOI层100的厚度范围为5~20nm,例如5nm、15nm或20nm;超薄BOX层110的厚度范围为5~30nm,例如5nm、20nm或30nm。
可选的,还可以在SOI衬底中还形成隔离区120,用于将所述SOI层100分割为独立的区域,用于后续加工形成晶体管结构所用。隔离区120的材料是绝缘材料,例如可以选用SiO2、Si3N4或其组合。隔离区120的宽度可以视半导体结构的设计需求决定。
栅极堆叠包括栅极200和栅极介质层280。栅极介质层280的材料可以是热氧化层,包括氧化硅、氮氧化硅,也可为高K介质。栅极200可以包括栅金属层、栅电极层、多晶硅层等结构。
侧墙210可以由氮化硅、氧化硅、氮氧化硅、碳化硅和/或其他合适的材料形成。侧墙210可以具有多层结构。侧墙210可以通过沉积-刻蚀工艺形成,其厚度范围大约是10nm-100nm。
在SOI层100内通过离子注入的方式形成源/漏区160和源/漏延伸区170。例如,对于PMOS来说,源/漏区160和源/漏延伸区170可以是P型掺杂,对于NMOS来说,源/漏区160和源/漏延伸区170可以是N型掺杂。
接地层140形成于体硅层130内靠近BOX层110的位置,例如,对于PFET或NFET可以任意采用n型或p型掺杂。在本发明的一个实施例中,应力引发区150采用碳掺杂形成于接地层140内。应力引发区150的位置在栅堆叠正下方的体硅层内(隔着BOX层),有利于为沟道区引入压应力,显著提高P型FET的性能。
下文中将结合本发明提供的半导体结构的制造方法对上述实施例进行进一步的阐述。
请参考图1,图1是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图,该方法包括:
步骤S101,提供SOI衬底,该SOI衬底从上至下包括基底层,BOX层和SOI层;
步骤S102,在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层;
步骤S103,去除伪栅堆叠形成栅极凹陷;
步骤S104,通过所述栅极凹陷对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷正下方形成位于所述SOI衬底的BOX层之下的应力引发区。
下面结合图2至图10对步骤S101至步骤S104进行说明,图2至图10是根据本发明的一个具体实施方式按照图1示出的流程制造半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。需要说明的是,本发明各个实施例的附图仅是为了示意的目的,因此没有必要按比例绘制。
参考图2~图10,执行步骤S101,提供SOI衬底,该SOI衬底包括基底层,BOX层和SOI层。
首先参考图2,其中,所述SOI衬底至少具有三层结构,分别是:体硅层130、体硅层130之上的BOX层110,以及覆盖在BOX层110之上的SOI层100。其中,所述BOX层110的材料通常选用SiO2。SOI层100的材料是单晶硅、Ge或Ⅲ-Ⅴ族化合物(如SiC、砷化镓、砷化铟或磷化铟等)。本发明中选用的SOI衬底是具有超薄SOI层100和超薄BOX层110的SOI衬底,其中SOI层100的厚度范围为5~20nm,例如5nm、15nm、20nm;BOX层110的厚度范围为5~30nm,例如5nm、20nm、30nm。
之后在该SOI衬底中还形成隔离区120,用于将所述SOI层100分割为独立的区域,用于后续加工形成晶体管结构所用,如图3所示。隔离区120的材料是绝缘材料,例如可以选用SiO2、Si3N4或其组合,隔离区120的宽度可以视半导体结构的设计需求决定。
形成隔离区120之后,通过离子注入的方式形成接地层140,参考图4。控制注入能量使得所述接地层形成于BOX层110之下。例如,对于PFET和NFET可以任意采用n型和p型掺杂。具体地,在形成接地层140的步骤中注入的离子类型取决于MOSFET的类型以及阈值电压的目标值。如果希望提高器件的阈值电压,对于NFET,可以采用p型离子,例如硼(B或BF2)或铟(In)或其组合;对于PFET,可以采用n型离子,例如砷(As)、磷(P)或其组合。如果希望减小器件的阈值电压,对于NFET,可以采用n型离子,例如砷(As)、磷(P)或其组合;对于PFET,可以采用p型离子,例如硼(B或BF2)或铟(In)或其组合。
接下来执行步骤S102,在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层。参考图5,在所述SOI衬底上(具体而言是在SOI层100上)形成伪栅堆叠,所述伪栅堆叠包括栅极介质层260和伪栅270,可以在随后的步骤中进行替代栅工艺,移除伪栅270以形成所需的栅极堆叠结构。其中,栅极介质层260的材料可以是热氧化层,包括氧化硅、氮氧化硅,也可为高K介质,例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合,其厚度在1nm~10nm之间,可以通过化学气相沉积(Chemical vapor deposition,CVD)、高密度等离子体CVD、ALD(原子层淀积)、等离子体增强原子层淀积(PEALD)、脉冲激光沉积(PLD)或其他合适的方法形成在SOI层100上。伪栅270的材料可以包括多晶硅、非晶硅或其他合适的材料。
在伪栅堆叠形成之后,可以进行退火以控制接地层140的掺杂分布,以便调节器件的开启电压。
在进行退火之后,通过低能注入的方式在所述SOI层100中形成源/漏延伸区170,参考图6。可以向所述SOI层100中注入P型或N型掺杂物或杂质。即,如果要制作的半导体器件为NMOS,则向所述SOI层100中掺杂N型杂质,例如砷和磷。如果所述半导体器件为PMOS,则向所述SOI层100中掺杂P型杂质,例如硼和铟。然后对所述半导体结构进行退火,以激活源/漏延伸区170中的掺杂。在一个实施例中,也可以不形成源/漏延伸区170。
通常地,可以考虑在源/漏延伸区170形成后,在伪栅堆叠的两侧形成侧墙210,用于将伪栅堆叠隔开。侧墙210可以由氮化硅、氧化硅、氮氧化硅、碳化硅和/或其他合适的材料形成。侧墙210可以具有多层结构。侧墙210可以通过沉积-刻蚀工艺形成,其厚度范围大约是10nm-100nm,如30nm、50nm或80nm。
形成侧墙210之后可以形成源/漏区160。源/漏区160可以通过向SOI层100中注入P型或N型掺杂物或杂质而形成,例如,对于PMOS来说,源/漏区160可以是P型掺杂,对于NMOS来说,源/漏区160可以是N型掺杂。源/漏区160可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成。在本实施例中,源/漏区160形成于SOI层100内部,在其他一些实施例中,源/漏区160可以是通过选择性外延生长所形成的提升的源漏极结构,其外延部分的顶部高于栅极堆叠底部(本说明书中所指的栅极堆叠底部意指栅极堆叠与SOI层100的交界线)。之后采用高温处理激活杂质,例如退火工艺。
在SOI衬底上形成覆盖所述源/漏区160、伪栅堆叠、侧墙210和隔离区120的层间介质层250。层间介质层250可以通过化学气相沉积(Chemical vapordeposition,CVD)、高密度等离子体CVD、旋涂或其他合适的方法形成在SOI衬底上。层间介质层250的材料可以包括SiO2、碳掺杂SiO2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。层间介质层250的厚度范围可以是40nm~150nm,如80nm、100nm或120nm。
对该半导体器件上的层间介质层250和伪栅堆叠进行化学机械抛光(Chemical-mechanical polish,CMP)的平坦化处理,如图7所示,使得该伪栅堆叠的上表面与层间介质层250的上表面齐平,并露出所述伪栅270的顶部和侧墙210。如后面将描述的,层间介质层250在后续的应力引发离子的注入过程中将起到注入屏蔽层的作用。
之后,执行步骤S103,去除伪栅堆叠形成栅极凹陷。去除伪栅270,形成栅极凹陷220,如图8所示。可以用刻蚀的方法去除伪栅270。
之后,执行步骤S104,通过所述栅极凹陷对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷正下方形成位于所述SOI衬底的BOX层之下的应力引发区。参考图9,通过所述栅极凹陷220对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷正下方形成位于所述SOI衬底的BOX层之下的应力引发区。例如,通过传统的离子注入工艺进行碳注入,控制其能量。在所述栅极凹陷位置,碳离子将穿过栅介质层、SOI层和BOX层,进入BOX层下方的体硅层中。而在其他位置,碳离子将被层间介质层250吸收,因此层间介质层250在此注入过程中作为注入屏蔽层。之后进行高温退火,以激活碳,形成应力引发区150,例如可以采用激光退火、闪光退火等,来激活半导体结构中的掺杂物。在一个实施例中,可以采用瞬间退火工艺对半导体结构进行退火,例如在大约800~1100℃的高温下进行激光退火。退火还可以修复碳注入对SOI层、BOX层和接地层的损伤。
应力引发区150形成在栅极介质层260正下方的SOI衬底内,贯穿接地层140,并延伸至体硅层130内,应力引发区150的上平面不高于SOI衬底的BOX层110的下平面。应力引发区150的形成可以为沟道区引入压应力,显著提高p型半导体器件的性能。
如下文所述,由于在后续步骤中将在栅极凹陷的位置处形成栅极,因此应力引发区150的位置处于之后将形成的栅极的正下方。因此,上述应力引发离子的注入可以认为是自对准的。
参考图10,之后在所述栅极凹陷处形成栅极。首先,去除所述栅极凹陷处原有的栅极介质层260;之后在SOI层100上形成新的栅极介质层280;在所述栅极介质层280上形成覆盖所述新的栅极介质层280的栅极金属层200。其中,栅极金属层的材料可以选用TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTa中的一种或其组合,其厚度在5nm~20nm之间。栅极结构可以通过化学气相沉积(Chemical vapor deposition,CVD)、高密度等离子体CVD、ALD(原子层淀积)、等离子体增强原子层淀积(PEALD)、脉冲激光沉积(PLD)或其他合适的方法依次沉积栅极介质层280和栅极金属层200之后进行平坦化而形成。
可选的,还可以在上述形成的半导体结构中进一步形成第一接触塞230和第二接触塞240,用于形成电连接。具体形成步骤包括:分别在介质层250中形成暴露至少部分源/漏区160的第一接触孔,以及暴露至少部分接地层140的第二接触孔。贯穿介质层250以及隔离区120的第二接触停止在接地层140上并暴露至少部分接地层140,另一贯穿源/漏区160之上的介质层250的第一接触孔暴露至少部分源/漏区160。在一次使用干法刻蚀、湿法刻蚀或其他合适的刻蚀方式刻蚀介质层250形成第一接触孔和第二接触孔的过程中,可以将接地层140的上平面作为刻蚀第二接触孔的停止层,同时将源/漏区160的上平面作为刻蚀第一接触孔的停止层,因此刻蚀第一接触孔和第二接触孔都分别具有对应的停止层,这样对刻蚀工艺的控制性要求降低,即降低了刻蚀的难度。后续加工中通常在第一接触孔和第二接触孔内填充金属,形成第一接触塞230和第二接触塞240,如图11所示。优选地,填充金属为W,当然根据半导体的制造需要,所述金属的材料还可以选用W、Al、TiAl合金中任一种或其组合。
本发明提供的半导体结构及其制造方法在超薄SOI衬底上的接地层中形成应力引发区,为半导体器件的沟道提供了有利应力,在减小短沟道效应的同时,显著提高了半导体器件的性能。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (12)
1.一种半导体结构的制造方法,包括:
a)提供SOI衬底,该SOI衬底从上至下包括基底层(130),BOX层(110)和SOI层(100);
b)在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层;
c)去除伪栅堆叠形成栅极凹陷(220);
d)通过所述栅极凹陷(220)对半导体结构进行应力引发离子的注入并进行退火,在栅极凹陷(220)正下方形成位于所述SOI衬底的BOX(110)层之下的应力引发区(150)。
2.根据权利要求1所述的方法,在步骤a)中还包括:通过离子注入和退火工艺形成接地层。
3.根据权利要求1所述的方法,在步骤b)中所述伪栅堆叠至少包括伪栅(270)。
4.根据权利要求3所述的方法,在形成伪栅堆叠之后还包括在所述伪栅堆叠的两侧形成侧墙(210)。
5.根据权利要求3所述的方法,在形成伪栅堆叠之后还包括形成源/漏区(160)。
6.根据权利要求1所述的方法,在步骤b)中注入屏蔽层为层间介质层。
7.根据权利要求1所述方法,在步骤d)之后还包括在栅极凹陷中形成栅极介质层和栅极金属层。
8.根据权利要求1所述的方法,其中应力引发离子为碳离子。
9.根据权利要求1或8所述方法,其中通过自对准的方式对半导体结构进行应力引发离子的注入。
10.一种半导体结构,包括:
SOI衬底,从上至下包括SOI层(100)、BOX层(110)和体硅层(130);
形成于SOI层(100)之上的栅极堆叠,包括栅极(200)和栅极介质层(260);
应力引发区(150),形成在所述栅极(200)正下方的体硅层(130)内。
11.根据权利要求10所述的半导体结构,其特征在于,应力引发区(150)中包含碳离子。
12.根据权利要求10所述的半导体结构,其特征在于,所述体硅层(130)中包括接地层,所述接地层靠近所述BOX层(110)。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210591064.4A CN103811349A (zh) | 2012-11-06 | 2012-11-06 | 半导体结构及其制造方法 |
PCT/CN2013/080537 WO2014071754A1 (zh) | 2012-11-06 | 2013-07-31 | 半导体结构及其制造方法 |
US14/439,165 US20150270399A1 (en) | 2012-11-06 | 2013-07-31 | Semiconductor structure and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210591064.4A CN103811349A (zh) | 2012-11-06 | 2012-11-06 | 半导体结构及其制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103811349A true CN103811349A (zh) | 2014-05-21 |
Family
ID=50684014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210591064.4A Pending CN103811349A (zh) | 2012-11-06 | 2012-11-06 | 半导体结构及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20150270399A1 (zh) |
CN (1) | CN103811349A (zh) |
WO (1) | WO2014071754A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9799675B2 (en) * | 2014-04-02 | 2017-10-24 | International Business Machines Corporation | Strain engineering in back end of the line |
US9768254B2 (en) * | 2015-07-30 | 2017-09-19 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US9691669B1 (en) * | 2015-08-28 | 2017-06-27 | Pdf Solutions, Inc. | Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies |
US9577102B1 (en) * | 2015-09-25 | 2017-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming gate and finFET |
US20190051565A1 (en) * | 2017-08-10 | 2019-02-14 | Globalfoundries Inc. | Cmos devices and manufacturing method thereof |
CN111435684B (zh) * | 2019-01-14 | 2023-05-23 | 联华电子股份有限公司 | 具有应变通道的晶体管及其制作方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020090768A1 (en) * | 2001-01-09 | 2002-07-11 | Fariborz Assaderaghi | Ground-plane device with back oxide topography |
CN1467795A (zh) * | 2002-06-07 | 2004-01-14 | ������������ʽ���� | 半导体衬底的制造方法和半导体器件的制造方法 |
US20050059201A1 (en) * | 2003-09-12 | 2005-03-17 | International Business Machines Corporation | Mosfet performance improvement using deformation in soi structure |
US20070128820A1 (en) * | 2005-12-05 | 2007-06-07 | Intel Corporation | Apparatus and method of fabricating a MOSFET transistor having a self-aligned implant |
CN101523608A (zh) * | 2006-05-24 | 2009-09-02 | 国际商业机器公司 | 包括双应力源的n沟道mosfet及其制造方法 |
CN102110710A (zh) * | 2009-12-23 | 2011-06-29 | 中国科学院微电子研究所 | 形成有沟道应力层的半导体结构及其形成方法 |
CN102623405A (zh) * | 2011-01-30 | 2012-08-01 | 中国科学院微电子研究所 | 一种形成半导体结构的方法 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3462301B2 (ja) * | 1995-06-16 | 2003-11-05 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
US6072217A (en) * | 1998-06-11 | 2000-06-06 | Sun Microsystems, Inc. | Tunable threshold SOI device using isolated well structure for back gate |
US6258695B1 (en) * | 1999-02-04 | 2001-07-10 | International Business Machines Corporation | Dislocation suppression by carbon incorporation |
US6391752B1 (en) * | 2000-09-12 | 2002-05-21 | Taiwan Semiconductor Manufacturing, Co., Ltd. | Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane |
US6562666B1 (en) * | 2000-10-31 | 2003-05-13 | International Business Machines Corporation | Integrated circuits with reduced substrate capacitance |
US8450806B2 (en) * | 2004-03-31 | 2013-05-28 | International Business Machines Corporation | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby |
US7253071B2 (en) * | 2004-06-02 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide |
US7268049B2 (en) * | 2004-09-30 | 2007-09-11 | International Business Machines Corporation | Structure and method for manufacturing MOSFET with super-steep retrograded island |
US7696000B2 (en) * | 2006-12-01 | 2010-04-13 | International Business Machines Corporation | Low defect Si:C layer with retrograde carbon profile |
DE102008006961A1 (de) * | 2008-01-31 | 2009-08-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen eines verformten Kanalgebiets in einem Transistor durch eine tiefe Implantation einer verformungsinduzierenden Sorte unter das Kanalgebiet |
FR2932609B1 (fr) * | 2008-06-11 | 2010-12-24 | Commissariat Energie Atomique | Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable |
KR20100038631A (ko) * | 2008-10-06 | 2010-04-15 | 주식회사 하이닉스반도체 | 반도체 장치 제조 방법 |
US8324074B2 (en) * | 2009-09-11 | 2012-12-04 | International Business Machines Corporation | Structure and method to minimize regrowth and work function shift in high-k gate stacks |
TWI419324B (zh) * | 2009-11-27 | 2013-12-11 | Univ Nat Chiao Tung | 具有三五族通道及四族源汲極之半導體裝置及其製造方法 |
US8133781B2 (en) * | 2010-02-15 | 2012-03-13 | International Business Machines Corporation | Method of forming a buried plate by ion implantation |
CN101924139B (zh) * | 2010-06-25 | 2012-05-30 | 北京大学 | 一种应变沟道场效应晶体管及其制备方法 |
US8232162B2 (en) * | 2010-09-13 | 2012-07-31 | International Business Machines Corporation | Forming implanted plates for high aspect ratio trenches using staged sacrificial layer removal |
US8633096B2 (en) * | 2010-11-11 | 2014-01-21 | International Business Machines Corporation | Creating anisotropically diffused junctions in field effect transistor devices |
US20120146142A1 (en) * | 2010-12-14 | 2012-06-14 | Institute of Microelectronics, Chinese Acaademy of Sciences | Mos transistor and method for manufacturing the same |
US8901537B2 (en) * | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
US8519454B2 (en) * | 2011-03-30 | 2013-08-27 | International Business Machines Corporation | Structure and process for metal fill in replacement metal gate integration |
US8691650B2 (en) * | 2011-04-14 | 2014-04-08 | International Business Machines Corporation | MOSFET with recessed channel film and abrupt junctions |
US9633854B2 (en) * | 2011-06-23 | 2017-04-25 | Institute of Microelectronics, Chinese Academy of Sciences | MOSFET and method for manufacturing the same |
US8716799B2 (en) * | 2011-06-23 | 2014-05-06 | Institute of Microelectronics, Chinese Academy of Sciences | Mosfet |
US8513081B2 (en) * | 2011-10-13 | 2013-08-20 | International Business Machines Corporation | Carbon implant for workfunction adjustment in replacement gate transistor |
CN103377930B (zh) * | 2012-04-19 | 2015-11-25 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
US9012997B2 (en) * | 2012-10-26 | 2015-04-21 | International Business Machines Corporation | Semiconductor device including ESD protection device |
-
2012
- 2012-11-06 CN CN201210591064.4A patent/CN103811349A/zh active Pending
-
2013
- 2013-07-31 US US14/439,165 patent/US20150270399A1/en not_active Abandoned
- 2013-07-31 WO PCT/CN2013/080537 patent/WO2014071754A1/zh active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020090768A1 (en) * | 2001-01-09 | 2002-07-11 | Fariborz Assaderaghi | Ground-plane device with back oxide topography |
CN1467795A (zh) * | 2002-06-07 | 2004-01-14 | ������������ʽ���� | 半导体衬底的制造方法和半导体器件的制造方法 |
US20050059201A1 (en) * | 2003-09-12 | 2005-03-17 | International Business Machines Corporation | Mosfet performance improvement using deformation in soi structure |
US20070128820A1 (en) * | 2005-12-05 | 2007-06-07 | Intel Corporation | Apparatus and method of fabricating a MOSFET transistor having a self-aligned implant |
CN101523608A (zh) * | 2006-05-24 | 2009-09-02 | 国际商业机器公司 | 包括双应力源的n沟道mosfet及其制造方法 |
CN102110710A (zh) * | 2009-12-23 | 2011-06-29 | 中国科学院微电子研究所 | 形成有沟道应力层的半导体结构及其形成方法 |
CN102623405A (zh) * | 2011-01-30 | 2012-08-01 | 中国科学院微电子研究所 | 一种形成半导体结构的方法 |
Also Published As
Publication number | Publication date |
---|---|
US20150270399A1 (en) | 2015-09-24 |
WO2014071754A1 (zh) | 2014-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8329566B2 (en) | Method of manufacturing a high-performance semiconductor device | |
CN102117750B (zh) | Mosfet结构及其制作方法 | |
CN103311247B (zh) | 半导体器件及其制造方法 | |
US8994119B2 (en) | Semiconductor device with gate stacks having stress and method of manufacturing the same | |
US8853024B2 (en) | Method of manufacturing semiconductor device | |
CN103928327B (zh) | 鳍式场效应晶体管及其形成方法 | |
US9018739B2 (en) | Semiconductor device and method of fabricating the same | |
CN109148578B (zh) | 半导体结构及其形成方法 | |
US20140203363A1 (en) | Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance | |
CN103811349A (zh) | 半导体结构及其制造方法 | |
CN103489779B (zh) | 半导体结构及其制造方法 | |
US8420489B2 (en) | High-performance semiconductor device and method of manufacturing the same | |
CN103943502B (zh) | 鳍式场效应晶体管及其形成方法 | |
CN103377946B (zh) | 一种半导体结构及其制造方法 | |
CN103377930B (zh) | 半导体结构及其制造方法 | |
CN102315268A (zh) | 半导体器件及其制造方法 | |
US20120326155A1 (en) | Semiconductor structure and method for manufacturing the same | |
US11605726B2 (en) | Semiconductor structure and method for forming the same | |
US9012963B2 (en) | Semiconductor device | |
US20160190318A1 (en) | Semiconductor device and manufacturing method thereof | |
CN102956647B (zh) | 半导体器件及其制造方法 | |
CN103377931B (zh) | 半导体结构及其制造方法 | |
CN104576378A (zh) | 一种mosfet结构及其制造方法 | |
CN104576381A (zh) | 一种非对称超薄soimos晶体管结构及其制造方法 | |
CN103779212A (zh) | 半导体结构及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140521 |