CN111435684B - 具有应变通道的晶体管及其制作方法 - Google Patents

具有应变通道的晶体管及其制作方法 Download PDF

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CN111435684B
CN111435684B CN201910030931.9A CN201910030931A CN111435684B CN 111435684 B CN111435684 B CN 111435684B CN 201910030931 A CN201910030931 A CN 201910030931A CN 111435684 B CN111435684 B CN 111435684B
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substrate
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layer
gate
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CN111435684A (zh
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杨柏宇
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种具有应变通道的晶体管及其制作方法，该半导体元件包含：一基底，具有一上表面；一源极区域，设于该基底中；一漏极区域，设于该基底中；一凹槽，介于该源极区域与该漏极区域之间，从该基底的该上表面延伸进入该基底中，其中该凹槽具有一六角形剖面轮廓；一应力诱发材料层，设于该凹槽内；一通道层，设于该应力诱发材料层上；以及一栅极结构，设于该通道层上。

Description

具有应变通道的晶体管及其制作方法
技术领域
本发明涉及半导体制作工艺技术领域，特别是有关于一种具有应变通道(strained channel)的晶体管及其制作方法。
背景技术
已知，在晶体管的结构中提供不同类型的应力(stress)可以增加通道区域中电荷载流子的迁移率(mobility)。例如，对通道区域提供拉伸(tensile)应力可以增加电子的迁移率，进而增加导电性并提升操作速度。对通道区域提供压缩(compressive)应力可以增加空洞的迁移率，从而增强晶体管的效能。
通常，针对N型晶体管，是将压缩应力引入通道区域，而针对P型晶体管，则是将拉伸应力引入通道区域。在现有技术中已经提出了各种结构在其相应的通道区域中引入应力，然而现有技术可能会有对不准的问题。
发明内容
本发明提供了一种改良的半导体结构及其制作方法，可以有效的在N型晶体管中将压缩应力引入其通道区域，而在P型晶体管中将拉伸应力引入其通道区域，而不会有对不准的问题。
本发明一方面提供一种形成半导体结构的方法。首先提供一基底，具有一上表面。在该基底上形成一第一牺牲栅极。在该第一牺牲栅极的侧壁上形成间隙壁。在该基底中，邻近该第一牺牲栅极处，形成一源极区域与一漏极区域。在该源极区域与该漏极区域之间形成一通道区域。在该基底上形成一停止层，其中该停止层顺形的覆盖该间隙壁、该第一牺牲栅极、该源极区域及该漏极区域。去除该第一牺牲栅极，在该间隙壁之间的该通道区域上形成一栅极沟槽。经由该栅极沟槽蚀刻该基底，在该源极区域与该漏极区域之间形成一凹槽，并从该基底的该上表面延伸进入该基底中，其中该凹槽具有一六角形剖面轮廓。在该凹槽内形成一应力诱发材料层。在该应力诱发材料层上外延成长出一通道层。在该通道层上形成一栅极结构。
本发明一方面提供一种半导体元件，包含：一基底，具有一上表面；一源极区域，设于该基底中；一漏极区域，设于该基底中；一凹槽，介于该源极区域与该漏极区域之间，从该基底的该上表面延伸进入该基底中，其中该凹槽具有一六角形剖面轮廓；一应力诱发材料层，设于该凹槽内；一通道层，设于该应力诱发材料层上；以及一栅极结构，设于该通道层上。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图7为本发明实施例所绘示的形成半导体结构的方法的剖面示意图。
主要元件符号说明
100 基底
100a 上表面
101 NMOS区域
102 PMOS区域
103 隔离区域
110 N型阱
130 沟槽绝缘结构
2 NMOS晶体管
21 牺牲栅极
21’ 金属栅极结构
200 通道区域
201 N型轻掺杂漏极(NLDD)区
210 多晶硅层
210’ 金属层
212 栅极介电层
212’ 栅极介电层
214 氮化硅盖层
216 间隙壁
220 栅极沟槽
221、221a 凹槽
3 PMOS晶体管
31 牺牲栅极
31’ 金属栅极结构
300 通道区域
301 P型轻掺杂漏极(PLDD)区
310 多晶硅层
310’ 金属层
312 栅极介电层
312’ 栅极介电层
314 氮化硅盖层
316 间隙壁
321、321a 凹陷结构
40 停止层
416 间隙壁
50 光致抗蚀剂图案
501、502 开口
601、602 应力诱发材料层
701 外延硅层(通道层)
702 外延硅层
NS 源极区域
ND 漏极区域
PS 源极区域
PD 漏极区域
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图7，其为依据本发明实施例所绘示的形成半导体结构的方法的剖面示意图。如图1所示，首先，提供一基底100，例如，P型硅基底，但不限于此。基底100可以包含一NMOS区域101、一PMOS区域102以及一隔离区域103。在隔离区域103内形成有一沟槽绝缘结构130，用来将NMOS区域101与PMOS区域102彼此隔离开。基底100包含一上表面100a。在PMOS区域102内可以形成有一N型阱110。
根据本发明实施例，在NMOS区域101内形成有一NMOS晶体管2，包含一牺牲栅极21，例如，多晶硅栅极。例如，牺牲栅极21可以包括一多晶硅层210、一栅极介电层212以及一氮化硅盖层214，但不限于此。在牺牲栅极21的各侧壁上可以设有一间隙壁216，例如，氮化硅间隙壁，但不限于此。在基底100中，邻近牺牲栅极21处，另形成有源极区域NS与漏极区域ND。
根据本发明实施例，源极区域NS与漏极区域ND可以是N型重掺杂区。此外，源极区域NS与漏极区域ND可以另包含有一N型轻掺杂漏极(NLDD)区201，位于间隙壁216正下方。根据本发明实施例，在源极区域NS与漏极区域ND之间形成有一通道区域200。
根据本发明实施例，在PMOS区域102内形成有一PMOS晶体管3，包含一牺牲栅极31，例如，多晶硅栅极。例如，牺牲栅极31可以包括一多晶硅层310、一栅极介电层312以及一氮化硅盖层314。在牺牲栅极31的各侧壁上可以设有一间隙壁316，例如，氮化硅间隙壁，但不限于此。在基底100中，邻近牺牲栅极31处，另形成有P型轻掺杂漏极(PLDD)区301。在P型轻掺杂漏极(PLDD)区301之间的牺牲栅极31正下方设有一通道区域300。
接着，在基底100上形成一停止层40，例如，氮化硅层，可以作为一蚀刻停止层。停止层40顺形的覆盖NMOS区域101、PMOS区域102及隔离区域103。例如，在NMOS区域101内，停止层40顺形的覆盖间隙壁216、牺牲栅极21、源极区域NS及漏极区域ND。在PMOS区域102内，停止层40顺形的覆盖间隙壁316、牺牲栅极31及PLDD区301。
如图2所示，接着可以进行光刻制作工艺及蚀刻制作工艺，去除牺牲栅极21，在间隙壁216之间的通道区域200上形成一栅极沟槽220。例如，先在停止层40上形成一光致抗蚀剂图案(图未示)，其具有一开口，位于牺牲栅极21正上方，然后，经由该开口蚀刻停止层40以及牺牲栅极21，将多晶硅层210、栅极介电层212以及氮化硅盖层214去除，形成栅极沟槽220，并显露出通道区域200。然后，去除上述光致抗蚀剂图案。
如图3所示，接着，在基底10上形成一光致抗蚀剂图案50，覆盖NMOS区域101、PMOS区域102及隔离区域103。光致抗蚀剂图案50包含一开口501，位于NMOS区域101中，对准栅极沟槽220，以及一开口502，位于PMOS区域102中，显露出PMOS晶体管3的牺牲栅极31以及邻近牺牲栅极31的至少部分PLDD区301。
接着，进行一各向异性干蚀刻制作工艺，经由开口501及栅极沟槽220蚀刻基底100，在源极区域NS与漏极区域ND之间形成一凹槽221，同时，经由开口502，在基底100中，邻近牺牲栅极31处，形成一凹陷结构321。凹槽221及凹陷结构321从基底100的上表面100a延伸进入基底100中至一第一预定深度。接着，去除光致抗蚀剂图案50。上述各向异性干蚀刻制作工艺会先经由开口502蚀刻停止层40，形成间隙壁416。
然后，如图4所示，进行一湿蚀刻制作工艺，继续蚀刻凹槽221及凹陷结构321，以形成一增宽的凹槽221a及增宽的凹陷结构321a。上述湿蚀刻制作工艺可以包括含羟基(OH)的物质，包括，但不限于，氢氧化钾、氢氧化四甲基铵(TMAH)或氢氧化钠。凹槽221a及凹陷结构321a及从基底100的上表面100a延伸进入基底100中至一第二预定深度。根据本发明实施例，第二预定深度不会比源极区域NS与漏极区域ND最下方的接面还要深。根据本发明实施例，凹槽221a及凹陷结构321a可以具有一六角形剖面轮廓。
如图5所示，接着于凹槽221a内形成一应力诱发材料层601，同时于凹陷结构321a形成一应力诱发材料层602。根据本发明实施例，应力诱发材料层601、602包含硅锗(SiGe)层。应力诱发材料层601、602可以利用选择性外延法形成，但不限于此。
接着，进行一外延制作工艺，在应力诱发材料层601及应力诱发材料层602上分别外延成长出外延硅层701及外延硅层702，其中外延硅层701为结晶硅层，可作为NMOS晶体管2的一通道层。外延硅层702则作为PMOS晶体管3的源极/漏极结构的一部分。
后续，可以继续进行源极和漏极的重掺杂离子注入，在PMOS区域102内形成源极区域PS和漏极区域PD。例如，源极区域PS和漏极区域PD可以是P型重掺杂区。
如图6所示，接着进行一化学气相沉积(chemical vapor depoistion，CVD)制作工艺，全面沉积一层间介电层80，例如，硅氧层或低介电常数材料层。层间介电层80覆盖停止层40以及PMOS区域102内的牺牲栅极31、外延硅层702，且层间介电层80填入栅极沟槽220中。可以另对层间介电层80进行一平坦化制作工艺，例如，化学机械研磨(CMP)制作工艺。
接着，可以进行光刻制作工艺及蚀刻制作工艺，将层间介电层80从栅极沟槽220中去除，显露出外延硅层701(通道层)，同时，将牺牲栅极31去除，形成栅极沟槽320，显露出通道区域300。
如图7所示，接着于栅极沟槽220内的外延硅层701(通道层)上形成一金属栅极结构21’，同时，在栅极沟槽320内的通道区域300上形成一金属栅极结构31’。根据本发明实施例，金属栅极结构21’可以包含一金属层210’及一栅极介电层212’，金属栅极结构31’可以包含一金属层310’及一栅极介电层312’，但不限于此。应理解的是，图7中的金属栅极结构21’及金属栅极结构31’仅为例示说明，在其他实施例中，金属栅极结构21’及金属栅极结构31’可以不同结构。
结构上，例如，如图7所示，NMOS晶体管2包含：一基底100，具有一上表面100a；一源极区域NS，设于基底100中；一漏极区域ND，设于基底100中；一凹槽221a，介于源极区域NS与漏极区域ND之间，从基底100的上表面100a延伸进入基底100中至一预定深度，其中凹槽221a具有一六角形剖面轮廓；一应力诱发材料层601，设于凹槽221a内；一通道层701，设于应力诱发材料层601上；以及一金属栅极结构21’，设于通道层701上。基底100是P型基底，又其中源极区域NS与漏极区域ND均为N型掺杂区域。
NMOS晶体管2另包含间隙壁216，设于金属栅极结构21’的侧壁上。NMOS晶体管2另包含一停止层40，位于基底100上，其中停止层40顺形的覆盖间隙壁216、源极区域NS与漏极区域ND。根据本发明实施例，停止层40包含氮化硅层，应力诱发材料层601包含硅锗层，通道层701包含结晶硅层。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种形成半导体结构的方法，包含：
提供基底，具有上表面，该基底包含NMOS区域和PMOS区域；
在该基底上的该NMOS区域内形成第一牺牲栅极，在该基底上的该PMOS区域内形成第二牺牲栅极；
在该第一牺牲栅极和该第二牺牲栅极的侧壁上形成间隙壁；
在该基底中的该NMOS区域内，邻近该第一牺牲栅极处，形成N型源极区域与N型漏极区域；
在该N型源极区域与该N型漏极区域之间形成通道区域；
去除该第一牺牲栅极，在该间隙壁之间的该通道区域上形成栅极沟槽；
经由该栅极沟槽蚀刻该基底，在该N型源极区域与该N型漏极区域之间形成凹槽，并从该基底的该上表面延伸进入该基底中，其中该凹槽具有六角形剖面轮廓；
在该基底中，邻近该第二牺牲栅极处，形成凹陷结构，其中该栅极沟槽与该凹陷结构是同时形成；
在该NMOS区域中的该凹槽内形成应力诱发材料层；
在该NMOS区域内的该应力诱发材料层上外延成长出通道层；以及
在该NMOS区域内的该栅极沟槽中的该通道层上形成栅极结构。
2.如权利要求1所述的方法，其中该基底为P型基底。
3.如权利要求1所述的方法，其中该牺牲栅极包含多晶硅栅极。
4.如权利要求1所述的方法，还包括在该基底上形成停止层，其中该停止层顺形的覆盖该间隙壁、该第一牺牲栅极、该N型源极区域及该N型漏极区域。
5.如权利要求4所述的方法，其中该停止层包含氮化硅层。
6.如权利要求4所述的方法，其中另包含：
在该应力诱发材料层上外延成长出该通道层之后，全面沉积层间介电层，其中该层间介电层覆盖该停止层并填入该栅极沟槽中；以及
将该层间介电层从该栅极沟槽去除，以显露出该通道层。
7.如权利要求1所述的方法，其中该应力诱发材料层包含硅锗层。
8.如权利要求1所述的方法，其中该通道层包含结晶硅层。
9.一种半导体元件，其特征在于，包含：
基底，具有上表面，该基底包含NMOS区域和PMOS区域；
N型源极区域和N型漏极区域，设于该基底中的该NMOS区域内；
P型源极区域和P型漏极区域，设于该基底中的该PMOS区域内；
凹槽，介于该N型源极区域与该N型漏极区域之间，从该基底的该上表面延伸进入该基底中，其中该凹槽具有六角形剖面轮廓；
凹陷结构，位于该P型源极区域和该P型漏极区域中，其中该凹陷结构具有六角形剖面轮廓；
应力诱发材料层，设于该凹槽和该凹陷结构内；
通道层，设于该NMOS区域内的该应力诱发材料层上；以及
栅极结构，设于该通道层上。
10.如权利要求9所述的半导体元件，其中该基底是P型基底。
11.如权利要求9所述的半导体元件，其中另包含间隙壁，设于该栅极结构的侧壁上。
12.如权利要求11所述的半导体元件，其中另包含停止层，位于该基底上，其中该停止层顺形的覆盖该间隙壁、该源极区域与该漏极区域。
13.如权利要求12所述的半导体元件，其中该停止层包含氮化硅层。
14.如权利要求9所述的半导体元件，其中该应力诱发材料层包含硅锗层。
15.如权利要求9所述的半导体元件，其中该通道层包含结晶硅层。
16.如权利要求9所述的半导体元件，其中该栅极结构包含金属栅极。
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